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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r13-20020aa79ecd000000b00667e17e30ddsi1095671pfq.339.2023.06.20.00.40.08; Tue, 20 Jun 2023 00:40:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kS1h8p0U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230452AbjFTHe4 (ORCPT + 99 others); Tue, 20 Jun 2023 03:34:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230252AbjFTHe2 (ORCPT ); Tue, 20 Jun 2023 03:34:28 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CFE5188; Tue, 20 Jun 2023 00:34:25 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35K5PpGW009732; Tue, 20 Jun 2023 07:33:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=2+FYJqvd8KPGLBxHJyZuzJMgY6Vqc6U1VDQqXT1I4S0=; b=kS1h8p0U+9Otp44mTrDOjTMhh/b0v9kx67ofv0cYSyikaA1oZzDwxIgonkwWMp0sAAZA fzcO4pfkcvOx6xBQQcq6qMNSflW8F8l5HgnuaKwQTG3DuSla3ev40qxgoZ4OpHiaS2Yn NyCDcBi6oI7ZoiQH/ZMh7u8Zx9J4AE6Neog0qkMN5WdV139yjHWcHiMJMuiUJx5mpeYf mrqC9Re9zF2fisBoqnmTJbqU1kT6+eBygdA4osEurtkb9LnrVMxeNyEkp3XS0Sx4UV90 udDvELqSJE5jVdBkZr2YmoD1zeV3NYn+rx91VDS9C6jMy0lV74XnCN0+vZ7R1meuIJdg CA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rarwes9y4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Jun 2023 07:33:32 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35K7XUTM000602 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Jun 2023 07:33:30 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 20 Jun 2023 00:33:10 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v6 01/13] coresight-tpdm: Remove the unnecessary lock Date: Tue, 20 Jun 2023 15:32:29 +0800 Message-ID: <1687246361-23607-2-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1687246361-23607-1-git-send-email-quic_taozha@quicinc.com> References: <1687246361-23607-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dUjUVHFAUIS7sAEQJCs2FAgw_b1dBeno X-Proofpoint-ORIG-GUID: dUjUVHFAUIS7sAEQJCs2FAgw_b1dBeno X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-20_04,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 malwarescore=0 bulkscore=0 phishscore=0 impostorscore=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306200067 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769206525106456781?= X-GMAIL-MSGID: =?utf-8?q?1769206525106456781?= Remove the unnecessary lock "CS_{UN,}LOCK" in TPDM driver. This lock is only needed while writing the data to Coresight registers. Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-tpdm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index f4854af..b645612 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -114,11 +114,9 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) { u32 pidr; - CS_UNLOCK(drvdata->base); /* Get the datasets present on the TPDM. */ pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0); - CS_LOCK(drvdata->base); } /* From patchwork Tue Jun 20 07:32:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 110286 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3493501vqr; Tue, 20 Jun 2023 00:45:57 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ42Co4MWJn1Mqy+brhOX2GtXuNrtfb1nFwE+9Df27LhIyxpnFYSqOxQrZJZt/gIht1SOO0m X-Received: by 2002:a05:6808:f02:b0:39e:d865:3b6a with SMTP id m2-20020a0568080f0200b0039ed8653b6amr6671119oiw.52.1687247156897; Tue, 20 Jun 2023 00:45:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687247156; cv=none; d=google.com; s=arc-20160816; b=QPpZ49FHglxmoMfBHpbICTwRVhSfsmylAW+5KoQScIsG7lY+qxe1z78iY1DqD8703a tdnzqQizCFFnNc6KuZzU0eY9VwefGaKpFrWnFxm7BkZXdzp7z50Vux7BihJa9n5L7jA7 TiLaNfAKs5OMDf6vfEBBcImHYvdZ6WhBib8oR+V6aH9Vv/bLK/QHonTIb+o2PeeoSGaU w3GFrNiGOCagoOM6lq+vAZCv10Ej4yWs2B335NsxBaZV52sX3La7b1wQruwsZBF3ykBs Gehs2GtJP3MDS9QuWgizk3FP+k6nMRRIGWnZH9Jlj/Ge9vooB+KyKWDnuDblHdi/hr5K wtMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=DNaojRv5QWWakQ+RKLmR/fQmqSTeCpymyhCzyrB09P4=; b=Nrp7ACSNScR9IKMKUjrZUZ4VNOlMlYqTzXAWTBmIpHZfeFbRLm8b/Mg+7aC3GydrZU utDhqNE701UASeXWEmZSSHZho/pGNpmKoFlcwsJdTmTapkdkE1z3J7XhynozfALUrHW6 6tcLnwEbPp/9NMvQBojKpMh8LA3fct+v8hiwGZbv1t3BLT8IOEl82ff3JcA+iHnm3J/p xgrxBPFMOhGF4bp1F4NzwIce7GHydCJ+GQ23S62P+v7TBSAMWPOQkTHAp/5muLdIWRc6 TQyEx91oiGvzbiIXelTboOJmxMQ7Q12WVS4zfBpxS7dsst2ZmzxVGP3wkZOV7e1hc0aP 4nEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZliKwsG9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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The associated aggregator will read this size before it is enabled. DSB element size currently only supports 32-bit and 64-bit. Signed-off-by: Tao Zhang Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 5c08342..931ee8f 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -44,6 +44,14 @@ properties: minItems: 1 maxItems: 2 + qcom,dsb-element-size: + description: + Specifies the DSB(Discrete Single Bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. DSB element size currently only supports 32-bit and 64-bit. + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [32, 64] + clocks: maxItems: 1 @@ -77,6 +85,8 @@ examples: compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0684c000 0x1000>; + qcom,dsb-element-size = /bits/ 8 <32>; + clocks = <&aoss_qmp>; clock-names = "apb_pclk"; From patchwork Tue Jun 20 07:32:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 110280 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3490233vqr; Tue, 20 Jun 2023 00:36:52 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ65WvebCiWF2+dXZhy13V5fcQ2bk0a1CQT88mFIt3iKWOAcbOexUl/aeq2yPWTSYcqjHyde X-Received: by 2002:a05:6871:c18a:b0:19f:6af1:87f8 with SMTP id yr10-20020a056871c18a00b0019f6af187f8mr7400590oab.41.1687246612624; Tue, 20 Jun 2023 00:36:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687246612; cv=none; d=google.com; s=arc-20160816; b=WtEt2uWqq0IJVNL3Wt504XLo4dW2JoKlMmU+WxxTtMbVY2OFW6M/z2ao8y4fd9GUFP mOgmeYr757HiJLLMEzSum5dxcYOVaPfaij1MnI91hheZg81/0qa/brERhX7xt3fOT2Ck hPOOXKasWtIR9Yz4H01vpxvyRImOBJScmx6GwOOahDwhcQffU2Jzj3vUWcULlzU0I0bZ whqDfXPVwz+7DWL2JgbHTFsLl4TV+quFa7Xr5aCYveC7CPaTG3+59YcKnuZDTVr8q6FA I6jO0UG+3+Uz2EfcSWQemW89k07jYWEBluXiXU3OjFLeBXywCKSQXIiI5GkOHS9Xl4Zw 35lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=trSdVxH7yCeRMrhysMZXirrEmR8AVfFFCIOn6KxevXo=; b=JuWNLAhIq1BbfXC/kIzeg8WeH8onzppSHyHg8dxGMPZ2TTej0N61rQZ9aIN01qHsN/ srvuagmgzHxCf5wwtRYR6htaG2qAimweVpTRVs1y8NffTQtIoc/GoA/rRoC72W1SmtDT C8A89I8C//0eRZVCfArkIr/IGmEh7EyKb4QoKQtOGx5CqDIYZPKY3BHFO8jfNJtaiThr n4VRjy/szDWn8IydGlnJ9Dw0JDyP3PqrS8nUEgoOLfNbrPSzSILZs5E/nHKUEglW63Zt qS34/ZZzWB9DAUg6FOEo5TloahdkN5AodsoLZYg5NIRXxllflg/p/hgr+v56bDoOwzLp N/Bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=CIHTSjSW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-tpdm.c | 2 +- include/linux/coresight.h | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 118fcf2..a8c52aa 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1093,6 +1093,7 @@ static int coresight_validate_source(struct coresight_device *csdev, if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC && subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE && + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM && subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS) { dev_err(&csdev->dev, "wrong device subtype in %s\n", function); return -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index b645612..abaff0b 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -203,7 +203,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) if (!desc.name) return -ENOMEM; desc.type = CORESIGHT_DEV_TYPE_SOURCE; - desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS; + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM; desc.ops = &tpdm_cs_ops; desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 949aa24..29cd6d8 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -61,6 +61,7 @@ enum coresight_dev_subtype_source { CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, + CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM, CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, }; From patchwork Tue Jun 20 07:32:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 110283 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3492009vqr; Tue, 20 Jun 2023 00:41:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4xv8eZsRgs4gx/npfjlzvGGB/fuZg8oLALx9gaEsCY20rMYE2wbc86+PMCSn3G+jEW5Duj X-Received: by 2002:a17:90a:3983:b0:25c:a3f:3adb with SMTP id z3-20020a17090a398300b0025c0a3f3adbmr11513372pjb.9.1687246903776; Tue, 20 Jun 2023 00:41:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687246903; cv=none; d=google.com; s=arc-20160816; b=egT7ZpeF6uCm+TtwPPhj5uKxgZyeYKItXD1IhbKJVk4SduOQf6ql3dPZxgowrPrcat h58knKbJMcOs8wtQHh6LPa2qVn77BY2Bsl6uAcb87A/3njWI0qP/IBh45shzNHdd7gLu 0MX2FmdWIW67uKcArWBBt7/OZ5xS8/LOKwe87aSgTEteyBWaUrRJiNItxP+9D5WCU8IA SexWPmFqFNmw1OK5bQ1Vmio1JV2wN7gru3o8iQm+dArcRTad6WpWPrRvW643Z+hzfYSj 62jE5Hw9QpD0GNIuVrpgrnS2Jj8eBEUckDZuR4MtEmq1M/HPhX+GPvskAfco7ZeI8S5K UCLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+BKdWwEWwdwCoPZPNCBpNs8qGJS3GBIA2guIKe9oTqs=; b=IvrmxVuI9b5pdb7amGVwBMBo2hU190qhJy/LmqI2a5xID74sgcYo/2AH8kLPCrbK8F M7+Wo3kSzmQ1UigsvgADTFqCbbF+lzGuUokguoCA1qwtRRchqLA5PNyn08TXHYwzu9qe TBTWM3+VRZVTGs/Bis8SYypDzMWJlJtks+SaoNmHk7OGE3fTE/HAiaEnN53xCfKKLuGw 5VjwMH4ig1SjZ3/Fhs115KO9Co5n4UmntmPQ1pNPGo4e/hohKn1JXNDA+BVmz4J/UZGr 4S/p9FRGIAzbtqRrBN8BGui0C+Vr02P2QlN/ju4qMS2KkvF+q+T+1ZVjNC0bQz2cb7dx snJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Kbk1KZ95; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Set the register bit that controls the DSB element size of the corresponding port. Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-tpda.c | 96 +++++++++++++++++++++++++--- drivers/hwtracing/coresight/coresight-tpda.h | 4 ++ 2 files changed, 90 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 8d2b9d2..7c71342 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -21,6 +21,58 @@ DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda"); +/* Search and read element data size from the TPDM node in + * the devicetree. Each input port of TPDA is connected to + * a TPDM. Different TPDM supports different types of dataset, + * and some may support more than one type of dataset. + * Parameter "inport" is used to pass in the input port number + * of TPDA, and it is set to 0 in the recursize call. + * Parameter "parent" is used to pass in the original call. + */ +static int tpda_set_element_size(struct tpda_drvdata *drvdata, + struct coresight_device *csdev, int inport, bool match_inport) +{ + static int nr_inport; + int i; + static bool tpdm_found; + struct coresight_device *in_csdev; + + if (inport > (TPDA_MAX_INPORTS - 1)) + return -EINVAL; + + if (match_inport) { + nr_inport = inport; + tpdm_found = false; + } + + for (i = 0; i < csdev->pdata->nr_inconns; i++) { + in_csdev = csdev->pdata->in_conns[i]->src_dev; + if (!in_csdev) + break; + + if (match_inport) + if (csdev->pdata->in_conns[i]->dest_port != inport) + continue; + + if ((in_csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && + (in_csdev->subtype.source_subtype + == CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM)) { + of_property_read_u8(in_csdev->dev.parent->of_node, + "qcom,dsb-element-size", &drvdata->dsb_esize[nr_inport]); + if (!tpdm_found) + tpdm_found = true; + else + dev_warn(drvdata->dev, + "More than one TPDM is mapped to the TPDA input port %d.\n", + nr_inport); + continue; + } + tpda_set_element_size(drvdata, in_csdev, 0, false); + } + + return 0; +} + /* Settings pre enabling port control register */ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) { @@ -32,26 +84,43 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDA_CR); } -static void tpda_enable_port(struct tpda_drvdata *drvdata, int port) +static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) { u32 val; val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + /* + * Configure aggregator port n DSB data set element size + * Set the bit to 0 if the size is 32 + * Set the bit to 1 if the size is 64 + */ + if (drvdata->dsb_esize[port] == 32) + val &= ~TPDA_Pn_CR_DSBSIZE; + else if (drvdata->dsb_esize[port] == 64) + val |= TPDA_Pn_CR_DSBSIZE; + else + return -EINVAL; + /* Enable the port */ val |= TPDA_Pn_CR_ENA; writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); + + return 0; } -static void __tpda_enable(struct tpda_drvdata *drvdata, int port) +static int __tpda_enable(struct tpda_drvdata *drvdata, int port) { + int ret; + CS_UNLOCK(drvdata->base); if (!drvdata->csdev->enable) tpda_enable_pre_port(drvdata); - tpda_enable_port(drvdata, port); - + ret = tpda_enable_port(drvdata, port); CS_LOCK(drvdata->base); + + return ret; } static int tpda_enable(struct coresight_device *csdev, @@ -59,16 +128,23 @@ static int tpda_enable(struct coresight_device *csdev, struct coresight_connection *out) { struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; + + ret = tpda_set_element_size(drvdata, csdev, in->dest_port, true); + if (ret) + return ret; spin_lock(&drvdata->spinlock); - if (atomic_read(&in->dest_refcnt) == 0) - __tpda_enable(drvdata, in->dest_port); + if (atomic_read(&in->dest_refcnt) == 0) { + ret = __tpda_enable(drvdata, in->dest_port); + if (!ret) { + atomic_inc(&in->dest_refcnt); + dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", in->dest_port); + } + } - atomic_inc(&in->dest_refcnt); spin_unlock(&drvdata->spinlock); - - dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", in->dest_port); - return 0; + return ret; } static void __tpda_disable(struct tpda_drvdata *drvdata, int port) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index 0399678..12a1472 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,8 @@ #define TPDA_Pn_CR(n) (0x004 + (n * 4)) /* Aggregator port enable bit */ #define TPDA_Pn_CR_ENA BIT(0) +/* Aggregator port DSB data set element size bit */ +#define TPDA_Pn_CR_DSBSIZE BIT(8) #define TPDA_MAX_INPORTS 32 @@ -23,6 +25,7 @@ * @csdev: component vitals needed by the framework. * @spinlock: lock for the drvdata value. * @enable: enable status of the component. + * @dsb_esize: DSB element size for each inport, it must be 32 or 64. */ struct tpda_drvdata { void __iomem *base; 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Events are something that occurs at some point in time. It could be a state decode, the act of writing/reading a particular address, a FIFO being empty, etc. This decoding of the event desired is done outside TPDM. DSB subunit need to be configured in enablement and disablement. A struct that specifics associated to dsb dataset is needed. It saves the configuration and parameters of the dsb datasets. This change is to add this struct and initialize the configuration of DSB subunit. Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-tpdm.c | 55 ++++++++++++++++++++++++++-- drivers/hwtracing/coresight/coresight-tpdm.h | 18 +++++++++ 2 files changed, 69 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index abaff0b..52aa48a6 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,17 +20,46 @@ DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); +static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) +{ + if (drvdata->datasets & TPDM_PIDR0_DS_DSB) { + memset(drvdata->dsb, 0, sizeof(struct dsb_dataset)); + + drvdata->dsb->trig_ts = true; + drvdata->dsb->trig_type = false; + } +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val; - /* Set the enable bit of DSB control register to 1 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); + /* Set trigger timestamp */ + if (drvdata->dsb->trig_ts) + val |= TPDM_DSB_TIER_XTRIG_TSENAB; + else + val &= ~TPDM_DSB_TIER_XTRIG_TSENAB; + writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + /* Set trigger type */ + if (drvdata->dsb->trig_type) + val |= TPDM_DSB_CR_TRIG_TYPE; + else + val &= ~TPDM_DSB_CR_TRIG_TYPE; + /* Set the enable bit of DSB control register to 1 */ val |= TPDM_DSB_CR_ENA; writel_relaxed(val, drvdata->base + TPDM_DSB_CR); } -/* TPDM enable operations */ +/* TPDM enable operations + * The TPDM or Monitor serves as data collection component for various + * dataset types. It covers Basic Counts(BC), Tenure Counts(TC), + * Continuous Multi-Bit(CMB), Multi-lane CMB(MCMB) and Discrete Single + * Bit(DSB). This function will initialize the configuration according + * to the dataset type supported by the TPDM. + */ static void __tpdm_enable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base); @@ -110,13 +139,24 @@ static const struct coresight_ops tpdm_cs_ops = { .source_ops = &tpdm_source_ops, }; -static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) +static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) { u32 pidr; /* Get the datasets present on the TPDM. */ pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0); + + if (drvdata->datasets & TPDM_PIDR0_DS_DSB) { + if (!drvdata->dsb) { + drvdata->dsb = devm_kzalloc(drvdata->dev, + sizeof(*drvdata->dsb), GFP_KERNEL); + if (!drvdata->dsb) + return -ENOMEM; + } + } + + return 0; } /* @@ -179,6 +219,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) struct coresight_platform_data *pdata; struct tpdm_drvdata *drvdata; struct coresight_desc desc = { 0 }; + int ret; pdata = coresight_get_platform_data(dev); if (IS_ERR(pdata)) @@ -198,6 +239,12 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) drvdata->base = base; + ret = tpdm_datasets_setup(drvdata); + if (ret) + return ret; + + tpdm_reset_datasets(drvdata); + /* Set up coresight component description */ desc.name = coresight_alloc_device_name(&tpdm_devs, dev); if (!desc.name) @@ -214,7 +261,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(drvdata->csdev); spin_lock_init(&drvdata->spinlock); - tpdm_init_default_data(drvdata); + /* Decrease pm refcount when probe is done.*/ pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 5438540..92c34cd 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -11,8 +11,14 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) +#define TPDM_DSB_TIER (0x784) + /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) +/* Enable bit for DSB subunit trigger type */ +#define TPDM_DSB_CR_TRIG_TYPE BIT(12) +/* Enable bit for DSB subunit trigger timestamp */ +#define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1) /* TPDM integration test registers */ #define TPDM_ITATBCNTRL (0xEF0) @@ -41,6 +47,16 @@ #define TPDM_PIDR0_DS_DSB BIT(1) /** + * struct dsb_dataset - specifics associated to dsb dataset + * @trig_ts: Enable/Disable trigger timestamp. + * @trig_type: Enable/Disable trigger type. + */ +struct dsb_dataset { + bool trig_ts; + bool trig_type; +}; + +/** * struct tpdm_drvdata - specifics associated to an TPDM component * @base: memory mapped base address for this component. * @dev: The device entity associated to this component. @@ -48,6 +64,7 @@ * @spinlock: lock for the drvdata value. * @enable: enable status of the component. * @datasets: The datasets types present of the TPDM. + * @dsb Specifics associated to an TPDM component. */ struct tpdm_drvdata { @@ -57,6 +74,7 @@ struct tpdm_drvdata { spinlock_t spinlock; bool enable; unsigned long datasets; + struct dsb_dataset *dsb; }; #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ From patchwork Tue Jun 20 07:32:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 110285 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3492632vqr; Tue, 20 Jun 2023 00:43:33 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6jGWNyNjuhyVs1w7Wo76Zs3gK8B2tbViSjdEegjzHnm6Ru5XFPneDpiwYq4JBmCws5jinC X-Received: by 2002:a05:6a20:3c86:b0:10b:bf2d:71bb with SMTP id b6-20020a056a203c8600b0010bbf2d71bbmr17322649pzj.27.1687247013210; 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This change provides a node to reset the configurations and disable the TPDM if it has been enabled. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 10 ++++++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 22 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 4a58e64..dbc2fbd0 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -11,3 +11,13 @@ Description: Accepts only one of the 2 values - 1 or 2. 1 : Generate 64 bits data 2 : Generate 32 bits data + +What: /sys/bus/coresight/devices//reset +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Reset the dataset of the tpdm, and disable the tpdm. + + Accepts only one value - 1. + 1 : Reset the dataset of the tpdm diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 52aa48a6..acc3eea 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -159,6 +159,27 @@ static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) return 0; } +static ssize_t reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int ret = 0; + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 10, &val); + if (ret || val != 1) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + tpdm_reset_datasets(drvdata); + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_WO(reset); + /* * value 1: 64 bits test data * value 2: 32 bits test data @@ -199,6 +220,7 @@ static ssize_t integration_test_store(struct device *dev, static DEVICE_ATTR_WO(integration_test); static struct attribute *tpdm_attrs[] = { + &dev_attr_reset.attr, &dev_attr_integration_test.attr, NULL, }; From patchwork Tue Jun 20 07:32:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 110279 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3489953vqr; Tue, 20 Jun 2023 00:36:09 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7oX9xjm2X19DQQMZHP9o8ohLQyey/I1BBUHOCxeW9ZHY3sa/7L8nML0d2DU2pkU/o6BTcr X-Received: by 2002:a17:90b:3187:b0:25e:9b1b:dee9 with SMTP id hc7-20020a17090b318700b0025e9b1bdee9mr9791464pjb.8.1687246568732; Tue, 20 Jun 2023 00:36:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687246568; cv=none; d=google.com; s=arc-20160816; b=jgVHiC7VE7QTbujkh7jYJlmh/p3JVPcZ+spt4MhjFPxzv1sh/aFUpvCPc2BvEZv2Rg wvY8hpTrAJ0nqNLJINjdrz2dBwL8HzgC/hG8tHxLelqoDq9EDqFpecYuOQS0pTALXVNo 1WI5BvDAChNNP4X+/qqnojKsDvy99NoiN+VTs3/bqevhBLqKUgJ0iFyYmdRU0NkyttIz UkN2MROGnwTzX4mKpoMp4tFvBRvubk2+cPUShlbSg8kBQCOWUmxBoCasUfW/DTo94jNH +CyDav73JIG+84MBVIUZ2UEKQzneu0gOT5tAl/R9ZPdqII/CMROqIUB82myZSVFQv2ZA I0gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=DfyZCmPJgINc2vFaG8QlV7pWGi3oWtmNllEgbtOpkTY=; b=oUB+zB39m8c0AQca5mAY110ZD5hAE4h5JJv3eDUFRkHIbC6JYP89suKIHXbiHFmsgU 2IrhAMBMIURkomCeHgVW9zmqis0dIn3vTMW/kXLvyxh9x9ETTD1V33pNAHISk5KSGaPI 1gWm2OnMlGjwkdW+xB7utRPLXaMEgMfrUds0I3ibi1NeGG0KB+KZd2jJVvYI/kz8reJr CgtolCF419BzAvmVt4vq4Sbyq4TxUd9hIIZDWXuphU2z+/gG+r2YzuBFcC5UUNjzdYzJ vqImPcdS0mBR0giprNNHJZUAdEwphbMJpSqXArPwFsFR2YTf2z1alqpTFofNBlmi2bG6 B/pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Iyq2XA8Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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This change is to add these nodes to achieve these function. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 24 ++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 94 ++++++++++++++++++++++ 2 files changed, 118 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index dbc2fbd0..0b7b4ad 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -21,3 +21,27 @@ Description: Accepts only one value - 1. 1 : Reset the dataset of the tpdm + +What: /sys/bus/coresight/devices//dsb_trig_type +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the trigger type of DSB tpdm. Read the trigger + type of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB trigger type to false + 1 : Set the DSB trigger type to true + +What: /sys/bus/coresight/devices//dsb_trig_ts +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the trigger timestamp of DSB tpdm. Read the + trigger timestamp of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB trigger type to false + 1 : Set the DSB trigger type to true diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index acc3eea..62efc18 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,6 +20,18 @@ DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); +static umode_t tpdm_dsb_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (drvdata && (drvdata->datasets & TPDM_PIDR0_DS_DSB)) + return attr->mode; + + return 0; +} + static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (drvdata->datasets & TPDM_PIDR0_DS_DSB) { @@ -229,8 +241,90 @@ static struct attribute_group tpdm_attr_grp = { .attrs = tpdm_attrs, }; +static ssize_t dsb_trig_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->trig_type); +} + +/* + * Trigger type (boolean): + * false - Disable trigger type. + * true - Enable trigger type. + */ +static ssize_t dsb_trig_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->dsb->trig_type = true; + else + drvdata->dsb->trig_type = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_type); + +static ssize_t dsb_trig_ts_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->trig_ts); +} + +/* + * Trigger timestamp (boolean): + * false - Disable trigger timestamp. + * true - Enable trigger timestamp. + */ +static ssize_t dsb_trig_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->dsb->trig_ts = true; + else + drvdata->dsb->trig_ts = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_ts); + +static struct attribute *tpdm_dsb_attrs[] = { + &dev_attr_dsb_trig_ts.attr, + &dev_attr_dsb_trig_type.attr, + NULL, +}; + +static struct attribute_group tpdm_dsb_attr_grp = { + .attrs = tpdm_dsb_attrs, + .is_visible = tpdm_dsb_is_visible, +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, + &tpdm_dsb_attr_grp, NULL, }; From patchwork Tue Jun 20 07:32:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 110301 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3495785vqr; Tue, 20 Jun 2023 00:52:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5u6TCJ6rW9X4tYC6d9WMcPvxSYAFNx2S5e/uzmP8Y8IHCSaKmTFNCjDviESXMZ6gtGpBpE X-Received: by 2002:a05:620a:45ab:b0:763:b7c5:139e with SMTP id bp43-20020a05620a45ab00b00763b7c5139emr19530qkb.47.1687247558921; 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Once the DSB programming mode is set, it will be written to the register DSB_CR. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 15 ++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 62 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 16 ++++++ 3 files changed, 93 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 0b7b4ad..2a82cd0 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -45,3 +45,18 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : Set the DSB trigger type to false 1 : Set the DSB trigger type to true + +What: /sys/bus/coresight/devices//dsb_mode +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the mode of DSB tpdm. Read the mode of DSB + tpdm. + + Accepts the value needs to be greater than 0. What data + bits do is listed below. + Bit[0:1] : Test mode control bit for choosing the inputs. + Bit[3] : Set to 0 for low performance mode. + Set to 1 for high performance mode. + Bit[4:8] : Select byte lane for high performance mode. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 62efc18..c38760b 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -42,6 +43,32 @@ static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) } } +static void set_dsb_test_mode(struct tpdm_drvdata *drvdata, u32 *val) +{ + u32 mode; + + mode = TPDM_DSB_MODE_TEST(drvdata->dsb->mode); + *val &= ~TPDM_DSB_TEST_MODE; + *val |= FIELD_PREP(TPDM_DSB_TEST_MODE, mode); +} + +static void set_dsb_hpsel_mode(struct tpdm_drvdata *drvdata, u32 *val) +{ + u32 mode; + + mode = TPDM_DSB_MODE_HPBYTESEL(drvdata->dsb->mode); + *val &= ~TPDM_DSB_HPSEL; + *val |= FIELD_PREP(TPDM_DSB_HPSEL, mode); +} + +static void set_dsb_perf_mode(struct tpdm_drvdata *drvdata, u32 *val) +{ + if (drvdata->dsb->mode & TPDM_DSB_MODE_PERF) + *val |= TPDM_DSB_CR_MODE; + else + *val &= ~TPDM_DSB_CR_MODE; +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val; @@ -55,6 +82,12 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + /* Set the test accurate mode */ + set_dsb_test_mode(drvdata, &val); + /* Set the byte lane for high-performance mode */ + set_dsb_hpsel_mode(drvdata, &val); + /* Set the performance mode */ + set_dsb_perf_mode(drvdata, &val); /* Set trigger type */ if (drvdata->dsb->trig_type) val |= TPDM_DSB_CR_TRIG_TYPE; @@ -241,6 +274,34 @@ static struct attribute_group tpdm_attr_grp = { .attrs = tpdm_attrs, }; +static ssize_t dsb_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%lx\n", + (unsigned long)drvdata->dsb->mode); +} + +static ssize_t dsb_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || val < 0) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->mode = val & TPDM_DSB_MODE_MASK; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_mode); + static ssize_t dsb_trig_type_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -312,6 +373,7 @@ static ssize_t dsb_trig_ts_store(struct device *dev, static DEVICE_ATTR_RW(dsb_trig_ts); static struct attribute *tpdm_dsb_attrs[] = { + &dev_attr_dsb_mode.attr, &dev_attr_dsb_trig_ts.attr, &dev_attr_dsb_trig_type.attr, NULL, diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 92c34cd..49fffb1 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -15,11 +15,25 @@ /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) +/* Enable bit for DSB subunit perfmance mode */ +#define TPDM_DSB_CR_MODE BIT(1) /* Enable bit for DSB subunit trigger type */ #define TPDM_DSB_CR_TRIG_TYPE BIT(12) + /* Enable bit for DSB subunit trigger timestamp */ #define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1) +/* DSB programming modes */ +/* Test mode control bit*/ +#define TPDM_DSB_MODE_TEST(val) (val & GENMASK(1, 0)) +/* Performance mode */ +#define TPDM_DSB_MODE_PERF BIT(3) +/* High performance mode */ +#define TPDM_DSB_MODE_HPBYTESEL(val) (val & GENMASK(8, 4)) +#define TPDM_DSB_MODE_MASK GENMASK(8, 0) +#define TPDM_DSB_TEST_MODE GENMASK(10, 9) +#define TPDM_DSB_HPSEL GENMASK(6, 2) + /* TPDM integration test registers */ #define TPDM_ITATBCNTRL (0xEF0) #define TPDM_ITCNTRL (0xF00) @@ -48,10 +62,12 @@ /** * struct dsb_dataset - specifics associated to dsb dataset + * @mode: DSB programming mode * @trig_ts: Enable/Disable trigger timestamp. * @trig_type: Enable/Disable trigger type. */ struct dsb_dataset { + u32 mode; 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Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. DSB edge detection control 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask. Eight 32 bit registers providing DSB interface edge detection mask control. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ drivers/hwtracing/coresight/coresight-tpdm.c | 143 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ 3 files changed, 196 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 2a82cd0..34189e4a 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -60,3 +60,35 @@ Description: Bit[3] : Set to 0 for low performance mode. Set to 1 for high performance mode. Bit[4:8] : Select byte lane for high performance mode. + +What: /sys/bus/coresight/devices//dsb_edge_ctrl +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read/Write a set of the edge control registers of the DSB + in TPDM. + + Expected format is the following: + + + Where: + : Start EDCR register number + : End EDCR register number + : The value need to be written + +What: /sys/bus/coresight/devices//dsb_edge_ctrl_mask +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + Read/Write a set of the edge control mask registers of the + DSB in TPDM. + + Expected format is the following: + + + Where: + : Start EDCMR register number + : End EDCMR register number + : The value need to be written diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index c38760b..fc92900 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -71,7 +71,14 @@ static void set_dsb_perf_mode(struct tpdm_drvdata *drvdata, u32 *val) static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { - u32 val; + u32 val, i; + + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) + writel_relaxed(drvdata->dsb->edge_ctrl[i], + drvdata->base + TPDM_DSB_EDCR(i)); + for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) + writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], + drvdata->base + TPDM_DSB_EDCMR(i)); val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); /* Set trigger timestamp */ @@ -302,6 +309,138 @@ static ssize_t dsb_mode_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_mode); +static ssize_t dsb_edge_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { + bytes = sysfs_emit_at(buf, size, + "Index:0x%x Val:0x%x\n", i, + drvdata->dsb->edge_ctrl[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +/* + * value 1: Start EDCR register number + * value 2: End EDCR register number + * value 3: The value need to be written + * The EDCR registers can include up to 16 32-bit registers, and each + * one can be configured to control up to 16 edge detections(2 bits + * control one edge detection). So a total 256 edge detections can be + * configured. So the starting number(value 1) and ending number(value 2) + * cannot be greater than 256, and value 1 should be less than value 2. + * The following values are the rage of value 3. + * 0 - Rising edge detection + * 1 - Falling edge detection + * 2 - Rising and falling edge detection (toggle detection) + */ +static ssize_t dsb_edge_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val, mask, start, end, edge_ctrl; + int i, reg; + + if (sscanf(buf, "%lx %lx %lx", &start, &end, &edge_ctrl) != 3) + return -EINVAL; + if ((start >= TPDM_DSB_MAX_LINES) || (end >= TPDM_DSB_MAX_LINES) || + (start > end) || (edge_ctrl > 0x2)) + return -EPERM; + + spin_lock(&drvdata->spinlock); + for (i = start; i <= end; i++) { + /* + * There are 2 bit per DSB Edge Control line. + * Thus we have 16 lines in a 32bit word. + */ + reg = EDCR_TO_WORD_IDX(i); + mask = EDCR_TO_WORD_MASK(i); + val = drvdata->dsb->edge_ctrl[reg]; + val &= ~EDCR_TO_WORD_MASK(i); + val |= EDCR_TO_WORD_VAL(edge_ctrl, i); + drvdata->dsb->edge_ctrl[reg] = val; + } + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_RW(dsb_edge_ctrl); + +static ssize_t dsb_edge_ctrl_mask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) { + bytes = sysfs_emit_at(buf, size, + "Index:0x%x Val:0x%x\n", i, + drvdata->dsb->edge_ctrl_mask[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +/* + * value 1: Start EDCMR register number + * value 2: End EDCMR register number + * value 3: The value need to be written + */ +static ssize_t dsb_edge_ctrl_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long start, end, val; + u32 set; + int i, reg; + + if (sscanf(buf, "%lx %lx %lx", &start, &end, &val) != 3) + return -EINVAL; + if ((start >= TPDM_DSB_MAX_LINES) || (end >= TPDM_DSB_MAX_LINES) + || (start > end) || (val & ~1UL)) + return -EPERM; + + spin_lock(&drvdata->spinlock); + for (i = start; i <= end; i++) { + /* + * There is 1 bit per DSB Edge Control Mark line. + * Thus we have 32 lines in a 32bit word. + */ + reg = EDCMR_TO_WORD_IDX(i); + set = drvdata->dsb->edge_ctrl_mask[reg]; + if (val) + set |= BIT(EDCR_TO_WORD_SHIFT(i)); + else + set &= ~BIT(EDCR_TO_WORD_SHIFT(i)); + drvdata->dsb->edge_ctrl_mask[reg] = set; + } + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_edge_ctrl_mask); + static ssize_t dsb_trig_type_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -374,6 +513,8 @@ static DEVICE_ATTR_RW(dsb_trig_ts); static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, + &dev_attr_dsb_edge_ctrl.attr, + &dev_attr_dsb_edge_ctrl_mask.attr, &dev_attr_dsb_trig_ts.attr, &dev_attr_dsb_trig_type.attr, NULL, diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 49fffb1..f81bfe8 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) +#define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) +#define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) @@ -34,6 +36,16 @@ #define TPDM_DSB_TEST_MODE GENMASK(10, 9) #define TPDM_DSB_HPSEL GENMASK(6, 2) +#define EDCRS_PER_WORD 16 +#define EDCR_TO_WORD_IDX(r) ((r) / EDCRS_PER_WORD) +#define EDCR_TO_WORD_SHIFT(r) ((r % EDCRS_PER_WORD) * 2) +#define EDCR_TO_WORD_VAL(val, r) (val << EDCR_TO_WORD_SHIFT(r)) +#define EDCR_TO_WORD_MASK(r) EDCR_TO_WORD_VAL(0x3, r) + +#define EDCMRS_PER_WORD 32 +#define EDCMR_TO_WORD_IDX(r) ((r) / EDCMRS_PER_WORD) +#define EDCMR_TO_WORD_SHIFT(r) ((r) % EDCMRS_PER_WORD) + /* TPDM integration test registers */ #define TPDM_ITATBCNTRL (0xEF0) #define TPDM_ITCNTRL (0xF00) @@ -60,14 +72,24 @@ #define TPDM_PIDR0_DS_IMPDEF BIT(0) #define TPDM_PIDR0_DS_DSB BIT(1) +#define TPDM_DSB_MAX_LINES 256 +/* MAX number of EDCR registers */ +#define TPDM_DSB_MAX_EDCR 16 +/* MAX number of EDCMR registers */ +#define TPDM_DSB_MAX_EDCMR 8 + /** * struct dsb_dataset - specifics associated to dsb dataset * @mode: DSB programming mode + * @edge_ctrl: Save value for edge control + * @edge_ctrl_mask: Save value for edge control mask * @trig_ts: Enable/Disable trigger timestamp. * @trig_type: Enable/Disable trigger type. */ struct dsb_dataset { u32 mode; + u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; + u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; bool trig_ts; bool trig_type; }; From patchwork Tue Jun 20 07:32:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 110278 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3489864vqr; Tue, 20 Jun 2023 00:35:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4+fsrh75YJzlMFsz4F8NiEBZ6PHuapIWjrSA6iqMx3i6bRsHzYmv++64mU/7G2NEBHHvCs X-Received: by 2002:a05:6a00:1911:b0:659:ae1c:c9e2 with SMTP id y17-20020a056a00191100b00659ae1cc9e2mr9081328pfi.17.1687246553169; Tue, 20 Jun 2023 00:35:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687246553; cv=none; d=google.com; s=arc-20160816; b=PI0nX43qwemkfdtB9zt9tN7DM28zfyfdI88PMickFv1Wpfa3E16+y/pl9FHSLdrg1k gouLDQJHk+Rj+1zrzpMHoiC6GCYAGXMwkl5WEeHPP+q7Ty4lcV8y8tihIlbAERzE8zDy qWZ1M7V0NOczFyuAjZya9pCLp7b7XCEggetkL52Alh8ckUjgyP5xO+R+DpzKiYiicGaK nkDRUPLMOmDxKUgu53FXykxuJAtWvjKnF7RfTHcoIdOXcfSvPSBeNAQE2bFU/iQ2CHow 1yknIeeufVB74SmW1K3DD2pHFGhF/X99OWXo364Rdd+TKbvFvea8K7bE5AHd8aLnGln+ ToHg== ARC-Message-Signature: i=1; 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Each DSB subunit TPDM has maximum of n(n<7) XPR registers to configure trigger pattern match output. Eight 32 bit registers providing DSB interface trigger output pattern match comparison. And each DSB subunit TPDM has maximum of m(m<7) XPMR registers to configure trigger pattern mask match output. Eight 32 bit registers providing DSB interface trigger output pattern match mask. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 28 +++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 93 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++- 3 files changed, 131 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 34189e4a..55ec81d 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -92,3 +92,31 @@ Description: : Start EDCMR register number : End EDCMR register number : The value need to be written + +What: /sys/bus/coresight/devices//dsb_trig_patt_val +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the trigger pattern value of DSB tpdm. + Read the trigger pattern value of DSB tpdm. + + Expected format is the following: + + + Where: + : Index number of XPR register, the range is 0 to 7 + +What: /sys/bus/coresight/devices//dsb_trig_patt_mask +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the trigger pattern mask of DSB tpdm. + Read the trigger pattern mask of DSB tpdm. + + Expected format is the following: + + + Where: + : Index number of XPMR register, the range is 0 to 7 diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index fc92900..974e63f 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -80,6 +80,13 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], drvdata->base + TPDM_DSB_EDCMR(i)); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + writel_relaxed(drvdata->dsb->trig_patt_val[i], + drvdata->base + TPDM_DSB_XPR(i)); + writel_relaxed(drvdata->dsb->trig_patt_mask[i], + drvdata->base + TPDM_DSB_XPMR(i)); + } + val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); /* Set trigger timestamp */ if (drvdata->dsb->trig_ts) @@ -441,6 +448,90 @@ static ssize_t dsb_edge_ctrl_mask_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_edge_ctrl_mask); +static ssize_t dsb_trig_patt_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i = 0; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + bytes = sysfs_emit_at(buf, size, + "Index: 0x%x Value: 0x%x\n", i, + drvdata->dsb->trig_patt_val[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +static ssize_t dsb_trig_patt_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index, val; + + if (sscanf(buf, "%lx %lx", &index, &val) != 2) + return -EINVAL; + if (index >= TPDM_DSB_MAX_PATT) + return -EPERM; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->trig_patt_val[index] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_patt_val); + +static ssize_t dsb_trig_patt_mask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i = 0; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + bytes = sysfs_emit_at(buf, size, + "Index: 0x%x Value: 0x%x\n", i, + drvdata->dsb->trig_patt_mask[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +static ssize_t dsb_trig_patt_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index, val; + + if (sscanf(buf, "%lx %lx", &index, &val) != 2) + return -EINVAL; + if (index >= TPDM_DSB_MAX_PATT) + return -EPERM; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->trig_patt_mask[index] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_patt_mask); + static ssize_t dsb_trig_type_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -515,6 +606,8 @@ static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_edge_ctrl.attr, &dev_attr_dsb_edge_ctrl_mask.attr, + &dev_attr_dsb_trig_patt_val.attr, + &dev_attr_dsb_trig_patt_mask.attr, &dev_attr_dsb_trig_ts.attr, &dev_attr_dsb_trig_type.attr, NULL, diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index f81bfe8..87d946e 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) +#define TPDM_DSB_XPR(n) (0x7C8 + (n * 4)) +#define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) #define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) @@ -77,19 +79,25 @@ #define TPDM_DSB_MAX_EDCR 16 /* MAX number of EDCMR registers */ #define TPDM_DSB_MAX_EDCMR 8 +/* MAX number of DSB pattern */ +#define TPDM_DSB_MAX_PATT 8 /** * struct dsb_dataset - specifics associated to dsb dataset * @mode: DSB programming mode * @edge_ctrl: Save value for edge control * @edge_ctrl_mask: Save value for edge control mask + * @trig_patt_val: Save value for trigger pattern + * @trig_patt_mask: Save value for trigger pattern mask * @trig_ts: Enable/Disable trigger timestamp. * @trig_type: Enable/Disable trigger type. */ struct dsb_dataset { u32 mode; - u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; - u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; + u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; + u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; + u32 trig_patt_val[TPDM_DSB_MAX_PATT]; + u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; bool trig_ts; bool trig_type; }; From patchwork Tue Jun 20 07:32:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 110290 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3494723vqr; Tue, 20 Jun 2023 00:49:30 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5uKM2DdjN+EtPcPQfttiAH6gtQXZL4eUBfPZZEj6pM3/n/7HazkRRaIrRPyxGEpKbEAH5g X-Received: by 2002:a05:6358:ce26:b0:12b:c8d5:f10b with SMTP id gt38-20020a056358ce2600b0012bc8d5f10bmr3785038rwb.29.1687247370522; Tue, 20 Jun 2023 00:49:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687247370; cv=none; d=google.com; s=arc-20160816; b=SDZXsDmFZA6SWlYFRlHQb9bcM64OAIwxRaPdhH/HRwGG7ia4pcbUQ3PPgU9jgd6w2u kTHVYA2DZI9h6EvYogZp5xlug3bPmmQqULoSBm1uSKcVQobE3acFhVrPVjDeeasEbZzG GH84JSR7JXChvkh5BN5o3GuB+3aDYUhB/VRDe4AznCPxcNKTqyEqQ2oXeVhaDfdRJH2w KDJjQcKyVFJ1qgHI7ZRkLNlnss9ZdTXFP2SxfJYx8rkyMF0yQA6WPMd3p1HrR78i5bEG jGlzOMnvPsvEVT7cs+9Zi994RKNEf8/f1xLLCYQDLel9q1/cMf8SseTOSeBVw8V0z+Je ObYg== ARC-Message-Signature: i=1; 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Each TPDM that support DSB subunit has maximum of n(n<7) TPR registers to configure value for timestamp request based on input pattern match. Eight 32 bit registers providing DSB interface timestamp request pattern match comparison. And each TPDM that support DSB subunit has maximum of m(m<7) TPMR registers to configure pattern mask for timestamp request. Eight 32 bit registers providing DSB interface timestamp request pattern match mask generation. Add nodes to enable/disable pattern timestamp and set pattern timestamp type. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 46 +++++ drivers/hwtracing/coresight/coresight-tpdm.c | 187 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 14 ++ 3 files changed, 242 insertions(+), 5 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 55ec81d..6e1b246 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -120,3 +120,49 @@ Description: Where: : Index number of XPMR register, the range is 0 to 7 + +What: /sys/bus/coresight/devices//dsb_patt_val +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the pattern value of DSB tpdm. Read + the pattern value of DSB tpdm. + + Accepts the following two values. + value 1: Index number of TPR register, the range is 0 to 7 + +What: /sys/bus/coresight/devices//dsb_patt_mask +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the pattern mask of DSB tpdm. Read + the pattern mask of DSB tpdm. + + Accepts the following two values. + value 1: Index number of TPMR register, the range is 0 to 7 + +What: /sys/bus/coresight/devices//dsb_patt_ts +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the pattern timestamp of DSB tpdm. Read + the pattern timestamp of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Disable DSB pattern timestamp. + 1 : Enable DSB pattern timestamp. + +What: /sys/bus/coresight/devices//dsb_patt_type +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the pattern type of DSB tpdm. Read + the pattern type of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB pattern type to value. + 1 : Set the DSB pattern type to toggle. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 974e63f..1aff244 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -69,6 +69,27 @@ static void set_dsb_perf_mode(struct tpdm_drvdata *drvdata, u32 *val) *val &= ~TPDM_DSB_CR_MODE; } +static void set_dsb_tier(struct tpdm_drvdata *drvdata, u32 *val) +{ + /* Set pattern timestamp type and enablement */ + if (drvdata->dsb->patt_ts) { + *val |= TPDM_DSB_TIER_PATT_TSENAB; + if (drvdata->dsb->patt_type) + *val |= TPDM_DSB_TIER_PATT_TYPE; + else + *val &= ~TPDM_DSB_TIER_PATT_TYPE; + } else { + *val &= ~TPDM_DSB_TIER_PATT_TSENAB; + } + + /* Set trigger timestamp */ + if (drvdata->dsb->trig_ts) + *val |= TPDM_DSB_TIER_XTRIG_TSENAB; + else + *val &= ~TPDM_DSB_TIER_XTRIG_TSENAB; + +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val, i; @@ -81,6 +102,10 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) drvdata->base + TPDM_DSB_EDCMR(i)); for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + writel_relaxed(drvdata->dsb->patt_val[i], + drvdata->base + TPDM_DSB_TPR(i)); + writel_relaxed(drvdata->dsb->patt_mask[i], + drvdata->base + TPDM_DSB_TPMR(i)); writel_relaxed(drvdata->dsb->trig_patt_val[i], drvdata->base + TPDM_DSB_XPR(i)); writel_relaxed(drvdata->dsb->trig_patt_mask[i], @@ -88,11 +113,7 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) } val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); - /* Set trigger timestamp */ - if (drvdata->dsb->trig_ts) - val |= TPDM_DSB_TIER_XTRIG_TSENAB; - else - val &= ~TPDM_DSB_TIER_XTRIG_TSENAB; + set_dsb_tier(drvdata, &val); writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); val = readl_relaxed(drvdata->base + TPDM_DSB_CR); @@ -448,6 +469,158 @@ static ssize_t dsb_edge_ctrl_mask_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_edge_ctrl_mask); +static ssize_t dsb_patt_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i = 0; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + bytes = sysfs_emit_at(buf, size, + "Index: 0x%x Value: 0x%x\n", i, + drvdata->dsb->patt_val[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +/* + * value 1: Index of TPR register + * value 2: Value need to be written + */ +static ssize_t dsb_patt_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index, val; + + if (sscanf(buf, "%lx %lx", &index, &val) != 2) + return -EINVAL; + if (index >= TPDM_DSB_MAX_PATT) + return -EPERM; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_val[index] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_patt_val); + +static ssize_t dsb_patt_mask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + unsigned long bytes; + int i = 0; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + bytes = sysfs_emit_at(buf, size, + "Index: 0x%x Value: 0x%x\n", i, + drvdata->dsb->patt_mask[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + return size; +} + +/* + * value 1: Index of TPMR register + * value 2: Value need to be written + */ +static ssize_t dsb_patt_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index, val; + + if (sscanf(buf, "%lx %lx", &index, &val) != 2) + return -EINVAL; + if (index >= TPDM_DSB_MAX_PATT) + return -EPERM; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_mask[index] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_patt_mask); + +static ssize_t dsb_patt_ts_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->patt_ts); +} + +/* + * value 1: Enable/Disable DSB pattern timestamp + */ +static ssize_t dsb_patt_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_ts = !!val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_patt_ts); + +static ssize_t dsb_patt_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->patt_type); +} + +/* + * value 1: Set DSB pattern type + */ +static ssize_t dsb_patt_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_type = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_patt_type); + static ssize_t dsb_trig_patt_val_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -606,6 +779,10 @@ static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_edge_ctrl.attr, &dev_attr_dsb_edge_ctrl_mask.attr, + &dev_attr_dsb_patt_val.attr, + &dev_attr_dsb_patt_mask.attr, + &dev_attr_dsb_patt_ts.attr, + &dev_attr_dsb_patt_type.attr, &dev_attr_dsb_trig_patt_val.attr, &dev_attr_dsb_trig_patt_mask.attr, &dev_attr_dsb_trig_ts.attr, diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 87d946e..3169fb5 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) +#define TPDM_DSB_TPR(n) (0x788 + (n * 4)) +#define TPDM_DSB_TPMR(n) (0x7A8 + (n * 4)) #define TPDM_DSB_XPR(n) (0x7C8 + (n * 4)) #define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) @@ -24,8 +26,12 @@ /* Enable bit for DSB subunit trigger type */ #define TPDM_DSB_CR_TRIG_TYPE BIT(12) +/* Enable bit for DSB subunit pattern timestamp */ +#define TPDM_DSB_TIER_PATT_TSENAB BIT(0) /* Enable bit for DSB subunit trigger timestamp */ #define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1) +/* Bit for DSB subunit pattern type */ +#define TPDM_DSB_TIER_PATT_TYPE BIT(2) /* DSB programming modes */ /* Test mode control bit*/ @@ -87,8 +93,12 @@ * @mode: DSB programming mode * @edge_ctrl: Save value for edge control * @edge_ctrl_mask: Save value for edge control mask + * @patt_val: Save value for pattern + * @patt_mask: Save value for pattern mask * @trig_patt_val: Save value for trigger pattern * @trig_patt_mask: Save value for trigger pattern mask + * @patt_ts: Enable/Disable pattern timestamp + * @patt_type: Set pattern type * @trig_ts: Enable/Disable trigger timestamp. * @trig_type: Enable/Disable trigger type. */ @@ -96,8 +106,12 @@ struct dsb_dataset { u32 mode; u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; + u32 patt_val[TPDM_DSB_MAX_PATT]; + u32 patt_mask[TPDM_DSB_MAX_PATT]; u32 trig_patt_val[TPDM_DSB_MAX_PATT]; u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; + bool patt_ts; + bool patt_type; bool trig_ts; bool trig_type; }; From patchwork Tue Jun 20 07:32:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 110284 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3492474vqr; Tue, 20 Jun 2023 00:43:09 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5LXYGRe0Ad+iGMGW3r+3XZEmeS5u0p2M7z2f1ukb3+seJV5YjSxQZCeh1U8scBdR8rTtDl X-Received: by 2002:aca:1207:0:b0:39e:aa99:3b9 with SMTP id 7-20020aca1207000000b0039eaa9903b9mr10004184ois.33.1687246989099; Tue, 20 Jun 2023 00:43:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687246989; cv=none; d=google.com; s=arc-20160816; b=djZj1277dX5/lStgs0UpeuT/mUuFCTuVAudPe6RqJlliUuTx3LP5m019ZzUCFilNJJ W/m7UoUmYnkL6uuCpuzO++L/Krhc/iC2ZBaaq9N8mBZ4N8q3GtOGR4ML0nwnz/joeybt XVcfyUqkfnz7tFTsJCmcE7jL0SvvArkwGTj5XJjrApUF+mYNertxIOvP5uascpm6u1jD RpiJP+zDToMxrfbK/LMWR4fbxbus30Pd9x/vfb04atF+6j5CACI+oYoiIwHOtUeP0JrG l9Htf2LK2p/fWUteBIvi773e/LTc0tjoRWOZ++ov9Dcpmfg9lPOUWE/KlZbflLQ/BmoG 1jeg== ARC-Message-Signature: i=1; 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It specifies the number of MSR registers supported by the DSB TDPM. Signed-off-by: Tao Zhang Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 931ee8f..d1d66bc 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -52,6 +52,15 @@ properties: $ref: /schemas/types.yaml#/definitions/uint8 enum: [32, 64] + qcom,dsb-msrs-num: + description: + Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) + registers supported by the monitor. If this property is not configured + or set to 0, it means this DSB TPDM doesn't support MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + clocks: maxItems: 1 @@ -86,6 +95,7 @@ examples: reg = <0x0684c000 0x1000>; qcom,dsb-element-size = /bits/ 8 <32>; + qcom,dsb-msrs-num = <16>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; From patchwork Tue Jun 20 07:32:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 110282 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3491807vqr; Tue, 20 Jun 2023 00:41:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6jvXz1gS69uW166E/vfjoowvPDw5UAOnkDVX7/uxLbc12P4z7Mv2cuUfwulfq7Jy0yYtVA X-Received: by 2002:a05:620a:2b46:b0:762:3c9b:d3c7 with SMTP id dp6-20020a05620a2b4600b007623c9bd3c7mr11429830qkb.18.1687246870975; Tue, 20 Jun 2023 00:41:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687246870; cv=none; d=google.com; s=arc-20160816; b=xCCie3wA9KYUmBY/nlN5ycaDKlclla1ojog5Wdme048maMtq9hmXZbD/cRSWs8jqfs SB8eFerH5nOfiZKldnKoAb2AurZxBioCXmclQZnm7r5YLI16PF4WSfWkJAbo4GHT7GsW N3ehF7pCfjFtT6/+HkUUItasFNi4GjFn73EvB+XMlGi8bjdMdAdUlYGuiU43ChcDhvF6 dZM7BULWuf0TeX2Rx1GDferYUFlfGkwlS400nnN1wpah4jSKOEkMVZ49YWTrk5b8Wdkp nX/4FdzQ8ietApHCPHUXZ+lQ3Z1BfFXKtiKzdC6kdsFSJ8OxpFb1g3qk3S0lo5V0dNm3 tTiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ygdpq5pE7M/kC6W2l6guKKRQ9h7KDDoYJZzbvOUWF+c=; b=yP+K1KiFi4Htz4RdxRQum/KElBUbpM2Kq40CfVs9VmWPFY6kC6+/qOFVAiMsdtU4xC CU17TWctVdk43/8Hft10MOS5PY8z2TdUfOr8dl7XlSKyR529zxiURf9gJWmYjxiKqpoR CZ2q9+OWfA06NsnJ66C84wi542E8Mdc9K0LN/BKkldnRpj/HjjmGZI6iomKIS2RSX0TU MTQ48OigIZ5EFjMEtaTEGjrTI6/aWIjb8uCjaObGat65G0sBsIPslh1jRyLMFZoxMug0 QBkdzX4V3kqjeoQGAjIWOrHqlo7014/kWSf4I5KwWXKuzBIuaUAvlZJyxoVHZKhaMfoA QOZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=NZ8PqvAW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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The TPDM MSR (mux select register) interface is an optional interface and associated bank of registers per TPDM subunit. The intent of mux select registers is to control muxing structures driving the TPDM’s’ various subunit interfaces. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 14 +++++ drivers/hwtracing/coresight/coresight-tpdm.c | 71 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 5 ++ 3 files changed, 90 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 6e1b246..aaf02a6 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -166,3 +166,17 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : Set the DSB pattern type to value. 1 : Set the DSB pattern type to toggle. + +What: /sys/bus/coresight/devices//dsb_msr +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the MSR(mux select register) of DSB tpdm. Read + the MSR(mux select register) of DSB tpdm. + + Expected format is the following: + + + Where: + : Index number of MSR register, the range is 0 to 31 diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 1aff244..9c5782f 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -90,6 +90,18 @@ static void set_dsb_tier(struct tpdm_drvdata *drvdata, u32 *val) } +static void set_dsb_msr(struct tpdm_drvdata *drvdata) +{ + int i; + + if (drvdata->dsb->msr_num == 0) + return; + + for (i = 0; i < drvdata->dsb->msr_num; i++) + writel_relaxed(drvdata->dsb->msr[i], + drvdata->base + TPDM_DSB_MSR(i)); +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val, i; @@ -116,6 +128,8 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) set_dsb_tier(drvdata, &val); writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); + set_dsb_msr(drvdata); + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); /* Set the test accurate mode */ set_dsb_test_mode(drvdata, &val); @@ -234,6 +248,14 @@ static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) if (!drvdata->dsb) return -ENOMEM; } + if (!of_property_read_u32(drvdata->dev->of_node, + "qcom,dsb_msr_num", &drvdata->dsb->msr_num)) { + drvdata->dsb->msr = devm_kzalloc(drvdata->dev, + (drvdata->dsb->msr_num * sizeof(*drvdata->dsb->msr)), + GFP_KERNEL); + if (!drvdata->dsb->msr) + return -ENOMEM; + } } return 0; @@ -775,6 +797,54 @@ static ssize_t dsb_trig_ts_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_trig_ts); +static ssize_t dsb_msr_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned int i; + unsigned long bytes; + ssize_t size = 0; + + if (drvdata->dsb->msr_num == 0) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < drvdata->dsb->msr_num; i++) { + bytes = sysfs_emit_at(buf, size, + "%u 0x%x\n", i, drvdata->dsb->msr[i]); + if (bytes <= 0) + break; + size += bytes; + } + spin_unlock(&drvdata->spinlock); + + return size; +} + +static ssize_t dsb_msr_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned int num, val; + int nval; + + if (drvdata->dsb->msr_num == 0) + return -EINVAL; + + nval = sscanf(buf, "%u %x", &num, &val); + if ((nval != 2) || (num >= drvdata->dsb->msr_num)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->msr[num] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_msr); + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_edge_ctrl.attr, @@ -787,6 +857,7 @@ static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_trig_patt_mask.attr, &dev_attr_dsb_trig_ts.attr, &dev_attr_dsb_trig_type.attr, + &dev_attr_dsb_msr.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 3169fb5..5372093 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -18,6 +18,7 @@ #define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) #define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) +#define TPDM_DSB_MSR(n) (0x980 + (n * 4)) /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) @@ -97,6 +98,8 @@ * @patt_mask: Save value for pattern mask * @trig_patt_val: Save value for trigger pattern * @trig_patt_mask: Save value for trigger pattern mask + * @msr_num Number of MSR supported by DSB TPDM + * @msr Save value for MSR * @patt_ts: Enable/Disable pattern timestamp * @patt_type: Set pattern type * @trig_ts: Enable/Disable trigger timestamp. @@ -110,6 +113,8 @@ struct dsb_dataset { u32 patt_mask[TPDM_DSB_MAX_PATT]; u32 trig_patt_val[TPDM_DSB_MAX_PATT]; u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; + u32 msr_num; + u32 *msr; bool patt_ts; bool patt_type; bool trig_ts;