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[8.43.85.97]) by mx.google.com with ESMTPS id p2-20020a170906604200b00988605122desi724578ejj.676.2023.06.19.23.07.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 23:07:45 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3549E385841B for ; Tue, 20 Jun 2023 06:07:36 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tndyumtaxlji0oc4xnzya.icoremail.net (zg8tndyumtaxlji0oc4xnzya.icoremail.net [46.101.248.176]) by sourceware.org (Postfix) with ESMTP id 3C6323858D1E for ; Tue, 20 Jun 2023 06:07:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3C6323858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id EwgMCgBnBcULQpFkB2IoAA--.56145S4; Tue, 20 Jun 2023 14:07:07 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai, Li Xu Subject: [PATCH] RISC-V: Set the natural size of constant vector mask modes to one RVV data vector. Date: Tue, 20 Jun 2023 06:07:05 +0000 Message-Id: <20230620060705.22235-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: EwgMCgBnBcULQpFkB2IoAA--.56145S4 X-Coremail-Antispam: 1UD129KBjvJXoWxZw47GFy5Wr18GFyxuF47twb_yoW5KFW3pa y5Gw4Yya48J3Z3W3WSkFyxJw4fCryvgw45uws5ZryUCr4rtrW7ZF1DK3y7JFykGan09r9I kw12kFy5Zw1UG3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769200696607365249?= X-GMAIL-MSGID: =?utf-8?q?1769200696607365249?= If reinterpret vnx2bi as vnx16bi, vnx16bi must occupy no more of the underlying registers than vnx2bi. Consider this following case: void test_vreinterpret_v_b64_i8m1 (uint8_t *in, int8_t *out) { vbool64_t vmask = __riscv_vlm_v_b64 (in, 2); vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1 (vmask); __riscv_vse8_v_i8m1(out, vout, 16); } compiler parameters: -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3 Compilation fails with: test_vreinterpret_v_b64_i8m1during RTL pass: expand test.c: In function 'test_vreinterpret_v_b64_i8m1': test.c:11:22: internal compiler error: in gen_lowpart_general, at rtlhooks.cc:57 11 | vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1(src); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 0xf11876 gen_lowpart_general(machine_mode, rtx_def*) ../.././riscv-gcc/gcc/rtlhooks.cc:57 0x191435e gen_vreinterpretvnx16qi(rtx_def*, rtx_def*) ../.././riscv-gcc/gcc/config/riscv/vector.md:486 0xe08858 maybe_expand_insn(insn_code, unsigned int, expand_operand*) ../.././riscv-gcc/gcc/optabs.cc:8213 0x1471209 riscv_vector::function_expander::generate_insn(insn_code) ../.././riscv-gcc/gcc/config/riscv/riscv-vector-builtins.cc:3813 0x147629c riscv_vector::function_expander::expand() ../.././riscv-gcc/gcc/config/riscv/riscv-vector-builtins.h:520 0x147629c riscv_vector::expand_builtin(unsigned int, tree_node*, rtx_def*) ../.././riscv-gcc/gcc/config/riscv/riscv-vector-builtins.cc:4103 0x9868f9 expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int) ../.././riscv-gcc/gcc/builtins.cc:7342 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_regmode_natural_size): set the natural size of vector mask mode to one rvv register. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: New test. --- gcc/config/riscv/riscv.cc | 4 ++++ .../gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c | 11 +++++++++++ 2 files changed, 15 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6eb63a9d4de..73454f65086 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7362,6 +7362,10 @@ riscv_regmode_natural_size (machine_mode mode) anything smaller than that. */ /* ??? For now, only do this for variable-width RVV registers. Doing it for constant-sized registers breaks lower-subreg.c. */ + + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) + return BYTES_PER_RISCV_VECTOR; + if (!riscv_vector_chunks.is_constant () && riscv_v_ext_mode_p (mode)) { if (riscv_v_ext_tuple_mode_p (mode)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c new file mode 100644 index 00000000000..534d5fe0f0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include "riscv_vector.h" + +void test_vreinterpret_v_b64_i8m1 (uint8_t *in, int8_t *out) +{ + vbool64_t vmask = __riscv_vlm_v_b64 (in, 2); + vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1 (vmask); + __riscv_vse8_v_i8m1(out, vout, 16); +}