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It is functionally identical to the first one already added in: 3cbe93a "arch: arm64: dts: lx2160a: describe the SerDes block #1" Signed-off-by: Josua Mayer --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index ea6a94b57aeb..2e68c05181dd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -626,6 +626,12 @@ serdes_1: phy@1ea0000 { #phy-cells = <1>; }; + serdes_2: phy@1eb0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1eb0000 0x0 0x1e30>; + #phy-cells = <1>; + }; + crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <10>; From patchwork Mon Jun 19 09:00:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 109838 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2866092vqr; Mon, 19 Jun 2023 02:13:59 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5FYFVZRtbGifFzZjC/AswCEm75yKC6zv184JzJxVdeszJjC22+QxqiprIPQ/i30toMc1lU X-Received: by 2002:a17:90a:8c15:b0:25e:a3cd:6d03 with SMTP id a21-20020a17090a8c1500b0025ea3cd6d03mr6748609pjo.46.1687166039128; Mon, 19 Jun 2023 02:13:59 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1687166039; cv=pass; d=google.com; s=arc-20160816; b=ge1sY+a35QXXxG1d6r/jLVq2XOfKKXqYKmiB9+LZ38moVcmbjz1QFNBm8t4LLbEj+Y 7+D6FR78lnlMRX0zl7Xm62DHMF+fUMke4wkrpMGdRTPHklM0eW6FgdtmFcYmCNageykx p0cVldd/KB+9zqH2er2VRY95mqqhI64dmg5sHqHkFqEpuxQp+kgV21PWkwxmvjNIW2Ut yVCbKewAkQLrfedX+1fN9+94lMCDnoti4zJuBQFAKqK1gB00gMzsD7ZY11Oeuaos4Vbj mFyb2oTfBUgfVXkIRh/8HfAUv/yIZYpIzWTQrqJmay8sYjSDoKM/OMlrs8cuL0GW+pF+ z05g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=K0B3b/ucyjOAYWlQFGDQjlTeWZr8CxeOTg0uej/vw2o=; b=O/LbYypsTDQ7bnlyoNka7c6PVV1HkCPL0/6UFj55594ztT8zpL7Lfz6Ct4e6xKaP7/ HZ74m35jYcTNwZrUQmeh+oQYzCww4KnDDoWHjK5Bbzlr5X4b/DC+hXTYJfEzM4WO/lVJ /z07qZLY2MrCPe6MEdmO1CJ7aVHw0r2mnEbfIqZthP+N6vFzucj9jGdB6wxB0XgW7Uyl AxPowiyvX/LrxqPG0KAfChNWso+MFm4xHuwZAe23abBCAMpvk82GxNECAc9X764T6lnE qaP1EJ6gHqo4jLTJE7f+66qIqECdEQ7pFYWgn2E8IuXlQbeZiMp0b3CElC1b6Rzlmwcv yOfw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@solidrn.onmicrosoft.com header.s=selector1-solidrn-onmicrosoft-com header.b=hdtCxKOG; arc=pass (i=1 spf=pass spfdomain=solid-run.com dkim=pass dkdomain=solid-run.com dmarc=pass fromdomain=solid-run.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ioana Ciornei Subject: [PATCH v3 2/4] dt-bindings: net: dpaa2 mac: add phys property Date: Mon, 19 Jun 2023 12:00:24 +0300 Message-Id: <20230619090026.22713-3-josua@solid-run.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230619090026.22713-1-josua@solid-run.com> References: <20230619090026.22713-1-josua@solid-run.com> X-ClientProxiedBy: FR0P281CA0236.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:b2::8) To AS8PR04MB8963.eurprd04.prod.outlook.com (2603:10a6:20b:42e::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB8963:EE_|DBBPR04MB7946:EE_ X-MS-Office365-Filtering-Correlation-Id: e3228910-e0fd-4feb-244c-08db70a3e26a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lGHUpDpp9WIjFZi+MuWZYP0PI2yw8x4Eh1La1Fye03YzPfnRWqW8YynqQkpETPTglrBtBAxvN+d93YdfB+4+mM2CBVthOXrumBR3z9fGnVlV1sYA7pykW+Vel/q/o0X3rN3nl0JMm/SfEw3hi8yYowJ5RbDEFan8b7pQvjjy+mvFpKiURRYUoDVC7lYafadB38k+4S73WKa83Yl9hBFXYQTolarAvoxW2kqe7fzyKsgO5xOTXcK3kebIfcjWtZHGmTanlqAtwb//64pY8UCm3T/OtuogjuZFXc90pAhyUY+QcXhkXE5Vlw7l3Psv1I4HXjUq75oXIAL6SGe7NV2NgOuBEo1QSim3AHLl6p1eIR9tJmG9x/ZZTSpjiyNj39vvA9L+KhHIYb6yias4MOCboo3qoyKcrBohO9bt2Ubwf3FPebi295/oiQS2nIGQs6K/1a0Tt+TUMiOTo2Qafe3nbFn/6PUkgfluxY+ggKL+45Vc/7LbZauJ+8Ocffg4/x5F3MFZkzqy568v3STeJQ5JMwET+ivtvr+l12NkbqRxvKLK30tMVTL/t6EEM102bmOR1wxQnFvKsV1+70YoMX38iH1QcH5k09Pi2RTed/eF8GsVj+Ye+bhoIC+WxbJhIDsW X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AS8PR04MB8963.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(366004)(39840400004)(136003)(396003)(346002)(376002)(451199021)(478600001)(6486002)(1076003)(6506007)(52116002)(6666004)(7416002)(5660300002)(86362001)(2906002)(36756003)(4326008)(54906003)(8936002)(8676002)(41300700001)(66556008)(66476007)(66946007)(316002)(2616005)(38350700002)(38100700002)(186003)(6512007)(26005);DIR:OUT;SFP:1101; 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It is currently used with the SerDes28G driver to switch SerDes protocol between SGMII and USXGMII at runtime. Support was introduced with: f978fe8 "dpaa2-mac: configure the SerDes phy on a protocol change" Add bindings description for the missing "phys" property, to fix dtc_chk errors present in various layerscape based dts: 'phys' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Josua Mayer Reviewed-by: Krzysztof Kozlowski --- V1 -> V2: this patch is newly added to patch-set Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml b/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml index a1b71b35319e..a40c7a84af2a 100644 --- a/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml +++ b/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml @@ -24,6 +24,10 @@ properties: maxItems: 1 description: The DPMAC number + phys: + maxItems: 1 + description: Generic PHY for SerDes runtime configuration. + phy-handle: true phy-connection-type: true From patchwork Mon Jun 19 09:00:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 109850 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2872539vqr; Mon, 19 Jun 2023 02:31:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6IsQKbjhXmLvkFc5h2++6RV4IDDY/tuzP9WhaGiyFm7sdUyHexZhcBOWl7CsGpSTOty3SA X-Received: by 2002:a92:c048:0:b0:33c:5109:bb07 with SMTP id o8-20020a92c048000000b0033c5109bb07mr7798002ilf.1.1687167081590; Mon, 19 Jun 2023 02:31:21 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1687167081; cv=pass; d=google.com; s=arc-20160816; b=o2e80Y/wUtfzSVIlM3+4qPbeLcxaHKxZF6KiLFWrD6H0lEu0HSXKoh4nCBlb4yviS2 3OtXG+gMHfzyI6zuHqR6zICgKGmSghRRV65pCmO/Qzz9auCAME4IpCdGpWbdz7vJLgDN x0nRYtJsyUNCvQdwgCMiSoHAbxsGEIaWYzMn7zDRyw25YsW7He0mPdJfxssqsVzZYNv9 SyK50bwlvOapXXGpC3fMZ+83SfBV7ioQ/W2gBTUD21psNIGfVRZ/Cv3wAC8ZjHyMCSNI qLbc8O/stT+sWS7Y1PIKSSXrp4fjhGaxGF1nGSCmKuUldmynt7ZnDkxGX4KJ+jFUP9R8 TSZw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8H2jGjKz+35/PSAl2sJFb27Pb9Jwju/vIYFpMDrBGuY=; b=oVvyszujLx8JSFgEBu6qHZjzgav/6l5CT1hKcYCc1nJdXlY/dRyQ1x7foSZkYMAflh H5UNuhKGkIWLBSPjWY235nzEFqH5XpRgjXM6cwXhaKZBjLhLuvAiYbcFnButpWj0pRcw 6NL1pcPxp0dt8B+54LR5Vf9lbdGTXzggTELcTHPOh4epyrXKZetWAVd44dABFItN2FFM oSIyviYVE586iKObeP3KBPGcfAYWUYk8S7Wxb+0QaRrrNFELczwa6g+izf4mAElwkSAD /6BqmSizKIZW6j+hvrVtyhicSgrttmuUJCyfGUThdwv54i32uvaVFDrd8CexXG6pbmBz qZSg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@solidrn.onmicrosoft.com header.s=selector1-solidrn-onmicrosoft-com header.b=Ib40bpLp; arc=pass (i=1 spf=pass spfdomain=solid-run.com dkim=pass dkdomain=solid-run.com dmarc=pass fromdomain=solid-run.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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LX2162 SoM is also a smaller form factor and reduced feature set to CEX. Since both product lines are physically incompatible, the existing group "SolidRun LX2160A based Boards" has been renamed to include "CEX" in its name, meaning products based on LX2160A COM Express Module, following this pattern: "solidrun,", "solidrun,lx2160a-cex", "fsl,lx2160a" Add DT compatible for both SolidRun LX2162A SoM, and LX2162 Clearfog boards to a new group based on LX2162A SoM, following this pattern: "solidrun,", "solidrun,lx2162a-som", "fsl,lx2160a" Signed-off-by: Josua Mayer Reviewed-by: Krzysztof Kozlowski --- V1 -> V2: fixed to not break existing boards V1 -> V2: explained new board / som DT binding in commit message Documentation/devicetree/bindings/arm/fsl.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 15d411084065..51911a89ebb4 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1370,7 +1370,7 @@ properties: - fsl,lx2162a-qds - const: fsl,lx2160a - - description: SolidRun LX2160A based Boards + - description: SolidRun LX2160A CEX-7 based Boards items: - enum: - solidrun,clearfog-cx @@ -1378,6 +1378,13 @@ properties: - const: solidrun,lx2160a-cex7 - const: fsl,lx2160a + - description: SolidRun LX2162A SoM based Boards + items: + - enum: + - solidrun,lx2162a-clearfog + - const: solidrun,lx2162a-som + - const: fsl,lx2160a + - description: S32G2 based Boards items: - enum: From patchwork Mon Jun 19 09:00:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 109849 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2871943vqr; Mon, 19 Jun 2023 02:29:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6DC01ZbKmC/TYBpQN2wjB3nQ1JO9j2SujHqUZ5ESSJdtcUupbHi2Z49l0eJbWDQn7TgtjM X-Received: by 2002:a05:6a20:144e:b0:121:cff2:a445 with SMTP id a14-20020a056a20144e00b00121cff2a445mr1625858pzi.18.1687166990672; Mon, 19 Jun 2023 02:29:50 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1687166990; cv=pass; d=google.com; s=arc-20160816; b=eWFPM+LPcr8jvWtu4qEMzkAO2vXZDjffoz4PFvDLBa5RVM8HxaEn0cO9HEzzvChJWj pAvoo7sD4uZeee7NBmb5zwP9Nw2WHOgu1oRIk3CBDRpvTcjxmclHcToi1Zk14Jrc821F +mz4biUeVfJ88c5Jveyq36u9grmfRZ9yREn8/vg3qW0UhGIvHMZCRJJLUESD5bCG7sAX 9LBey14ErFCxYKFm4yteurwuMDpJD6WYuVynZ59/qu4nPM5D7QeoGVJpssuEqmrzLxjT L+a5i7gT7LXmaTQ/MPp5Z4WizATa9P9/sk87kIerHSgKV9hTc+vgTBFSB4Yz0mJJqiI5 qJGA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xN5vmTSHzIVh/4jQdKDEKhXvvXz8l/fey99lgcDJBqM=; b=WKnYe5Nl2Eb1uY9CUBmrBwawXJOjkAavXTag+5KtNv9G7ZeJVJalxRh/PGhO4oY68c OTmfSocIPP123iAgkBXvFqlroVPBWwcw5tRjwEVRp3hafoYnkOG1b+swoNM86spQPAhi NzdjbAzcre7Twz86v3wfm0UexChWt2iKVHhXt2UtoOoHQ2jKMaeAM1Fw4Sj5KS+jZwdw E4neNJX0bzT0KCJyMJBD+7VYDEZqYNsa0xMs//bRHT0zdhPt++EzspkT0g1fqV1flORF LnN1M8vTkGQBuNOQ6hwRvVc5wOz0kwIxnHUDWF2IRWPzHM9YwXSbT79aQFU9Vy16xvik iiYg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@solidrn.onmicrosoft.com header.s=selector1-solidrn-onmicrosoft-com header.b=H8BPmp90; arc=pass (i=1 spf=pass spfdomain=solid-run.com dkim=pass dkdomain=solid-run.com dmarc=pass fromdomain=solid-run.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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The SoM has few software-controllable features: - AR8035 Ethernet PHY - eMMC - SPI Flash - fan controller - various eeproms The Clearfog evaluation board provides: - microSD connector - USB-A - 2x 10Gbps SFP+ - 2x 25Gbps SFP+ with a retimer - 8x 2.5Gbps RJ45 - 2x mPCI (assembly option / disables 2xRJ45) The 8x RJ45 ports are connected with an 8-port PHY: Marvell 88E2580 supporting up to 5Gbps, while SoC and magnetics are limited to 2.5Gbps. However 2500 speed is untested due to documentation and drivier limitations. To avoid confusion the phy nodes have been explicitly limited to 1000 for now. The PCI nodes are disabled, but explicitly added to mark that this board can have pci. It is expected that the bootloader will patch the status property "okay" and disable 2x RJ45 ports, according to active serdes configuration. Signed-off-by: Josua Mayer --- V1 -> V2: reordered "compatible" and "reg" properties V1 -> V2: replaced chip-specific DT node names with generic ones V1 -> V2: removed dead code from fspi node V2 -> V3: dropped deprecated address-cells, address-size props from flash node arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/fsl-lx2162a-clearfog.dts | 371 ++++++++++++++++++ .../dts/freescale/fsl-lx2162a-sr-som.dtsi | 73 ++++ 3 files changed, 445 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index ef7d17aef58f..b4fb5044d1c7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-clearfog.dtb fsl-ls1028a-qds-13bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-13bb.dtbo fsl-ls1028a-qds-65bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-65bb.dtbo diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts new file mode 100644 index 000000000000..57d8c93bfc57 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2162A Clearfog +// +// Copyright 2023 Josua Mayer + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" +#include "fsl-lx2162a-sr-som.dtsi" + +/ { + model = "SolidRun LX2162A Clearfog"; + compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a"; + + aliases { + crypto = &crypto; + i2c0 = &i2c0; + i2c1 = &i2c2; + i2c2 = &i2c4; + i2c3 = &sfp_i2c0; + i2c4 = &sfp_i2c1; + i2c5 = &sfp_i2c2; + i2c6 = &sfp_i2c3; + i2c7 = &mpcie1_i2c; + i2c8 = &mpcie0_i2c; + i2c9 = &pcieclk_i2c; + mmc0 = &esdhc0; + mmc1 = &esdhc1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led_sfp_at: led-sfp-at { + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */ + default-state = "off"; + }; + led_sfp_ab: led-sfp-ab { + gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */ + default-state = "off"; + }; + led_sfp_bt: led-sfp-bt { + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */ + default-state = "off"; + }; + led_sfp_bb: led-sfp-bb { + gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */ + default-state = "off"; + }; + }; + + sfp_at: sfp-at { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c0>; + mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */ + maximum-power-milliwatt = <2000>; + }; + + sfp_ab: sfp-ab { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c1>; + mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */ + maximum-power-milliwatt = <2000>; + }; + + sfp_bt: sfp-bt { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c2>; + mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */ + maximum-power-milliwatt = <2000>; + }; + + sfp_bb: sfp-bb { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c3>; + mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */ + maximum-power-milliwatt = <2000>; + }; +}; + +&i2c2 { + status = "okay"; + + /* retimer@18 */ + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + sfp_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + sfp_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + sfp_i2c2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + sfp_i2c3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + mpcie1_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + mpcie0_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + pcieclk_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + /* clock-controller@6b */ + }; + }; +}; + +&dpmac3 { + sfp = <&sfp_at>; + managed = "in-band-status"; + phys = <&serdes_1 7>; +}; + +&dpmac4 { + sfp = <&sfp_ab>; + managed = "in-band-status"; + phys = <&serdes_1 6>; +}; + +&dpmac5 { + sfp = <&sfp_bt>; + managed = "in-band-status"; + phys = <&serdes_1 5>; +}; + +&dpmac6 { + sfp = <&sfp_bb>; + managed = "in-band-status"; + phys = <&serdes_1 4>; +}; + +&dpmac11 { + status = "okay"; + phys = <&serdes_2 0>; + phy-handle = <ðernet_phy2>; + phy-connection-type = "sgmii"; +}; + +&dpmac12 { + status = "okay"; + phys = <&serdes_2 1>; + phy-handle = <ðernet_phy0>; + phy-connection-type = "sgmii"; +}; + +&dpmac13 { + status = "okay"; + phys = <&serdes_2 6>; + phy-handle = <ðernet_phy5>; + phy-connection-type = "sgmii"; +}; + +&dpmac14 { + status = "okay"; + phys = <&serdes_2 7>; + phy-handle = <ðernet_phy7>; + phy-connection-type = "sgmii"; +}; + +&dpmac15 { + status = "okay"; + phys = <&serdes_2 4>; + phy-handle = <ðernet_phy3>; + phy-connection-type = "sgmii"; +}; + +&dpmac16 { + status = "okay"; + phys = <&serdes_2 5>; + phy-handle = <ðernet_phy1>; + phy-connection-type = "sgmii"; +}; + +&dpmac17 { + /* override connection to on-SoM phy */ + /delete-property/ phy-handle; + /delete-property/ phy-connection-type; + + status = "okay"; + phys = <&serdes_2 2>; + phy-handle = <ðernet_phy4>; + phy-connection-type = "sgmii"; +}; + +&dpmac18 { + status = "okay"; + phys = <&serdes_2 3>; + phy-handle = <ðernet_phy6>; + phy-connection-type = "sgmii"; +}; + +&emdio1 { + /* + * SoM has a phy at address 1 connected to SoC Ethernet Controller 1. + * It competes for WRIOP MAC17, and no connector has been wired. + */ + /delete-node/ ethernet-phy@1; + + ethernet_phy0: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <8>; + max-speed = <1000>; + }; + + ethernet_phy1: ethernet-phy@9 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <9>; + max-speed = <1000>; + }; + + ethernet_phy2: ethernet-phy@10 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <10>; + max-speed = <1000>; + }; + + ethernet_phy3: ethernet-phy@11 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <11>; + max-speed = <1000>; + }; + + ethernet_phy4: ethernet-phy@12 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <12>; + max-speed = <1000>; + }; + + ethernet_phy5: ethernet-phy@13 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <13>; + max-speed = <1000>; + }; + + ethernet_phy6: ethernet-phy@14 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <14>; + max-speed = <1000>; + }; + + ethernet_phy7: ethernet-phy@15 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <15>; + max-speed = <1000>; + }; +}; + +&esdhc0 { + status = "okay"; + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; +}; + +&pcie3 { + status = "disabled"; +}; + +&pcie4 { + status = "disabled"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio4 { + status = "okay"; +}; + +&pcs_mdio5 { + status = "okay"; +}; + +&pcs_mdio6 { + status = "okay"; +}; + +&pcs_mdio11 { + status = "okay"; +}; + +&pcs_mdio12 { + status = "okay"; +}; + +&pcs_mdio13 { + status = "okay"; +}; + +&pcs_mdio14 { + status = "okay"; +}; + +&pcs_mdio15 { + status = "okay"; +}; + +&pcs_mdio16 { + status = "okay"; +}; + +&pcs_mdio17 { + status = "okay"; +}; + +&pcs_mdio18 { + status = "okay"; +}; + +&serdes_1 { + status = "okay"; +}; + +&serdes_2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi new file mode 100644 index 000000000000..ac3f9bc60265 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2162A-SOM +// +// Copyright 2021 Rabeeh Khoury +// Copyright 2023 Josua Mayer + +&crypto { + status = "okay"; +}; + +&dpmac17 { + phy-handle = <ðernet_phy0>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; + + ethernet_phy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +&esdhc1 { + status = "okay"; + bus-width = <8>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; +}; + +&fspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; + }; +}; + +&i2c0 { + status = "okay"; + + fan-controller@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + ddr_spd: eeprom@51 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x51>; + read-only; + }; + + config_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + }; +}; + +&i2c4 { + status = "okay"; + + variable_eeprom: eeprom@54 { + compatible = "st,24c2048", "atmel,24c2048"; + reg = <0x54>; + }; +};