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[2620:137:e000::1:20]) by mx.google.com with ESMTP id lf11-20020a170902fb4b00b001b51fa75f3bsi2514712plb.24.2023.06.16.05.35.30; Fri, 16 Jun 2023 05:35:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=yYp9RbPV; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345103AbjFPMDT (ORCPT + 99 others); Fri, 16 Jun 2023 08:03:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229518AbjFPMDM (ORCPT ); Fri, 16 Jun 2023 08:03:12 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58B2B295B; Fri, 16 Jun 2023 05:03:11 -0700 (PDT) Date: Fri, 16 Jun 2023 12:03:09 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1686916989; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2+hO6lUsJ+fKQi1OpOmoqjBrIThguK00NWLOatsOhNc=; b=yYp9RbPVAjNLWiXdjkP9vM+CjCnr81j3JRnBiMH6zR7qixawBxVItUM36Aa0nq7rY6rFy7 5xRxANEaSHGHZRP3mToZ6862+v48VH/CWzk/pv6pINs9LeJySqpuSy/U6gGhCcHPdK2w7L ttQ1G0AAO6g1Lkfsywuqqsn8gB6wGoW2/vJK1YKK3Q72qhVBsE8Doz4yxdU7tL3SfOOd2U L+DajcjYQdHJ1Nfe472BCrT98xiPzmv60R8Z03ThF18pwN/rKvtOtpYdQFCv0qinLBNv6o ZiXSdoEACZUpFepFkAn4wbtpK9wENoaoog5ScKB0QQO1NmZ7WD4Iu1FMZrqTKQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1686916989; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2+hO6lUsJ+fKQi1OpOmoqjBrIThguK00NWLOatsOhNc=; b=YNcoHxQDkwnBuccQl/QjlyWg0X+lXnSxzqX06YR2H1GINcp7azdw8O6R9KNGWEefHOZUal 0xAs5/zp1wmIYVDg== From: "irqchip-bot for Jianmin Lv" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/loongson-liointc: Fix IRQ trigger polarity Cc: stable@vger.kernel.org, Huacai Chen , Chong Qiao , Jianmin Lv , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20230614115936.5950-4-lvjianmin@loongson.cn> References: <20230614115936.5950-4-lvjianmin@loongson.cn> MIME-Version: 1.0 Message-ID: <168691698940.404.8300996918505647671.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768680173056229103?= X-GMAIL-MSGID: =?utf-8?q?1768862718767237271?= The following commit has been merged into the irq/irqchip-next branch of irqchip: Commit-ID: 1d7471b4e0ebba5a4bf9db4ade43619e8f2d333d Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/1d7471b4e0ebba5a4bf9db4ade43619e8f2d333d Author: Jianmin Lv AuthorDate: Wed, 14 Jun 2023 19:59:34 +08:00 Committer: Marc Zyngier CommitterDate: Fri, 16 Jun 2023 12:59:28 +01:00 irqchip/loongson-liointc: Fix IRQ trigger polarity For the INT_POLARITY register of Loongson-2K series IRQ controller, '0' indicates high level or rising edge triggered, '1' indicates low level or falling edge triggered, and we can find out the information from the Loongson 2K1000LA User Manual v1.0, Table 9-2, Section 9.3 (中断寄存器描述 / Description of the Interrupt Registers). For Loongson-3 CPU series, setting INT_POLARITY register is not supported and writting it has no effect. So trigger polarity setting shouled be fixed for Loongson-2K CPU series. Fixes: 17343d0b4039 ("irqchip/loongson-liointc: Support to set IRQ type for ACPI path") Cc: stable@vger.kernel.org Reviewed-by: Huacai Chen Co-developed-by: Chong Qiao Signed-off-by: Chong Qiao Signed-off-by: Jianmin Lv Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230614115936.5950-4-lvjianmin@loongson.cn --- drivers/irqchip/irq-loongson-liointc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c index 8d00a9a..5dd9db8 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -32,6 +32,10 @@ #define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04) #define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08) #define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c) +/* + * LIOINTC_REG_INTC_POL register is only valid for Loongson-2K series, and + * Loongson-3 series behave as noops. + */ #define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10) #define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14) @@ -116,19 +120,19 @@ static int liointc_set_type(struct irq_data *data, unsigned int type) switch (type) { case IRQ_TYPE_LEVEL_HIGH: liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); - liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); break; case IRQ_TYPE_LEVEL_LOW: liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); - liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); break; case IRQ_TYPE_EDGE_RISING: liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); - liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); break; case IRQ_TYPE_EDGE_FALLING: liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); - liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); break; default: irq_gc_unlock_irqrestore(gc, flags);