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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ft11-20020a17090b0f8b00b002562f925dcfsi1445484pjb.50.2023.06.16.04.48.47; Fri, 16 Jun 2023 04:49:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=jdGZp3m2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344205AbjFPLlm (ORCPT + 99 others); Fri, 16 Jun 2023 07:41:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242108AbjFPLlg (ORCPT ); Fri, 16 Jun 2023 07:41:36 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 296C7295B; Fri, 16 Jun 2023 04:41:29 -0700 (PDT) X-UUID: b8ed71480c3a11ee9cb5633481061a41-20230616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=0XfcLm2226ywh5z9orK1WYKPEry9DXdr8F7YQh+6JrA=; b=jdGZp3m2u7DvxBmO/GoZEBqQY8+7t+p3+VPA5+ErbqUcIZ+ViqIuK17RJR1L9OoI9PV2ucPZc/I7gRKcUtCjMTNuvYLH4jItoFjApKf31w7+9h9U4Yg62x8iSuB/87AxBFFHcp1ayCiUOecUrc3gryog+ZZwaU6jHamPGz3CM6w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.26,REQID:b55cf223-f75b-4ae9-9a7a-a0e0578fb61b,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:cb9a4e1,CLOUDID:35544d6f-2f20-4998-991c-3b78627e4938,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: b8ed71480c3a11ee9cb5633481061a41-20230616 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1018526311; Fri, 16 Jun 2023 19:41:24 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 16 Jun 2023 19:41:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 16 Jun 2023 19:41:23 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Rob Herring CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v3 01/13] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188 Date: Fri, 16 Jun 2023 19:40:59 +0800 Message-ID: <20230616114111.17554-2-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230616114111.17554-1-shawn.sung@mediatek.com> References: <20230616114111.17554-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS, T_SCC_BODY_TEXT_LINE,T_SPF_TEMPERROR,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768859780200872533?= X-GMAIL-MSGID: =?utf-8?q?1768859780200872533?= Add compatible name for MediaTek MT8188 ETHDR. Signed-off-by: Hsiao Chien Sung --- .../bindings/display/mediatek/mediatek,ethdr.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml index 801fa66ae615..677882348ede 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -23,7 +23,11 @@ description: properties: compatible: - const: mediatek,mt8195-disp-ethdr + oneOf: + - const: mediatek,mt8195-disp-ethdr + - items: + - const: mediatek,mt8188-disp-ethdr + - const: mediatek,mt8195-disp-ethdr reg: maxItems: 7 From patchwork Fri Jun 16 11:41:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 109062 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1277751vqr; Fri, 16 Jun 2023 04:45:43 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6HyA97G9QIvNQ8CMbWYIWg1IH5XUOPcT4iGWFwURLWG1D6/Z9Q2FUQD1kS3U++mCVlYi9N X-Received: by 2002:a05:6358:c686:b0:129:ca90:3b6c with SMTP id fe6-20020a056358c68600b00129ca903b6cmr1217408rwb.17.1686915943514; Fri, 16 Jun 2023 04:45:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686915943; cv=none; d=google.com; s=arc-20160816; b=DoOF8udZ4NwZJ3b4unbgk1rqP3g8DKwmFVLNVBkTNrogejhVlnyZn43IHOJwVw69nB ZrIuxn0xHaqFw0akB8LqGCoFK7uVzL/n8GJ8IikD0uu2SR78XCKWM+fqPz1B9It9jPbT /PDFPfqGJ7Vamct6wqqs3qPlbWJgAjkGfSfyJfc8Dq8gSLUCThp57VUs9yn28NwhugJl gltK+bPhKhNkfjG42SwXYMqlSbij/F1y4FoG6wirE5DfdVGyWW364p9Ahc4rCpLQ91yt rt8wd2E/UM2D8cJWJ+Au34i03koKHe3dbkNsgfvvkNGXzsROh99fetW8SmW4ZQmijWV4 BAAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Cfz9sH9lwt6+qccNYgMipqkrGxtN0q3GwRdSjw0DauA=; b=ypDLTHuTDVQ8dlBa3f4/Gn0rFsOj3hYxi50MWI70QO8VxP3VNLoYJ75a6lSvh2j/aO qqaJE3q07sbCSz07z05o6HJe0Hr+YZtC46svUeqHwyH3/dPYy/RzUNAynfar1BsHdOab ffiq8OpevG90ucOtXuviXZ6e5Nhb9VfdDuSxxaJJkBzKhVs+OoZPqdv+fRSvsZRC7k9l JpISPmN5uHJNnwDjsaAIFFGDpnyMQlqubgeHTWSgafPBkuml6KntUkHx5c4W8srQgw09 0R4LjTrnd/IjX98tmP0YJldEM/50uOlocjYJnyvzfHKGnM3qkCVsvbJHLO0kHwv8VXz/ GMYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=PFWJ8ngq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Hsiao Chien Sung --- .../bindings/display/mediatek/mediatek,mdp-rdma.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml index dd12e2ff685c..7570a0684967 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml @@ -21,7 +21,11 @@ description: properties: compatible: - const: mediatek,mt8195-vdo1-rdma + oneOf: + - const: mediatek,mt8195-vdo1-rdma + - items: + - const: mediatek,mt8188-vdo1-rdma + - const: mediatek,mt8195-vdo1-rdma reg: maxItems: 1 From patchwork Fri Jun 16 11:41:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 109063 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1277812vqr; Fri, 16 Jun 2023 04:45:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6TKR5PADIuG9dfIqaRoOJrqqzNPlopD3ciTBdeKpZKQ4gMACBDKv6Y3uX3XOoWm/vYueKp X-Received: by 2002:a17:902:f54e:b0:1b2:5c50:67ab with SMTP id h14-20020a170902f54e00b001b25c5067abmr1718031plf.22.1686915949176; Fri, 16 Jun 2023 04:45:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686915949; cv=none; d=google.com; s=arc-20160816; b=QPjK9swau/4+vXDsfDbfp5Zk4ZuJ8BeAq8J/TDNFfZx9emR27Cub2Qs++swuZt3wmR FSJazk2eAON90NBcJCgO0CgfRzVsGagErRRVFrac4JfyLYhDA0yOvjZto8VZjDUuFhkc hl2sVCo55P5kC5X7UTJy38us1hCf1R7w0xVff5y1uS4DZyF8BZAJ+gvmfu+mHwxMhB1N HEgUC2KJPdpnmjukAPazU67xsq5kpXsXcYiX3F0WT7fjUsZuMNiDIrLop/3xMd+aY6Kx 1VcTH5HGuu+umQAHqh1XEWZdXW9hngo6WQGhTUOOn6Q9xOXvW5Qa/Xd6w5phfy/7rbO9 lF0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=OVVWiQdAhDsoVl7MPahx1qZhjGtpKxL5lhbVi8FSpWw=; b=NSEuKLMquAh4vLodbF00XaA5OLYR5SYv94HlqhKT4pqrMMFXSkzela6Q33BuoRouD2 O8PXROMyWbDThbR0a/Hf0uMVaRfL5wKctDnUN6I0yqjJV03XQ8UmpAF4wiBAOxurVf49 GFneAZQlUhYMPgGbLVVneVD5emKl8wlzf83lzFoeSjiZNDn6PWjBUkdikqapsShD3Whb FlalxsNh5Kq65NXc2Z03n2KlhDpH/SmNT5qODhmYBewpq/ymAYnBOI3Uw2VBcr7VeUHQ JYFJhvt5fND8QZMRRySbZR6BlIUfUeI9mUGO9AidXdMoTi/xQiyTZ4l5c0bewXHFSYkb F+Hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=Fg790Xtj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Hsiao Chien Sung Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++ 1 file changed, 3 insertions(+) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index eead5cb8636e..5c678695162e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -27,6 +27,9 @@ properties: - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge + - items: + - const: mediatek,mt8188-disp-merge + - const: mediatek,mt8195-disp-merge reg: maxItems: 1 From patchwork Fri Jun 16 11:41:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 109078 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1285398vqr; Fri, 16 Jun 2023 05:00:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6JK4zWT+p81ejoNmomCa/c+NLEjwNCKki1bFytEKA1wdZqO9fBF0/8oe6j3A/ouhGwblM2 X-Received: by 2002:a17:902:d38d:b0:1b1:9f7d:2aec with SMTP id e13-20020a170902d38d00b001b19f7d2aecmr1462647pld.68.1686916839251; Fri, 16 Jun 2023 05:00:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686916839; cv=none; d=google.com; s=arc-20160816; b=q0ho2XghAN/OQfTgYHKz/TlGi575cVvagx+9Ma7EX/gAGvTOybdT4FMKJGogLNB4MW W4xo6U0mF+ohqcTLhXI6w2m0XDorMpkvbWt7v6GlK9+4gloIPdf5D3ftCmuJimdhYTeD /x24V9zWgUASnysiH2lCFc+6gZTQhpj1HjESVNxnYM2iM1MyIINAOPzXoBagk7CycMZY tIcFMI6FNM6Z6S9h5Ly9Au8hnGZnKsbh/g8qapmEpgHEkLRb2a7UIh9Ja5HCZ2dsHkUO IOqmJC+O8e7l6iPVj3JePKp+uBjFkKXxYCGOx8T2yM9Nix2pnFKppOE2MkZCEaNVLcy9 HcfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=/7oS+2IMRGCN+cy7LP4Me8LNKCO1aJoLyf7Y/imTN78=; b=dgFT6x1MtqRsYT7ePV3a6+ykh24tu9taoeHJPA+hOF41xxcIRYhok48TV79j6Lwo4w 9j04fl+ayLVemIQkmrInEPnxBxyl/W512WmIgTYCGQhc+yq3j9GD1dTyZI80tojLbdlQ 4y3CEHQiNDw0x9iWs1EZTk6P5DOUca81eRmX0DsGJpoAJPpadO6pQsPbFod/AyeZVSPE gBVRUuSsJCyuRLW2Rg+Nh4ajAlRzzkj534/+MxNxsn1FM7aif4xsHAlfFiYuf6N6HVzO XLO8hetLTZOZPHSIpP7WbKP7R4rXpXrgSJ/qC1kt3fe5AU42oXpltuMZujORzZfMZUku IW8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=g4A93tOs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u9-20020a170902e80900b001aaf639c4easi12913887plg.109.2023.06.16.05.00.25; Fri, 16 Jun 2023 05:00:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=g4A93tOs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344677AbjFPLly (ORCPT + 99 others); Fri, 16 Jun 2023 07:41:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344036AbjFPLli (ORCPT ); Fri, 16 Jun 2023 07:41:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B939D2D73; Fri, 16 Jun 2023 04:41:33 -0700 (PDT) X-UUID: b924b5a40c3a11eeb20a276fd37b9834-20230616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=/7oS+2IMRGCN+cy7LP4Me8LNKCO1aJoLyf7Y/imTN78=; b=g4A93tOsLVLkjBZP2BWYwK18m+gWXPwj4VvW22TP6lu1f/jXTtEsgnlu7+rOgKgeSLwdxhgIKMUjupVKQCIkywBeIox9VnujrafbyJFFR7AmfOW9zQ50mSX6cPAXPFjy4yb6di9zZxslR1wpmmfmadGB5Is7CD3zXPTIRMg1VW4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.26,REQID:64575a7d-d830-4f5d-876c-efd3eb0ba3d5,IP:0,U RL:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:20 X-CID-META: VersionHash:cb9a4e1,CLOUDID:67b9a83e-de1e-4348-bc35-c96f92f1dcbb,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: b924b5a40c3a11eeb20a276fd37b9834-20230616 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2128038488; Fri, 16 Jun 2023 19:41:24 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 16 Jun 2023 19:41:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 16 Jun 2023 19:41:23 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Rob Herring CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v3 04/13] dt-bindings: display: mediatek: padding: Add MT8188 Date: Fri, 16 Jun 2023 19:41:02 +0800 Message-ID: <20230616114111.17554-5-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230616114111.17554-1-shawn.sung@mediatek.com> References: <20230616114111.17554-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768860511571616531?= X-GMAIL-MSGID: =?utf-8?q?1768860511571616531?= Padding is a new hardware module on MediaTek MT8188, add dt-bindings for it. Signed-off-by: Hsiao Chien Sung --- .../display/mediatek/mediatek,padding.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml -- 2.18.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml new file mode 100644 index 000000000000..db24801ebc48 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Padding + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: + Padding provides ability to add pixels to width and height of a layer with + specified colors. Due to hardware design, Mixer in VDOSYS1 requires + width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled, + we need Padding to deal with odd width. + Please notice that even if the Padding is in bypass mode, settings in + register must be cleared to 0, or undefined behaviors could happen. + +properties: + compatible: + const: mediatek,mt8188-padding + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: RDMA Clock + + mediatek,gce-client-reg: + description: + GCE (Global Command Engine) is a multi-core micro processor that helps + its clients to execute commands without interrupting CPU. This property + describes GCE client's information that is composed by 4 fields. + 1. Phandle of the GCE (there may be several GCE processors) + 2. Sub-system ID defined in the dt-binding like a user ID + (Please refer to include/dt-bindings/gce/-gce.h) + 3. Offset from base address of the subsys you are at + 4. Size of the register the client needs + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: Phandle of the GCE + - description: Subsys ID defined in the dt-binding + - description: Offset from base address of the subsys + - description: Size of register + maxItems: 1 + +required: + - compatible + - reg + - power-domains + - clocks + - mediatek,gce-client-reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + padding0: padding@1c11d000 { + compatible = "mediatek,mt8188-padding"; + reg = <0 0x1c11d000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; + }; + }; From patchwork Fri Jun 16 11:41:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 109067 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1279785vqr; Fri, 16 Jun 2023 04:49:31 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5/hiI8wwIxcvHvdbG3kvIF68sBRHMjdZwl1D3h7C9DPWIOg+SUIAO1xv3N8ZfJALIf6IeG X-Received: by 2002:a17:903:2307:b0:1b3:e31e:abaa with SMTP id d7-20020a170903230700b001b3e31eabaamr1835740plh.0.1686916171509; Fri, 16 Jun 2023 04:49:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686916171; cv=none; d=google.com; s=arc-20160816; b=nU6om12F+ep0o8DhfEL76Rbl0qvsfNIbFVE6KDy9jGellsUYPaoWVeVv+Znq+8MiDI 2AVgE5zvlH6R3SAa2uKtgCtXubP6yoj8tSsbGHq0dirAhnYR7gX7fElF9agk/G8o+EfS qa9aLALqMBI5VekDylOMeatl/Bu1lsxYr+GnqZ3Bev30S0fGWjgq73H824extIrMA3e0 CoNNI4rdSJ7fHTC9JSWgDTjRYtqK+AB029MMomBdwhYEU/PBY/Whn2/pdbXXhtG/T9Wi +4oobQWkDOZvdeDYEIsYxMEr5HTH4E6W31AYj30Ry3X6LuBg14scyUDI022kCs/4G0iG Zltg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=63zz3OIWKmol1iGJYfPdhwr3BoyTS3LsSeYyIjQ+eck=; b=qfW0TDd2QUhHlWTyCx8HJkeQKIdmdYipCfXHlPFapaHcbW7mdWTrtTG/SL0NrICsHV RMfaaDxJq/14S94ToVDzdZHjziswYu9h2DqjBeLrSp7YSj846mUyEJ0s2RwM8siOKoYU MItQ83guKkgqMI/oOn0L2obg4tHZCft0QMR3X/7ir+wdYvTCLtvmAXJAERDQQGan3rV9 ARQhxopam2O2xXlF1eF0uQBh3Qs+6btH8Y7CsQMew+8ZsPVFNHh8gO7YhzGteGc5KUdI zN6FvqKdAXUsHlj8ulOWhyer7HevX8Lq2h+urLAbgJdtr5JT4jLhWtwUWAVmWhfr0hpk gZIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=eXBEMm9B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Hsiao Chien Sung --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 536f5a5ebd24..642fa2e4736e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8188-vdosys0 + - mediatek,mt8188-vdosys1 - mediatek,mt8192-mmsys - mediatek,mt8195-vdosys1 - mediatek,mt8195-vppsys0 From patchwork Fri Jun 16 11:41:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 109069 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1281262vqr; Fri, 16 Jun 2023 04:52:33 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ58zTVrajRc/HxJmmPhKoZThkDtd6vJTLnIyn0gadXic9meqFBczACWad1SuOvGTOWGk44D X-Received: by 2002:a05:6a20:8f02:b0:11d:8cd1:111d with SMTP id b2-20020a056a208f0200b0011d8cd1111dmr10353805pzk.6.1686916353168; Fri, 16 Jun 2023 04:52:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686916353; cv=none; d=google.com; s=arc-20160816; b=002i6aDKkc6wQtr/EZkTYbDqYJ8yoS1P/OD9LQGSX9BQR70qFgfKNEXfZN3DlR1VCb KDbuOk1kp55liOy5Jit9IF4sul6uzZgf7vulgZz3yeyGWmnHV3U6twwMUIyfWQKDAeqv +RYRbYllwn8m3tY3i97WV2DgkQAvLptFv38UCjAvuT0id8ZY2B7FvjteSVzGoHuR0Gxp TnvTcwc2vq4mf1FmQLCesiz7XQv8RYAxRd1DLr32Ku5MoU6VcAEypdWm8Al7/g9+VRJi AnvVtf3wAr1mkhVZdtfxM2wtV6AAZ/saKE8U7kpi1cmUTfqmfaFGN/bV7khBip6TwG87 /oow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=iXBCKHuNhtaEDsybbjjLMRWfevS24t/pBx4IJw8dO9I=; b=sPzKlb8ejuI3sLVLl8wohVCuLpgI6p0utOuHB76nWwyCbDfUBvtS54uVNIA/L8u79r g/vYgNYy4r1++oXzfY5+EQ5FafTg87GdOc6t+8VOQ53TAePmKi0An/Um/E4Pnm426GjQ uRJAlTzaByYy8j5dA6XK3Ysg1UHvabfE77+UkdQDJrO1bpCv/l3hqkeVK6pVjUv9zUX0 739BH5UnQt7ibevqcsJ+aQBW64n2HNNfguN/qy9aDXFCmxB1IYgV9tdy5poDGR9sJsCk zosbQNMAAQdHJW7a3C8LrCma9RgXOg5gH2WZyXaBwkQ1g8+bYsdJ2deBVM2x3yvcxgoF bEWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="UNG/POpA"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Hsiao Chien Sung --- include/dt-bindings/reset/mt8188-resets.h | 75 +++++++++++++++++++++++ 1 file changed, 75 insertions(+) -- 2.18.0 diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h index ba9a5e9b8899..5a58c54e7d20 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -38,4 +38,79 @@ #define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1 #define MT8188_INFRA_RST3_PTP_CTRL_RST 2 +#define MT8188_VDO0_RST_DISP_OVL0 0 +#define MT8188_VDO0_RST_FAKE_ENG0 1 +#define MT8188_VDO0_RST_DISP_CCORR0 2 +#define MT8188_VDO0_RST_DISP_MUTEX0 3 +#define MT8188_VDO0_RST_DISP_GAMMA0 4 +#define MT8188_VDO0_RST_DISP_DITHER0 5 +#define MT8188_VDO0_RST_DISP_WDMA0 6 +#define MT8188_VDO0_RST_DISP_RDMA0 7 +#define MT8188_VDO0_RST_DSI0 8 +#define MT8188_VDO0_RST_DSI1 9 +#define MT8188_VDO0_RST_DSC_WRAP0 10 +#define MT8188_VDO0_RST_VPP_MERGE0 11 +#define MT8188_VDO0_RST_DP_INTF0 12 +#define MT8188_VDO0_RST_DISP_AAL0 13 +#define MT8188_VDO0_RST_INLINEROT0 14 +#define MT8188_VDO0_RST_APB_BUS 15 +#define MT8188_VDO0_RST_DISP_COLOR0 16 +#define MT8188_VDO0_RST_MDP_WROT0 17 +#define MT8188_VDO0_RST_DISP_RSZ0 18 + +#define MT8188_VDO1_RST_SMI_LARB2 0 +#define MT8188_VDO1_RST_SMI_LARB3 1 +#define MT8188_VDO1_RST_GALS 2 +#define MT8188_VDO1_RST_FAKE_ENG0 3 +#define MT8188_VDO1_RST_FAKE_ENG1 4 +#define MT8188_VDO1_RST_MDP_RDMA0 5 +#define MT8188_VDO1_RST_MDP_RDMA1 6 +#define MT8188_VDO1_RST_MDP_RDMA2 7 +#define MT8188_VDO1_RST_MDP_RDMA3 8 +#define MT8188_VDO1_RST_VPP_MERGE0 9 +#define MT8188_VDO1_RST_VPP_MERGE1 10 +#define MT8188_VDO1_RST_VPP_MERGE2 11 +#define MT8188_VDO1_RST_VPP_MERGE3 12 +#define MT8188_VDO1_RST_VPP_MERGE4 13 +#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14 +#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15 +#define MT8188_VDO1_RST_DISP_MUTEX 16 +#define MT8188_VDO1_RST_MDP_RDMA4 17 +#define MT8188_VDO1_RST_MDP_RDMA5 18 +#define MT8188_VDO1_RST_MDP_RDMA6 19 +#define MT8188_VDO1_RST_MDP_RDMA7 20 +#define MT8188_VDO1_RST_DP_INTF1_MMCK 21 +#define MT8188_VDO1_RST_DPI0_MM_CK 22 +#define MT8188_VDO1_RST_DPI1_MM_CK 23 +#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24 +#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25 +#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26 +#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27 +#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28 +#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29 +#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30 +#define MT8188_VDO1_RST_PADDING0 31 +#define MT8188_VDO1_RST_PADDING1 32 +#define MT8188_VDO1_RST_PADDING2 33 +#define MT8188_VDO1_RST_PADDING3 34 +#define MT8188_VDO1_RST_PADDING4 35 +#define MT8188_VDO1_RST_PADDING5 36 +#define MT8188_VDO1_RST_PADDING6 37 +#define MT8188_VDO1_RST_PADDING7 38 +#define MT8188_VDO1_RST_DISP_RSZ0 39 +#define MT8188_VDO1_RST_DISP_RSZ1 40 +#define MT8188_VDO1_RST_DISP_RSZ2 41 +#define MT8188_VDO1_RST_DISP_RSZ3 42 +#define MT8188_VDO1_RST_HDR_VDO_FE0 43 +#define MT8188_VDO1_RST_HDR_GFX_FE0 44 +#define MT8188_VDO1_RST_HDR_VDO_BE 45 +#define MT8188_VDO1_RST_HDR_VDO_FE1 46 +#define MT8188_VDO1_RST_HDR_GFX_FE1 47 +#define MT8188_VDO1_RST_DISP_MIXER 48 +#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49 +#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50 +#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51 +#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52 +#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ From patchwork Fri Jun 16 11:41:05 2023 Content-Type: text/plain; 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Fri, 16 Jun 2023 19:41:24 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 16 Jun 2023 19:41:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 16 Jun 2023 19:41:24 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Rob Herring CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v3 07/13] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys Date: Fri, 16 Jun 2023 19:41:05 +0800 Message-ID: <20230616114111.17554-8-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230616114111.17554-1-shawn.sung@mediatek.com> References: <20230616114111.17554-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768860452963661539?= X-GMAIL-MSGID: =?utf-8?q?1768860452963661539?= - Add register definitions for MT8188 - Add VDOSYS1 routing table - Update MUTEX definitions accordingly - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mt8188-mmsys.h | 127 ++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 13 +++ drivers/soc/mediatek/mtk-mmsys.h | 29 +++++++ drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++ 4 files changed, 204 insertions(+) -- 2.18.0 diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h index 448cc3761b43..447afb72d95f 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -67,6 +67,57 @@ #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) +#define MT8188_VDO1_SW0_RST_B 0x1d0 +#define MT8188_VDO1_HDR_TOP_CFG 0xd00 +#define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 +#define MT8188_VDO1_MIXER_IN1_PAD 0xd40 +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 +#define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10 +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 +#define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18 +#define MT8188_MERGE4_SOUT_TO_DPI1_SEL BIT(2) +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL BIT(3) +#define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24 +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28 +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30 +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34 +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 +#define MT8188_SOUT_TO_MIXER_IN1_SEL 1 +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 +#define MT8188_SOUT_TO_MIXER_IN2_SEL 1 +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 +#define MT8188_SOUT_TO_MIXER_IN3_SEL 1 +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c +#define MT8188_SOUT_TO_MIXER_IN4_SEL 1 +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58 +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60 +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64 +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, @@ -146,4 +197,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { }, }; +static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = { + { + DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, + MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 + }, { + DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, + MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 + }, { + DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, + MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN1_SEL + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN2_SEL + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN3_SEL + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN4_SEL + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), + MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), + MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), + MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8188_MERGE4_SOUT_TO_DPI1_SEL + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), + MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL + } +}; + #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 9619faa796e8..3a81ef2bcc3c 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), }; +static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { + .clk_driver = "clk-mt8188-vdo1", + .routes = mmsys_mt8188_vdo1_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), + .sw0_rst_offset = MT8188_VDO1_SW0_RST_B, + .num_resets = 96, + .vsync_len = 1, +}; + static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table, @@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha_sel << (19 + idx), cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt); + if (mmsys->data->vsync_len) + mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0, + mmsys->data->vsync_len, cmdq_pkt); } EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config); @@ -431,6 +443,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data }, { .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data }, { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data }, + { .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data }, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data }, /* "mediatek,mt8195-mmsys" compatible is deprecated */ { .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data }, diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 6725403d2e3a..964b5449d672 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -86,6 +86,34 @@ struct mtk_mmsys_routes { u32 val; }; +/** + * struct mtk_mmsys_driver_data - settings for the mmsys + * @clk_driver: Clock driver name that the mmsys is using + * (defined in drivers/clk/mediatek/clk-*.c). + * @routes: Routing table of the mmsys. + * It provides mux settings from one module to another. + * @num_routes: Array size of the routes. + * @sw0_rst_offset: Register offset for the reset control. + * @num_resets: Number of reset bits that are defined + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe) + * or VDOSYS (Video). Only VDOSYS needs to be added to drm driver. + * @vsync_len: VSYNC length of the MIXER. + * VSYNC is usually triggered by the connector, so its length is + * a fixed value as long as the frame rate is decided, but ETHDR and + * MIXER generate their own VSYNC due to hardware design, therefore + * MIXER has to sync with ETHDR by adjusting VSYNC length. + * On MT8195, there is no such setting so we use the gap between + * falling edge and rising edge of SOF (Start of Frame) signal to + * do the job, but since MT8188, VSYNC_LEN setting is introduced to + * solve the problem and is given 0x40 (ticks) as the default value. + * Please notice that this value has to be set to 1 (minimum) if + * ETHDR is bypassed, otherwise MIXER could wait too long and causing + * underflow. + * + * Each MMSYS (multi-media system) may have different settings, they may use + * different clock sources, mux settings, reset control ...etc., and these + * differences are all stored here. + */ struct mtk_mmsys_driver_data { const char *clk_driver; const struct mtk_mmsys_routes *routes; @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data { const u16 sw0_rst_offset; const u32 num_resets; const bool is_vppsys; + const u8 vsync_len; }; /* diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 4aa0913817ae..028d2e7026bd 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -134,6 +134,22 @@ #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 #define MT8188_MUTEX_MOD2_DISP_PWM0 33 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24 +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30 +#define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 + #define MT8195_MUTEX_MOD_DISP_OVL0 0 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 @@ -265,6 +281,7 @@ #define MT8183_MUTEX_SOF_DPI0 2 #define MT8188_MUTEX_SOF_DSI0 1 #define MT8188_MUTEX_SOF_DP_INTF0 3 +#define MT8188_MUTEX_SOF_DP_INTF1 4 #define MT8195_MUTEX_SOF_DSI0 1 #define MT8195_MUTEX_SOF_DSI1 2 #define MT8195_MUTEX_SOF_DP_INTF0 3 @@ -276,6 +293,7 @@ #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) +#define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7) #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) @@ -446,6 +464,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0, + [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1, + [DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2, + [DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3, + [DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4, + [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, + [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, + [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, + [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, + [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, + [DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3, + [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4, + [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1, }; static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { @@ -606,6 +639,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = { MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, [MUTEX_SOF_DP_INTF0] = MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, + [MUTEX_SOF_DP_INTF1] = + MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1, }; static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { From patchwork Fri Jun 16 11:41:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 109073 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1284544vqr; Fri, 16 Jun 2023 04:59:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7mzH7RTJdDw9YdJvbcOCojxLhWscRNK2HagvoYuTdT44I1wxa+AcwezbFp8HUo5T8tCoiS X-Received: by 2002:a17:902:d2c6:b0:1b0:295b:f192 with SMTP id n6-20020a170902d2c600b001b0295bf192mr2085070plc.3.1686916760985; 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Fri, 16 Jun 2023 19:41:25 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 16 Jun 2023 19:41:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 16 Jun 2023 19:41:24 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Rob Herring CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v3 08/13] soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsys Date: Fri, 16 Jun 2023 19:41:06 +0800 Message-ID: <20230616114111.17554-9-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230616114111.17554-1-shawn.sung@mediatek.com> References: <20230616114111.17554-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,UPPERCASE_50_75,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768860429309497728?= X-GMAIL-MSGID: =?utf-8?q?1768860429309497728?= - Add Padding components - Add Mutex module definitions for Padding Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mutex.c | 16 ++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 8 ++++++++ 2 files changed, 24 insertions(+) -- 2.18.0 diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 028d2e7026bd..a91cb87f5eaa 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -142,6 +142,14 @@ #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_PADDING0 8 +#define MT8188_MUTEX_MOD_DISP1_PADDING1 9 +#define MT8188_MUTEX_MOD_DISP1_PADDING2 10 +#define MT8188_MUTEX_MOD_DISP1_PADDING3 11 +#define MT8188_MUTEX_MOD_DISP1_PADDING4 12 +#define MT8188_MUTEX_MOD_DISP1_PADDING5 13 +#define MT8188_MUTEX_MOD_DISP1_PADDING6 14 +#define MT8188_MUTEX_MOD_DISP1_PADDING7 15 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 @@ -472,6 +480,14 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0, + [DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1, + [DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2, + [DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3, + [DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4, + [DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5, + [DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6, + [DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7, [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2475ef914746..ae9088a34339 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -49,6 +49,14 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_MDP_RDMA5, DDP_COMPONENT_MDP_RDMA6, DDP_COMPONENT_MDP_RDMA7, + DDP_COMPONENT_PADDING0, + DDP_COMPONENT_PADDING1, + DDP_COMPONENT_PADDING2, + DDP_COMPONENT_PADDING3, + DDP_COMPONENT_PADDING4, + DDP_COMPONENT_PADDING5, + DDP_COMPONENT_PADDING6, + DDP_COMPONENT_PADDING7, DDP_COMPONENT_MERGE0, DDP_COMPONENT_MERGE1, DDP_COMPONENT_MERGE2, From patchwork Fri Jun 16 11:41:07 2023 Content-Type: text/plain; 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Fri, 16 Jun 2023 19:41:25 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 16 Jun 2023 19:41:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 16 Jun 2023 19:41:24 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Rob Herring CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v3 09/13] soc: mediatek: Support reset bit mapping in mmsys driver Date: Fri, 16 Jun 2023 19:41:07 +0800 Message-ID: <20230616114111.17554-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230616114111.17554-1-shawn.sung@mediatek.com> References: <20230616114111.17554-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768862841606705101?= X-GMAIL-MSGID: =?utf-8?q?1768862841606705101?= - Reset ID must starts from 0 and be consecutive, but the reset bits in our hardware design is not continuous, some bits are left unused, we need a map to solve the problem - Use old style 1-to-1 mapping if .rst_tb is not defined Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++ drivers/soc/mediatek/mtk-mmsys.h | 3 +++ 2 files changed, 12 insertions(+) -- 2.18.0 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 3a81ef2bcc3c..13249658721f 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -314,6 +314,15 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l u32 offset; u32 reg; + if (mmsys->data->rst_tb) { + if (id >= mmsys->data->num_resets) { + dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n", + id, mmsys->data->num_resets); + return -EINVAL; + } + id = mmsys->data->rst_tb[id]; + } + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); id = id % MMSYS_SW_RESET_PER_REG; reg = mmsys->data->sw0_rst_offset + offset; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 964b5449d672..c4c19fcd4b62 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -78,6 +78,8 @@ #define DSI_SEL_IN_RDMA 0x1 #define DSI_SEL_IN_MASK 0x1 +#define MMSYS_RST_NR(bank, bit) ((bank * 32) + bit) + struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; @@ -119,6 +121,7 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; + const u8 *rst_tb; const u32 num_resets; const bool is_vppsys; const u8 vsync_len; From patchwork Fri Jun 16 11:41:08 2023 Content-Type: text/plain; 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Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mt8188-mmsys.h | 84 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 6 ++- 2 files changed, 89 insertions(+), 1 deletion(-) -- 2.18.0 diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h index 447afb72d95f..297ec2753850 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -3,6 +3,11 @@ #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H #define __SOC_MEDIATEK_MT8188_MMSYS_H +#include +#include + +#define MT8188_VDO0_SW0_RST_B 0x190 + #define MT8188_VDO0_OVL_MOUT_EN 0xf14 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) @@ -118,6 +123,85 @@ #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 #define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c +static const u8 mmsys_mt8188_vdo0_rst_tb[] = { + [MT8188_VDO0_RST_DISP_OVL0] = MMSYS_RST_NR(0, 0), + [MT8188_VDO0_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 2), + [MT8188_VDO0_RST_DISP_CCORR0] = MMSYS_RST_NR(0, 4), + [MT8188_VDO0_RST_DISP_MUTEX0] = MMSYS_RST_NR(0, 6), + [MT8188_VDO0_RST_DISP_GAMMA0] = MMSYS_RST_NR(0, 8), + [MT8188_VDO0_RST_DISP_DITHER0] = MMSYS_RST_NR(0, 10), + [MT8188_VDO0_RST_DISP_WDMA0] = MMSYS_RST_NR(0, 17), + [MT8188_VDO0_RST_DISP_RDMA0] = MMSYS_RST_NR(0, 19), + [MT8188_VDO0_RST_DSI0] = MMSYS_RST_NR(0, 21), + [MT8188_VDO0_RST_DSI1] = MMSYS_RST_NR(0, 22), + [MT8188_VDO0_RST_DSC_WRAP0] = MMSYS_RST_NR(0, 23), + [MT8188_VDO0_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 24), + [MT8188_VDO0_RST_DP_INTF0] = MMSYS_RST_NR(0, 25), + [MT8188_VDO0_RST_DISP_AAL0] = MMSYS_RST_NR(0, 26), + [MT8188_VDO0_RST_INLINEROT0] = MMSYS_RST_NR(0, 27), + [MT8188_VDO0_RST_APB_BUS] = MMSYS_RST_NR(0, 28), + [MT8188_VDO0_RST_DISP_COLOR0] = MMSYS_RST_NR(0, 29), + [MT8188_VDO0_RST_MDP_WROT0] = MMSYS_RST_NR(0, 30), + [MT8188_VDO0_RST_DISP_RSZ0] = MMSYS_RST_NR(0, 31), +}; + +static const u8 mmsys_mt8188_vdo1_rst_tb[] = { + [MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0), + [MT8188_VDO1_RST_SMI_LARB3] = MMSYS_RST_NR(0, 1), + [MT8188_VDO1_RST_GALS] = MMSYS_RST_NR(0, 2), + [MT8188_VDO1_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 3), + [MT8188_VDO1_RST_FAKE_ENG1] = MMSYS_RST_NR(0, 4), + [MT8188_VDO1_RST_MDP_RDMA0] = MMSYS_RST_NR(0, 5), + [MT8188_VDO1_RST_MDP_RDMA1] = MMSYS_RST_NR(0, 6), + [MT8188_VDO1_RST_MDP_RDMA2] = MMSYS_RST_NR(0, 7), + [MT8188_VDO1_RST_MDP_RDMA3] = MMSYS_RST_NR(0, 8), + [MT8188_VDO1_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 9), + [MT8188_VDO1_RST_VPP_MERGE1] = MMSYS_RST_NR(0, 10), + [MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11), + [MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0), + [MT8188_VDO1_RST_VPP_MERGE4] = MMSYS_RST_NR(1, 1), + [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 2), + [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 3), + [MT8188_VDO1_RST_DISP_MUTEX] = MMSYS_RST_NR(1, 4), + [MT8188_VDO1_RST_MDP_RDMA4] = MMSYS_RST_NR(1, 5), + [MT8188_VDO1_RST_MDP_RDMA5] = MMSYS_RST_NR(1, 6), + [MT8188_VDO1_RST_MDP_RDMA6] = MMSYS_RST_NR(1, 7), + [MT8188_VDO1_RST_MDP_RDMA7] = MMSYS_RST_NR(1, 8), + [MT8188_VDO1_RST_DP_INTF1_MMCK] = MMSYS_RST_NR(1, 9), + [MT8188_VDO1_RST_DPI0_MM_CK] = MMSYS_RST_NR(1, 10), + [MT8188_VDO1_RST_DPI1_MM_CK] = MMSYS_RST_NR(1, 11), + [MT8188_VDO1_RST_MERGE0_DL_ASYNC] = MMSYS_RST_NR(1, 13), + [MT8188_VDO1_RST_MERGE1_DL_ASYNC] = MMSYS_RST_NR(1, 14), + [MT8188_VDO1_RST_MERGE2_DL_ASYNC] = MMSYS_RST_NR(1, 15), + [MT8188_VDO1_RST_MERGE3_DL_ASYNC] = MMSYS_RST_NR(1, 16), + [MT8188_VDO1_RST_MERGE4_DL_ASYNC] = MMSYS_RST_NR(1, 17), + [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 18), + [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 19), + [MT8188_VDO1_RST_PADDING0] = MMSYS_RST_NR(1, 20), + [MT8188_VDO1_RST_PADDING1] = MMSYS_RST_NR(1, 21), + [MT8188_VDO1_RST_PADDING2] = MMSYS_RST_NR(1, 22), + [MT8188_VDO1_RST_PADDING3] = MMSYS_RST_NR(1, 23), + [MT8188_VDO1_RST_PADDING4] = MMSYS_RST_NR(1, 24), + [MT8188_VDO1_RST_PADDING5] = MMSYS_RST_NR(1, 25), + [MT8188_VDO1_RST_PADDING6] = MMSYS_RST_NR(1, 26), + [MT8188_VDO1_RST_PADDING7] = MMSYS_RST_NR(1, 27), + [MT8188_VDO1_RST_DISP_RSZ0] = MMSYS_RST_NR(1, 28), + [MT8188_VDO1_RST_DISP_RSZ1] = MMSYS_RST_NR(1, 29), + [MT8188_VDO1_RST_DISP_RSZ2] = MMSYS_RST_NR(1, 30), + [MT8188_VDO1_RST_DISP_RSZ3] = MMSYS_RST_NR(1, 31), + [MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0), + [MT8188_VDO1_RST_HDR_GFX_FE0] = MMSYS_RST_NR(2, 1), + [MT8188_VDO1_RST_HDR_VDO_BE] = MMSYS_RST_NR(2, 2), + [MT8188_VDO1_RST_HDR_VDO_FE1] = MMSYS_RST_NR(2, 16), + [MT8188_VDO1_RST_HDR_GFX_FE1] = MMSYS_RST_NR(2, 17), + [MT8188_VDO1_RST_DISP_MIXER] = MMSYS_RST_NR(2, 18), + [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 19), + [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 20), + [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 21), + [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 22), + [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23), +}; + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 13249658721f..7a6221f87669 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -87,6 +87,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .clk_driver = "clk-mt8188-vdo0", .routes = mmsys_mt8188_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), + .sw0_rst_offset = MT8188_VDO0_SW0_RST_B, + .rst_tb = mmsys_mt8188_vdo0_rst_tb, + .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb), }; static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { @@ -94,7 +97,8 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { .routes = mmsys_mt8188_vdo1_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), .sw0_rst_offset = MT8188_VDO1_SW0_RST_B, - .num_resets = 96, + .rst_tb = mmsys_mt8188_vdo1_rst_tb, + .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb), .vsync_len = 1, }; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j63-20020a636e42000000b00543c1b255d3si15072946pgc.174.2023.06.16.04.50.16; Fri, 16 Jun 2023 04:50:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="ip1Z/9Xt"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344570AbjFPLmE (ORCPT + 99 others); Fri, 16 Jun 2023 07:42:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344038AbjFPLli (ORCPT ); Fri, 16 Jun 2023 07:41:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBCA42D79; Fri, 16 Jun 2023 04:41:34 -0700 (PDT) X-UUID: b9b9c6800c3a11eeb20a276fd37b9834-20230616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=i9jj0vUqT26774bVi3zs8Yawe1psaWVvLBuHIIfHyzU=; b=ip1Z/9Xtf5cJwEdeqnR7r4JzlEBlIdoM5+xGbgbLfIuN8oppFSxNMsnpnOr87rgWl/lIfGo+Z153iJXS37qh3ciJqbHDbrbrMeNd8SZDqd0QjUKf0wjtrXTkeBDz/F5+aYIFTgCFRVaTMC/7qECSXlBXEIuf0JaaWi3qRTXK56w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.26,REQID:2728c994-5243-4e88-b704-d7c414812496,IP:0,U RL:0,TC:0,Content:-5,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-35 X-CID-META: VersionHash:cb9a4e1,CLOUDID:84544d6f-2f20-4998-991c-3b78627e4938,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: b9b9c6800c3a11eeb20a276fd37b9834-20230616 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1003879635; Fri, 16 Jun 2023 19:41:25 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 16 Jun 2023 19:41:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 16 Jun 2023 19:41:24 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Rob Herring CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v3 11/13] drm/mediatek: Support MT8188 VDOSYS1 in display driver Date: Fri, 16 Jun 2023 19:41:09 +0800 Message-ID: <20230616114111.17554-12-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230616114111.17554-1-shawn.sung@mediatek.com> References: <20230616114111.17554-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768859873351890775?= X-GMAIL-MSGID: =?utf-8?q?1768859873351890775?= - The mmsys_dev_num in MT8188 VDOSYS0 was set to 1 since VDOSYS1 was not available before. Increase it to support VDOSYS1 in display driver. - Add compatible name for MT8188 VDOSYS1 (shares the same driver data with MT8195 VDOSYS1) Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.18.0 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6dcb4ba2466c..613093068bb4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -287,6 +287,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .main_path = mt8188_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), + .mmsys_dev_num = 2, }; static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { @@ -327,6 +328,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8186_mmsys_driver_data}, { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data}, + { .compatible = "mediatek,mt8188-vdosys1", + .data = &mt8195_vdosys1_driver_data}, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data}, { .compatible = "mediatek,mt8195-mmsys", From patchwork Fri Jun 16 11:41:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 109080 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1288848vqr; Fri, 16 Jun 2023 05:04:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5bF7fRJNMO3sJvCNKhMmF8OMoUji/FSUG/kiev3TRWUHZbqdVT6Wb2YSeL/VsEoQPZ0qUV X-Received: by 2002:a92:dc81:0:b0:341:d30d:173e with SMTP id c1-20020a92dc81000000b00341d30d173emr2163997iln.15.1686917078607; Fri, 16 Jun 2023 05:04:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686917078; cv=none; d=google.com; s=arc-20160816; b=MqPdshBC22YC0V8OGCYuhBDpZ4Eo1jK/x/OchBxrN8TVyTWXLcLyLscNLQy1nkwKfV 0K+FNGOhOW7gajj+baUuMqrgnl1u5Pv+SmqDj3RF3PkPa3nzxuXKXULqZbThnrYjzVbZ ejYR1Y2Q9vGEEywBQfl7KuKSo13RRzrMuyLF42X9W7rzCG5umAG7V4gzn1CSTZCz1ShK 7S3d9FJQU5IunOlp2WNOBzYNtOknDn6l0dGj+ch0ML7ru3P4haQ96UO23j0P0obpngId NNNQY6KII+XRMSxUZd/5b2+wD5UIK3jKbMuECziKfPcpqM/bvX1pEQ0pLcqdOJgap2La EhUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=uJrhqEVUl+JgSBLetX8UvH1e137N/lC8nLdCIORzaaA=; b=oOEXpZNGOYFVNEFIb99NVfrVst+E6nqIZtEM0XfPmeq40V5VmiG8tSj4FVrpE6GIDK DT1OhcLBwHIEwuOjgaANvtUwltSNqlKX33go8Rut8PFA15y2SpHvn+Yiqh9BnpDCUazM zI7w+VFQCiPtlEt25hr+ajL9cl4vzSUebAQBrQW/g0cZ630wy1FiGvhJq8X8kzZ/Gu1P IyXbrAvqJMRlbaP/kFoYHNKm4LE5aKuXimgd4AF0040EZFamQBiwSJZyOLFTsKpiPvJ5 qL3buevZdBVeu79RAkEv3mys/EudkpR5Mb4T/o5SbB0J1TKGewc3InnwYMwbjCKmUsfL Z7qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=KhX9GC6M; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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PADDING) - Use a for-loop to add/remove components in an arrays, so we can only maintain this array to make sure every component will be initialized properly Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 128 +++++++++++------- 1 file changed, 78 insertions(+), 50 deletions(-) -- 2.18.0 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index c0a38f5217ee..a5f5a0f8ea85 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -51,6 +51,7 @@ enum mtk_ovl_adaptor_comp_id { struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; + enum mtk_ddp_comp_id comp_id; int alias_id; }; @@ -67,19 +68,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = { }; static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = { - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 }, - [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 }, - [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 }, - [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 }, - [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 }, - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 }, + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 }, + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 }, + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 }, + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 }, + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 }, + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 }, + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 }, + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 }, + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 }, + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 }, + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 }, + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 }, + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 }, }; void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -192,6 +193,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) { comp = ovl_adaptor->ovl_adaptor_comp[i]; + if (!comp) + continue; ret = pm_runtime_get_sync(comp); if (ret < 0) { dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret); @@ -202,12 +205,23 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { comp = ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) + if (!comp) + continue; + + switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_RDMA: ret = mtk_mdp_rdma_clk_enable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) + break; + case OVL_ADAPTOR_TYPE_MERGE: ret = mtk_merge_clk_enable(comp); - else + break; + case OVL_ADAPTOR_TYPE_ETHDR: ret = mtk_ethdr_clk_enable(comp); + break; + default: + dev_err(dev, "Unknown type: %d\n", comp_matches[i].type); + } + if (ret) { dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret); goto clk_err; @@ -219,18 +233,33 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) clk_err: while (--i >= 0) { comp = ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) + + if (!comp) + continue; + + switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_RDMA: mtk_mdp_rdma_clk_disable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) + break; + case OVL_ADAPTOR_TYPE_MERGE: mtk_merge_clk_disable(comp); - else + break; + case OVL_ADAPTOR_TYPE_ETHDR: mtk_ethdr_clk_disable(comp); + break; + default: + dev_err(dev, "Unknown type: %d\n", comp_matches[i].type); + } } i = OVL_ADAPTOR_MERGE0; pwr_err: - while (--i >= 0) - pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]); + while (--i >= 0) { + comp = ovl_adaptor->ovl_adaptor_comp[i]; + if (!comp) + continue; + pm_runtime_put(comp); + } return ret; } @@ -244,13 +273,22 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev) for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { comp = ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) { + if (!comp) + continue; + + switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_RDMA: mtk_mdp_rdma_clk_disable(comp); pm_runtime_put(comp); - } else if (i < OVL_ADAPTOR_ETHDR0) { + break; + case OVL_ADAPTOR_TYPE_MERGE: mtk_merge_clk_disable(comp); - } else { + break; + case OVL_ADAPTOR_TYPE_ETHDR: mtk_ethdr_clk_disable(comp); + break; + default: + dev_err(dev, "Unknown type: %d\n", comp_matches[i].type); } } } @@ -313,36 +351,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev) void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex) { - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + int i; + + for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_add_comp(mutex, comp_matches[i].comp_id); + } } void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex) { - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + int i; + + for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id); + } } void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next) From patchwork Fri Jun 16 11:41:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 109092 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1309709vqr; Fri, 16 Jun 2023 05:37:28 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ40TfeUqYv6lBeXWPLqPV6QY3sZkub3SS+CmTe8hNTGybJ4sKGknGgiK3xEQ9TtpVPJ2kIE X-Received: by 2002:a62:84ce:0:b0:653:791b:d326 with SMTP id k197-20020a6284ce000000b00653791bd326mr9208615pfd.1.1686919048502; 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Due to hardware design, Mixer in VDOSYS1 requires width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled, we need Padding to deal with odd width. Please notice that even if the Padding is in bypass mode, settings in register must be cleared to 0, or undefined behaviors could happen. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 + .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 42 +++++- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_padding.c | 136 ++++++++++++++++++ 6 files changed, 184 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c -- 2.18.0 diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index d4d193f60271..5e4436403b8d 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -16,7 +16,8 @@ mediatek-drm-y := mtk_disp_aal.o \ mtk_dsi.o \ mtk_dpi.o \ mtk_ethdr.o \ - mtk_mdp_rdma.o + mtk_mdp_rdma.o \ + mtk_padding.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 2254038519e1..f9fdb1268aa5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg, const u32 *mtk_mdp_rdma_get_formats(struct device *dev); size_t mtk_mdp_rdma_get_num_formats(struct device *dev); +int mtk_padding_clk_enable(struct device *dev); +void mtk_padding_clk_disable(struct device *dev); +void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt); #endif diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index a5f5a0f8ea85..58db0d4cb5b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -26,13 +26,22 @@ #define MTK_OVL_ADAPTOR_LAYER_NUM 4 enum mtk_ovl_adaptor_comp_type { - OVL_ADAPTOR_TYPE_RDMA = 0, + OVL_ADAPTOR_TYPE_PADDING, + OVL_ADAPTOR_TYPE_RDMA, OVL_ADAPTOR_TYPE_MERGE, OVL_ADAPTOR_TYPE_ETHDR, OVL_ADAPTOR_TYPE_NUM, }; enum mtk_ovl_adaptor_comp_id { + OVL_ADAPTOR_PADDING0, + OVL_ADAPTOR_PADDING1, + OVL_ADAPTOR_PADDING2, + OVL_ADAPTOR_PADDING3, + OVL_ADAPTOR_PADDING4, + OVL_ADAPTOR_PADDING5, + OVL_ADAPTOR_PADDING6, + OVL_ADAPTOR_PADDING7, OVL_ADAPTOR_MDP_RDMA0, OVL_ADAPTOR_MDP_RDMA1, OVL_ADAPTOR_MDP_RDMA2, @@ -62,6 +71,7 @@ struct mtk_disp_ovl_adaptor { }; static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = { + [OVL_ADAPTOR_TYPE_PADDING] = "padding", [OVL_ADAPTOR_TYPE_RDMA] = "vdo1-rdma", [OVL_ADAPTOR_TYPE_MERGE] = "merge", [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr", @@ -76,6 +86,14 @@ static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = { [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 }, [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 }, [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 }, + [OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING0, 0 }, + [OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING1, 1 }, + [OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING2, 2 }, + [OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING3, 3 }, + [OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING4, 4 }, + [OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING5, 5 }, + [OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING6, 6 }, + [OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING7, 7 }, [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 }, [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 }, [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 }, @@ -90,6 +108,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); struct mtk_plane_pending_state *pending = &state->pending; struct mtk_mdp_rdma_cfg rdma_config = {0}; + struct device *padding_l; + struct device *padding_r; struct device *rdma_l; struct device *rdma_r; struct device *merge; @@ -106,6 +126,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, &pending->addr, (pending->pitch / fmt_info->cpp[0]), pending->x, pending->y, pending->width, pending->height); + padding_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx]; + padding_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx + 1]; rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx]; rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1]; merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; @@ -143,10 +165,15 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, rdma_config.color_encoding = pending->color_encoding; mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt); + if (padding_l) + mtk_padding_config(padding_l, cmdq_pkt); + if (use_dual_pipe) { rdma_config.x_left = l_w; rdma_config.width = r_w; mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt); + if (padding_r) + mtk_padding_config(padding_r, cmdq_pkt); } mtk_merge_start_cmdq(merge, cmdq_pkt); @@ -209,6 +236,9 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) continue; switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_PADDING: + ret = mtk_padding_clk_enable(comp); + break; case OVL_ADAPTOR_TYPE_RDMA: ret = mtk_mdp_rdma_clk_enable(comp); break; @@ -238,6 +268,9 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) continue; switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_PADDING: + mtk_padding_clk_disable(comp); + break; case OVL_ADAPTOR_TYPE_RDMA: mtk_mdp_rdma_clk_disable(comp); break; @@ -277,6 +310,10 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev) continue; switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_PADDING: + mtk_padding_clk_disable(comp); + pm_runtime_put(comp); + break; case OVL_ADAPTOR_TYPE_RDMA: mtk_mdp_rdma_clk_disable(comp); pm_runtime_put(comp); @@ -414,6 +451,9 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node, static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = { { + .compatible = "mediatek,mt8188-padding", + .data = (void *)OVL_ADAPTOR_TYPE_PADDING, + }, { .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_RDMA, }, { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 613093068bb4..ed5b5b8d6c2e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -977,6 +977,7 @@ static struct platform_driver * const mtk_drm_drivers[] = { &mtk_dsi_driver, &mtk_ethdr_driver, &mtk_mdp_rdma_driver, + &mtk_padding_driver, }; static int __init mtk_drm_init(void) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index eb2fd45941f0..562f2db47add 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -64,5 +64,5 @@ extern struct platform_driver mtk_dpi_driver; extern struct platform_driver mtk_dsi_driver; extern struct platform_driver mtk_ethdr_driver; extern struct platform_driver mtk_mdp_rdma_driver; - +extern struct platform_driver mtk_padding_driver; #endif /* MTK_DRM_DRV_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c b/drivers/gpu/drm/mediatek/mtk_padding.c new file mode 100644 index 000000000000..31b4efff968f --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_padding.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +/** + * struct mtk_padding - basic information of Padding + * @clk: Clock of the module + * @regs: Virtual address of the Padding for CPU to access + * @cmdq_reg: CMDQ setting of the Padding + * + * Every Padding should have different clock source, register base, and + * CMDQ settings, we stored these differences all together. + */ +struct mtk_padding { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; +}; + +int mtk_padding_clk_enable(struct device *dev) +{ + struct mtk_padding *padding = dev_get_drvdata(dev); + + return clk_prepare_enable(padding->clk); +} + +void mtk_padding_clk_disable(struct device *dev) +{ + struct mtk_padding *padding = dev_get_drvdata(dev); + + clk_disable_unprepare(padding->clk); +} + +void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_padding *padding = dev_get_drvdata(dev); + + /* bypass padding */ + mtk_ddp_write_mask(cmdq_pkt, GENMASK(1, 0), &padding->cmdq_reg, padding->regs, 0, + GENMASK(1, 0)); +} + +static int mtk_padding_bind(struct device *dev, struct device *master, void *data) +{ + return 0; +} + +static void mtk_padding_unbind(struct device *dev, struct device *master, void *data) +{ +} + +static const struct component_ops mtk_padding_component_ops = { + .bind = mtk_padding_bind, + .unbind = mtk_padding_unbind, +}; + +static int mtk_padding_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_padding *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get clk\n"); + return PTR_ERR(priv->clk); + } + + priv->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to do ioremap\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) { + dev_err(dev, "failed to get gce client reg\n"); + return ret; + } +#endif + + platform_set_drvdata(pdev, priv); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret = component_add(dev, &mtk_padding_component_ops); + if (ret) { + pm_runtime_disable(dev); + return dev_err_probe(dev, ret, "failed to add component\n"); + } + + return 0; +} + +static int mtk_padding_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_padding_component_ops); + return 0; +} + +static const struct of_device_id mtk_padding_driver_dt_match[] = { + { .compatible = "mediatek,mt8188-padding" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match); + +struct platform_driver mtk_padding_driver = { + .probe = mtk_padding_probe, + .remove = mtk_padding_remove, + .driver = { + .name = "mediatek-disp-padding", + .owner = THIS_MODULE, + .of_match_table = mtk_padding_driver_dt_match, + }, +};