From patchwork Thu Jun 15 17:32:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 108672 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp820147vqr; Thu, 15 Jun 2023 11:04:14 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7Kwom7S4Wij2HwqvHM5NgqtbUxjnAacTVD+HYkelvcNBt4wLkI1oM5u1bAZDAxsDerlTo6 X-Received: by 2002:a17:907:94c2:b0:97d:cdf4:719f with SMTP id dn2-20020a17090794c200b0097dcdf4719fmr17821080ejc.68.1686852254325; Thu, 15 Jun 2023 11:04:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686852254; cv=none; d=google.com; s=arc-20160816; b=xxDcTOFM29gJ5FgROMepRNKlXSagwDs+rHGmEgSS/H+hxpbNJui6Iw3cV3jy+4T5Fm n0lZHgzBA+T8fq4YrH+LBjp/lzy7uIWqz9Vwml9fcR0Q7Cjt6byaGWGz96IGnm0o90z2 SA8AothgZY1jYlyrOLIhXD9bSuQ2DDdpiqd5pRmcJjB9ZWv0AjuYPb5VCNphrAlYtV7n qx8ipYxqpPb/rFNwK1hvN0tRZC6p0HR9ejeBxDCV5v37a0XU/xIY3X9KZy2/Q4RDxQzv WOX3mJTH+cm/CF3hUiHV00VrVL6i7Fwa9Z7TtmG/g7QSIF9i3NMaQndNrkunxOHosQ9O KIWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=ULhKstKHH0NNIfx8JS1CSvEjMgd4WWDA5zJ0FSDUBXE=; b=SJD9kGH1+4o6/9SE97wC9keSY0vH+a/NiK/VMceK495OxNe20dqLdR3E95515eIsaR Z3vT1W0x3fYA/2GThRJcf8MBgYzCARFhUU54wYl8l+SEJvUefo/xpfIbyoiWrpNkctJu 2KF1KH/gLm+SG3Y6kn0ha6cI2DPLb/sOlW2I0jbjXPYExb8Vf6DBIo0toD01n6z99uVR E6zgPJe6sikFt43QtIVf/dlf99bD3f33PCgRiI9nsRiyasK+hUWDriXWsGFeAiLh2/gI /w4zk/8lRCaV+9v7Rp+JHUkFyUTfiAIA65dHc2SrJgYlJU6Ei/jHLzcAvDYzofZq05Tl XVSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XSTGDmEx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k11-20020a17090666cb00b00977c98c1412si10028739ejp.834.2023.06.15.11.03.50; Thu, 15 Jun 2023 11:04:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XSTGDmEx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235116AbjFOReH (ORCPT + 99 others); Thu, 15 Jun 2023 13:34:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236672AbjFOReF (ORCPT ); Thu, 15 Jun 2023 13:34:05 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 818D51FF9; Thu, 15 Jun 2023 10:34:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686850441; x=1718386441; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=+NwFs4+og2uCPUm6VzVvVeB7ddBS4TzUbKnCattLObI=; b=XSTGDmEx9i+eVBwVF0iZ+xjAOaDhiQEbthq4lMQQlTGImT4CmvAtBgPA sq+ouNnOiXS+XjBzCdYCMLke/gAKuvlxLNgFwit2+yjfCqqOwwrHZ8s4f hVGHqk+5hxRMouZeMIkHB1SgGXCiUnrzlc+9ShTgYmBK0IsKC4763ujLL F0GDvtSIs2H46jkAuwoxy3HUlOLXaZLikqbgXm2OM1byAhRdN7Jhng96M VDbd2J86/fn377IxzO2Z3aiyaodjJKAqFNnMP7Aplbjzvic53GfJ0ACtJ KmqsCbxSBXdfn/tjn9xACkUgyhkOPils2n8s7tg6828XkjOr/18XQyJYk Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10742"; a="338614021" X-IronPort-AV: E=Sophos;i="6.00,245,1681196400"; d="scan'208";a="338614021" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2023 10:33:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10742"; a="689863272" X-IronPort-AV: E=Sophos;i="6.00,245,1681196400"; d="scan'208";a="689863272" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga006.jf.intel.com with ESMTP; 15 Jun 2023 10:33:13 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, Kan Liang , stable@vger.kernel.org Subject: [PATCH] perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL Date: Thu, 15 Jun 2023 10:32:42 -0700 Message-Id: <20230615173242.3726364-1-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768792789828571840?= X-GMAIL-MSGID: =?utf-8?q?1768792789828571840?= From: Kan Liang When counting a FRONTEND event, the MSR_PEBS_FRONTEND is not correctly set on GNR and MTL p-core. The umask value for the FRONTEND events is changed on GNR and MTL. The new umask is missing in the extra_regs[] table. Add a dedicated intel_gnr_extra_regs[] for GNR and MTL p-core. Fixes: bc4000fdb009 ("perf/x86/intel: Add Granite Rapids") Signed-off-by: Kan Liang Cc: stable@vger.kernel.org --- arch/x86/events/intel/core.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 89b9c1cebb61..27f3a7b34bd5 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -349,6 +349,16 @@ static struct event_constraint intel_spr_event_constraints[] = { EVENT_CONSTRAINT_END }; +static struct extra_reg intel_gnr_extra_regs[] __read_mostly = { + INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), + INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), + INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), + INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), + INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), + INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), + INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), + EVENT_EXTRA_END +}; EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); @@ -6496,6 +6506,7 @@ __init int intel_pmu_init(void) case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_EMERALDRAPIDS_X: x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; + x86_pmu.extra_regs = intel_spr_extra_regs; fallthrough; case INTEL_FAM6_GRANITERAPIDS_X: case INTEL_FAM6_GRANITERAPIDS_D: @@ -6506,7 +6517,8 @@ __init int intel_pmu_init(void) x86_pmu.event_constraints = intel_spr_event_constraints; x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; - x86_pmu.extra_regs = intel_spr_extra_regs; + if (!x86_pmu.extra_regs) + x86_pmu.extra_regs = intel_gnr_extra_regs; x86_pmu.limit_period = spr_limit_period; x86_pmu.pebs_ept = 1; x86_pmu.pebs_aliases = NULL; @@ -6650,6 +6662,7 @@ __init int intel_pmu_init(void) pmu->pebs_constraints = intel_grt_pebs_event_constraints; pmu->extra_regs = intel_grt_extra_regs; if (is_mtl(boot_cpu_data.x86_model)) { + x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].extra_regs = intel_gnr_extra_regs; x86_pmu.pebs_latency_data = mtl_latency_data_small; extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;