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[8.43.85.97]) by mx.google.com with ESMTPS id mj8-20020a170906af8800b00977cc53e8fbsi8618438ejb.974.2023.06.14.18.20.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 18:20:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="Ux+fw4/k"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 68D2A3858C1F for ; Thu, 15 Jun 2023 01:20:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 68D2A3858C1F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686792022; bh=RDrOtygXP2zagjySfGBwZ1ucqCvXhmXOkH2d1DjY5aY=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=Ux+fw4/k3bxNwkWWNb1L56YFt+0tBOgJg31hyh6iPySvqpttnCUiSuzkPqUZ/zV7i kC4AuXik/wd6CR0Y3b7a1B1DjrfiTgaNZOg0QyE58+9H6Dh4e2r1yxJEBRddhJWs+Y gssipTUFM2GtGpwERpIq8obFIBKpGytqZ0g1+KAs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 603BF3858C1F for ; Thu, 15 Jun 2023 01:19:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 603BF3858C1F X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="445148829" X-IronPort-AV: E=Sophos;i="6.00,243,1681196400"; d="scan'208";a="445148829" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2023 18:19:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="689596988" X-IronPort-AV: E=Sophos;i="6.00,243,1681196400"; d="scan'208";a="689596988" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga006.jf.intel.com with ESMTP; 14 Jun 2023 18:19:37 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 53E7B10056B5; Thu, 15 Jun 2023 09:19:36 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: Lehua Ding Subject: [committed] RISC-V: Ensure vector args and return use function stack to pass [PR110119] Date: Thu, 15 Jun 2023 09:19:34 +0800 Message-Id: <20230615011934.2262108-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768675753180010136?= X-GMAIL-MSGID: =?utf-8?q?1768729633137496644?= From: Lehua Ding The V2 patch address comments from Juzhe, thanks. Hi, The reason for this bug is that in the case where the vector register is set to a fixed length (with `--param=riscv-autovec-preference=fixed-vlmax` option), TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be passed through two scalar registers, but when GCC calls FUNCTION_VALUE (call function riscv_get_arg_info inside) it returns NULL_RTX. These two functions are not unified. The current treatment is to pass all vector arguments and returns through the function stack, and a new calling convention for vector registers will be added in the future. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/ https://github.com/palmer-dabbelt/riscv-elf-psabi-doc/commit/126fa719972ff998a8a239c47d506c7809aea363 Best, Lehua gcc/ChangeLog: PR target/110119 * config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for vector mode (riscv_pass_by_reference): Return true for vector mode gcc/testsuite/ChangeLog: PR target/110119 * gcc.target/riscv/rvv/base/pr110119-1.c: New test. * gcc.target/riscv/rvv/base/pr110119-2.c: New test. --- gcc/config/riscv/riscv.cc | 17 ++++++++---- .../gcc.target/riscv/rvv/base/pr110119-1.c | 26 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr110119-2.c | 26 +++++++++++++++++++ 3 files changed, 64 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index dd5361c2bd2..e5ae4e81b7a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3915,13 +3915,13 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, riscv_pass_in_vector_p (type); } - /* TODO: Currently, it will cause an ICE for --param - riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here - let GCC generate loads/stores. Ideally, we should either warn the user not - to use an RVV vector type as function argument or support the calling - convention directly. */ + /* All current vector arguments and return values are passed through the + function stack. Ideally, we should either warn the user not to use an RVV + vector type as function argument or support a calling convention + with better performance. */ if (riscv_v_ext_mode_p (mode)) return NULL_RTX; + if (named) { riscv_aggregate_field fields[2]; @@ -4106,6 +4106,13 @@ riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg) return false; } + /* All current vector arguments and return values are passed through the + function stack. Ideally, we should either warn the user not to use an RVV + vector type as function argument or support a calling convention + with better performance. */ + if (riscv_v_ext_mode_p (arg.mode)) + return true; + /* Pass by reference if the data do not fit in two integer registers. */ return !IN_RANGE (size, 0, 2 * UNITS_PER_WORD); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c new file mode 100644 index 00000000000..f16502bcfee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "riscv_vector.h" + +typedef int8_t vnx2qi __attribute__ ((vector_size (2))); + +__attribute__ ((noipa)) vnx2qi +f_vnx2qi (int8_t a, int8_t b, int8_t *out) +{ + vnx2qi v = {a, b}; + return v; +} + +__attribute__ ((noipa)) vnx2qi +f_vnx2qi_2 (vnx2qi a, int8_t *out) +{ + return a; +} + +__attribute__ ((noipa)) vint32m1_t +f_vint32m1 (int8_t *a, int8_t *out) +{ + vint32m1_t v = *(vint32m1_t *) a; + return v; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c new file mode 100644 index 00000000000..b233ff1e904 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gczve32x --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include +#include "riscv_vector.h" + +__attribute__ ((noipa)) vint32m1x3_t +foo1 (int32_t *in, int vl) +{ + vint32m1x3_t v = __riscv_vlseg3e32_v_i32m1x3 (in, vl); + return v; +} + +__attribute__ ((noipa)) void +foo2 (vint32m1x3_t a, int32_t *out, int vl) +{ + __riscv_vsseg3e32_v_i32m1x3 (out, a, vl); +} + +__attribute__ ((noipa)) vint32m1x3_t +foo3 (vint32m1x3_t a, int32_t *out, int32_t *in, int vl) +{ + __riscv_vsseg3e32_v_i32m1x3 (out, a, vl); + vint32m1x3_t v = __riscv_vlseg3e32_v_i32m1x3 (in, vl); + return v; +}