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Wed, 14 Jun 2023 15:01:20 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 35EF0uj4018430; Wed, 14 Jun 2023 15:01:07 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3r7271jay5-1; Wed, 14 Jun 2023 15:01:07 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 35EF17Ib018597; Wed, 14 Jun 2023 15:01:07 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 35EF17QS018590; Wed, 14 Jun 2023 15:01:07 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id DDAD845A1; Wed, 14 Jun 2023 20:31:06 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: quic_vbadigan@quicinc.com, quic_ramkri@quicinc.com, linux-arm-msm@vger.kernel.org, konrad.dybcio@linaro.org, Krishna chaitanya chundru , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Kishon Vijay Abraham I , Bjorn Helgaas , linux-pci@vger.kernel.org (open list:PCI ENDPOINT SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Subject: [PATCH RFC v1 1/3] PCI: endpoint: Add wakeup host API to EPC core Date: Wed, 14 Jun 2023 20:30:47 +0530 Message-Id: <1686754850-29817-2-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1686754850-29817-1-git-send-email-quic_krichai@quicinc.com> References: <1686754850-29817-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: BF0FECC41ivyOQxrc5i0x8T3TjiisACg X-Proofpoint-GUID: BF0FECC41ivyOQxrc5i0x8T3TjiisACg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-14_10,2023-06-14_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 mlxscore=0 mlxlogscore=654 adultscore=0 phishscore=0 suspectscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306140131 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768693378423740026?= X-GMAIL-MSGID: =?utf-8?q?1768693378423740026?= Endpoint cannot send any data/MSI when the device state is in D3cold or D3hot. Endpoint needs to bring the device back to D0 to send any kind of data. For this endpoint can send inband PME the device is in D3hot or toggle wake when the device is D3 cold. To support this adding wake up host to epc core. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/endpoint/pci-epc-core.c | 29 +++++++++++++++++++++++++++++ include/linux/pci-epc.h | 3 +++ 2 files changed, 32 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 46c9a5c..d203947 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -167,6 +167,35 @@ const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, EXPORT_SYMBOL_GPL(pci_epc_get_features); /** + * pci_epc_wakeup_host() - interrupt the host system + * @epc: the EPC device which has to interrupt the host + * @func_no: the physical endpoint function number in the EPC device + * @vfunc_no: the virtual endpoint function number in the physical function + * + * Invoke to wakeup host + */ +int pci_epc_wakeup_host(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + int ret; + + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) + return -EINVAL; + + if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + return -EINVAL; + + if (!epc->ops->wakeup_host) + return 0; + + mutex_lock(&epc->lock); + ret = epc->ops->wakeup_host(epc, func_no, vfunc_no); + mutex_unlock(&epc->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(pci_epc_wakeup_host); + +/** * pci_epc_stop() - stop the PCI link * @epc: the link of the EPC device that has to be stopped * diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 301bb0e..a8496be 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -59,6 +59,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type) * @start: ops to start the PCI link * @stop: ops to stop the PCI link * @get_features: ops to get the features supported by the EPC + * @wakeup_host: ops to wakeup the host * @owner: the module owner containing the ops */ struct pci_epc_ops { @@ -88,6 +89,7 @@ struct pci_epc_ops { void (*stop)(struct pci_epc *epc); const struct pci_epc_features* (*get_features)(struct pci_epc *epc, u8 func_no, u8 vfunc_no); + int (*wakeup_host)(struct pci_epc *epc, u8 func_no, u8 vfunc_no); struct module *owner; }; @@ -232,6 +234,7 @@ int pci_epc_start(struct pci_epc *epc); void pci_epc_stop(struct pci_epc *epc); const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no); +int pci_epc_wakeup_host(struct pci_epc *epc, u8 func_no, u8 vfunc_no); enum pci_barno pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features); enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features From patchwork Wed Jun 14 15:00:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 108009 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp32548vqr; Wed, 14 Jun 2023 08:30:19 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7RRsVhEZ1Q2E4keqf7xCR+2yBsZ9bIq9QgbM3U7sMEYuxEHztqNDEYMQp4qn9L5PWtVyuB X-Received: by 2002:a17:902:8602:b0:1ab:d6f:51b0 with SMTP id f2-20020a170902860200b001ab0d6f51b0mr11739243plo.18.1686756619221; Wed, 14 Jun 2023 08:30:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686756619; cv=none; d=google.com; s=arc-20160816; b=oRsF1XDPR1AWvAZV8Ropal6zJYfqqCSR5HZ3UVyKTFBlxYK+kuL+qldWas39NAK0hd mmWlNMZHq2YWQPkrB6/pF8b4qTHrMWwk1ywl0X+kO/QBo4mvoskCktsUYtFcfQJhsE7L hMflr5Y0T6e43SJSdCBjHOsHoUSONjbTJqsjKLWiOxN35XDl5j1U7yWAPehzqmNI8KQY nhMgNBdJhdB+RGoZ+O/wMYZ1LjqeU9wdj8nl1lIlKLncvVMJg8w6jwvTcw6b8F20u6yr NtxAXioHeqnuC3p4vJOEhxQS+sbSQwOwAidh3WG5wxqHV9dctzt/TVzh9xnvHcnKvZPj Ez3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=vqJWExu1DJam83x+oYh9SasCk//OcKLC5ZJsLEOuE9U=; b=b9X1YLDgx9qDPqIFSnIijzMIWt7HLys9f3RjG7SGdokQLno3S0UvPyILqjVx+ExauB TJAPJcAQmB4v2x+fTTsxTHFWfufe4Dygfp+XJkb9viuoaU8Z8G9KEXJZzqCuZJAde0Tf pXYvGiD3LwILwhuLUuy1LN3jOKflDXJtYksA8fkRZL0MSJcxrccdKftM7SSLli0UKaae upEzMVYfnPqolGymQPsjFfKpAJRVDEww3gzFtWcwu3KVAMFZT4nuQpNwgNFESLLlvafu JYS0MizAWE/pwY+Wj69L3BahFbTZjpKDjNhtgUgJWg13hbA//vNWNuO+4i1esgA43o6E /NuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kdTIuEeJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-ep.c | 11 +++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index f9182f8..60cc323 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -463,6 +463,16 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) return ep->ops->get_features(ep); } +static int dw_pcie_ep_wakeup_host(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + struct dw_pcie_ep *ep = epc_get_drvdata(epc); + + if (!ep->ops->wakeup_host) + return -EINVAL; + + return ep->ops->wakeup_host(ep, func_no); +} + static const struct pci_epc_ops epc_ops = { .write_header = dw_pcie_ep_write_header, .set_bar = dw_pcie_ep_set_bar, @@ -477,6 +487,7 @@ static const struct pci_epc_ops epc_ops = { .start = dw_pcie_ep_start, .stop = dw_pcie_ep_stop, .get_features = dw_pcie_ep_get_features, + .wakeup_host = dw_pcie_ep_wakeup_host, }; int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 79713ce..e338591 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -330,6 +330,8 @@ struct dw_pcie_ep_ops { * driver. */ unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no); + + int (*wakeup_host)(struct dw_pcie_ep *ep, u8 func_no); }; struct dw_pcie_ep_func { From patchwork Wed Jun 14 15:00:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 108007 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp32132vqr; Wed, 14 Jun 2023 08:29:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4iAL3EfQ/tMK6NXURmk3XGpWxVUSm6qVi0e/z/D6aAZ2rpkozjWe2q0bDZiEYttBTKFEc4 X-Received: by 2002:a17:90a:341:b0:25c:1138:d97c with SMTP id 1-20020a17090a034100b0025c1138d97cmr1691622pjf.24.1686756588914; Wed, 14 Jun 2023 08:29:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686756588; cv=none; d=google.com; s=arc-20160816; b=tiHSkQMERigXVwCV+C7apWEsfjKW/JPzEgtlj5xEAm85SbdXXk9yjZeoo0BoPJfzgj PHLUL2WbJpT7zj0/FpEOlA8RkRpfNxKTul4VLfXdnoF9D3IvfOIkBLDhVOgIrm1VVTO2 EjomRveXKVLuN9gqPXVW/79JzLkAXY8awqiNgH5GP4atIrrM6xlzaGxQuUeniQHR6d2R KD7NbdudtEYbulCs7t4oJ7ZALmT71RdelU9OgL1NXSt3Q5PIrIlegxA+36iW2fiYKBEI GZm89Iy2iRZOnm4n3DFwami3iNLdAnsJ0cL1lVf1ckLeB7vMhCoKTZ018pLCUmXSB9nJ r3RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=2+pO9+6YtfcoOB3pvUjrJKOPEF2iL6mRrIG/MmOjYfQ=; b=SSI7Hc7ih4+6qeDEQFZuByKtUzrbCuLlYGyroZ3ZNXouVM34Zqe+ao7GveExv/44fc VeFg+koCE4pB0x0skXHWwpB62yxnbXjH39BUWOGRCmvb5Ow15G8+Ro/kl/WdFv9d1Oty fQEFHFNA2u9m9T97wg2CEIfnobf1W0q/sh1rggN0pCdOsVBKBJsgESs1a+SYqqJip0Dk j7heigzkt52mBni+73e4GZoZnN79WxzDfTTO74MNBmhiUhmDNn1RK2squd+3Xp8bAx/y Tyd4FOs7m8DvJOibuRBch6+Jm0R+YWIsYja9g7NrceOlH6/K2eNIvtgO+UH4zy7BfkJD BcGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=QiExWRnu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 34 +++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 5d146ec..916a138 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -91,6 +91,7 @@ /* PARF_PM_CTRL register fields */ #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1) #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) +#define PARF_PM_CTRL_XMT_PME BIT(4) #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) /* PARF_MHI_CLOCK_RESET_CTRL fields */ @@ -794,10 +795,43 @@ static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) dw_pcie_ep_reset_bar(pci, bar); } +static int qcom_pcie_ep_wakeup_host(struct dw_pcie_ep *ep, u8 func_no) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); + struct device *dev = pci->dev; + u32 perst, dstate, val; + + perst = gpiod_get_value(pcie_ep->reset); + /* Toggle wake GPIO when device is in D3 cold */ + if (perst) { + dev_info(dev, "Device is in D3 cold toggling wake\n"); + gpiod_set_value_cansleep(pcie_ep->wake, 1); + usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); + gpiod_set_value_cansleep(pcie_ep->wake, 0); + return 0; + } + + dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & + DBI_CON_STATUS_POWER_STATE_MASK; + if (dstate == 3) { + dev_info(dev, "Device is in D3 hot sending inband PME\n"); + val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); + val |= PARF_PM_CTRL_XMT_PME; + writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); + } else { + dev_err(dev, "Device is not in D3 state wakeup is not supported\n"); + return -EPERM; + } + + return 0; +} + static const struct dw_pcie_ep_ops pci_ep_ops = { .ep_init = qcom_pcie_ep_init, .raise_irq = qcom_pcie_ep_raise_irq, .get_features = qcom_pcie_epc_get_features, + .wakeup_host = qcom_pcie_ep_wakeup_host, }; static int qcom_pcie_ep_probe(struct platform_device *pdev)