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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:49 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:32 +0200 Subject: [PATCH v2 1/7] clk: qcom: gpucc-sm6350: Introduce index-based clk lookup MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v2-1-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=2501; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=TaMoHmTX5YmIOUIdAoElMKm2cSA2iQeh1gPxDTztMHU=; b=SuDstwjNjC4hB4jFdESHz9+jus8boaBzbYU+NNQHiLZongyDXxnapKuBEHAt5EBMcs95Y2i/H TdQqQNj02JUCwkN8winp20RjQqBJuUrth0siHnCXo/wmoKj7gHVe7RQ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768678019894133614?= X-GMAIL-MSGID: =?utf-8?q?1768678019894133614?= Add the nowadays-prefered and marginally faster way of looking up parent clocks in the device tree. It also allows for clock-names-independent operation, so long as the order (which is enforced by schema) is kept. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6350.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c index ef15185a99c3..a9887d1f0ed7 100644 --- a/drivers/clk/qcom/gpucc-sm6350.c +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -24,6 +24,12 @@ #define CX_GMU_CBCR_WAKE_MASK 0xF #define CX_GMU_CBCR_WAKE_SHIFT 8 +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + enum { P_BI_TCXO, P_GPLL0_OUT_MAIN, @@ -61,6 +67,7 @@ static struct clk_alpha_pll gpu_cc_pll0 = { .hw.init = &(struct clk_init_data){ .name = "gpu_cc_pll0", .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, .fw_name = "bi_tcxo", }, .num_parents = 1, @@ -104,6 +111,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = { .hw.init = &(struct clk_init_data){ .name = "gpu_cc_pll1", .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, .fw_name = "bi_tcxo", }, .num_parents = 1, @@ -121,11 +129,11 @@ static const struct parent_map gpu_cc_parent_map_0[] = { }; static const struct clk_parent_data gpu_cc_parent_data_0[] = { - { .fw_name = "bi_tcxo" }, + { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .fw_name = "gcc_gpu_gpll0_clk" }, - { .fw_name = "gcc_gpu_gpll0_div_clk" }, + { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" }, + { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk" }, }; static const struct parent_map gpu_cc_parent_map_1[] = { @@ -138,12 +146,12 @@ static const struct parent_map gpu_cc_parent_map_1[] = { }; static const struct clk_parent_data gpu_cc_parent_data_1[] = { - { .fw_name = "bi_tcxo" }, + { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" }, { .hw = &crc_div.hw }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .fw_name = "gcc_gpu_gpll0_clk" }, + { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { From patchwork Wed Jun 14 11:35:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 107907 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1176051vqr; Wed, 14 Jun 2023 04:39:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7dVQXsdeUDkoe60fUWYnra+7liacymr2BJ63Mdr1VgWY314mCULxGcHsEJIuZFGz2A4ld2 X-Received: by 2002:a17:907:60d6:b0:974:6026:a315 with SMTP id hv22-20020a17090760d600b009746026a315mr15696136ejc.44.1686742792727; Wed, 14 Jun 2023 04:39:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686742792; cv=none; d=google.com; s=arc-20160816; b=Bmsq6hb2A+AGvLPuMMypRC/x5jfQz78A7FfUgMCN/kGdXST5wZHaUlgl1D/zJrvulE thJxs2vsq2VnaC6u551Zj5HXYz1KVjVhWwXM/2Dg6upKD+VokjLXRT2czTAlXQyby+bq /pxH/kYtf6iTxhXEJFF6mUlf6MEQ984M8VBYN+GTGZ9k9jysunBfkVF+z/eNxffWcXgr mGlUTpj5ZsB+wVumYQhJ6ZjZQs+Bohobb7OSyxXgu5COVi1fi0N71sbyiTvU7i/YKm/o IVC+pw6smDHqucmoH/ajGLSoOz7X6gkn0EQth0eXRIuCkf2RUqeDuPWPqMib1KzmXIY4 +duA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=qQ877MkpC4ehMBHierpFme4jBSlXee3tho/1k2lPnrc=; b=O6XdlDJNgyQYhNadJDYVo6lDVXKyrcU1ZvURilPW3PYpe7JjzSfzU4c4ujufFLJCNS AppHFcg1q85mYRSML7XgpQ6TvBf8XApoPq3ENFL2X52hEK7HWpIjCG6zKb0ALZjZ3WzM 50p1Rwvgok4a3LIW4LqIRkozHZDCq1k8xrnmbfPlwr74Q+G4YXQdHwwyqlzJnBfWdTH/ nGVF5arqwmD4nOodb2v/rO9+i3gAmbR2GuNrY7+Ld9B9g1vgw9JMGN0kIwOJzfSyxkLs UuWUqAa5pPQZa6gmN9iqL+aWNq3EcCJnknC0V8mjMEukpwFMc+tulqnPD59eAOn0+v5g aByg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uI93E48U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:50 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:33 +0200 Subject: [PATCH v2 2/7] clk: qcom: gpucc-sm6350: Fix clock source names MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v2-2-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=1472; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Um2mvoH0hgq2pxMG9SLY6mhwWzANPWf1u6+3THUrEME=; b=2C90kfo8MN0j6VNDnSDnGoAxAhAtouxdKh8jKaNG5fneNrIb81w/UW4+kwXuSrKmvexCRr9cz 8duNdf3C0VPCiFGebaCghiTiKRhyqiQs/KLXoL4Y3Rso3YuoKiDg1TT X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768678010715874940?= X-GMAIL-MSGID: =?utf-8?q?1768678010715874940?= fw_name for GCC inputs didn't match the bindings. Fix it. Fixes: 013804a727a0 ("clk: qcom: Add GPU clock controller driver for SM6350") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6350.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c index a9887d1f0ed7..0bcbba2a2943 100644 --- a/drivers/clk/qcom/gpucc-sm6350.c +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -132,8 +132,8 @@ static const struct clk_parent_data gpu_cc_parent_data_0[] = { { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" }, - { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk" }, + { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" }, + { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk_src" }, }; static const struct parent_map gpu_cc_parent_map_1[] = { @@ -151,7 +151,7 @@ static const struct clk_parent_data gpu_cc_parent_data_1[] = { { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" }, + { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { From patchwork Wed Jun 14 11:35:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 107919 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1186284vqr; Wed, 14 Jun 2023 04:57:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5XjZR7AFgVddg5SaGsaXJIFFGwXieNydy+rMWVi4vTDtz/5I7VO0Er0Bs319ED9SQxtUb7 X-Received: by 2002:a17:906:fe4d:b0:973:93e3:bc9a with SMTP id wz13-20020a170906fe4d00b0097393e3bc9amr14528961ejb.6.1686743841574; Wed, 14 Jun 2023 04:57:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686743841; cv=none; d=google.com; s=arc-20160816; b=Y50fCcMK/let8EHGmvCfEBwT/UZpbfpmZSJ2QjOq3LsbbWUA0BX2qfivBCq70TeeNX cepvxSFRZikCZZ0nsc5lY7oer6RrJJ1jfUULJed2w8Zr31PshmQzKIAja9QnUID1dzO4 JVk231wB6/2OcC+KehXV0xLi/q5g6th7m1DbHReu9xH34ICArtMBb+ntmbUSSdOiCwo5 Xb2wcokRzqAyPdMg9ghUGj44+jT5xx1XHezS8G55F5p5LuZvJqvj6gNkoRNGXyx8OvVB f47Lr/C/TxtrTfPKBb1raSUQOAr23HLE4CwKcwI1gsmktzlRw2e0h90F9bp6gyoXW0Vf gC2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=PbHzuVw9djUb2dacqpTuChV+YchmANRy5455/F4AJp0=; b=Wd7lW82PO+gLOrkLk6OrBTg5BlN7YMnykYM9M/6k9Gp2Em+1y0DdFuyP/HzRF4MzQ4 rl72L219elz9hW8krMx7vvcds4iivVjaRpB+KHfwQwLu7/qUkENKPyFMsSLwQFyJSF4s iQ2yX2abErS0DFm7LWWXnyr6Q51UFeHVH88q8Znj/aKGhqapKhmCThqvzOcDw/3qB0im p7wTZknE1MREydx90My3yc1jTp6K24YSTBBvkoLNI1KSZoEoZFtorWd6DiGEbH4wVvYm AezIozaS8Pg1PtbEB9OonOefJEqnxjo8nOWWB8ThdGeYDg3vAELHqQRDDfXMfqTePB7I igDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hEudXtbM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:52 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:34 +0200 Subject: [PATCH v2 3/7] arm64: dts: qcom: sm6350: Add GPUCC node MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v2-3-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=1415; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gsjvRRutg0p4O5/y2LMtWAUeMOWVStHD9z6YTRu1r8w=; b=ci/KzkaFWmBtpokctHZ0kQ1lRBx7DZqVYmrgzDc9/fI22dpniJyL96eFOt8B1wrTgBrY6DuQ4 TshDj9C0V5nDHLSxV12rpBEq6e+82I1p5hR0QeK08Hr8LJZx6qX4F1n X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768679110115138320?= X-GMAIL-MSGID: =?utf-8?q?1768679110115138320?= From: Konrad Dybcio Add and configure a node for the GPU clock controller. Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 30e77010aed5..fd35810bcfb5 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -1308,6 +1309,20 @@ compute-cb@5 { }; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm6350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK>, + <&gcc GCC_GPU_GPLL0_DIV_CLK>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm6350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; From patchwork Wed Jun 14 11:35:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 107909 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1176195vqr; Wed, 14 Jun 2023 04:40:10 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6qrKU3enqbvaueXNdKulDBbzKKlgtSVAUT30GUDG21YPFt0zoWBot7jpVl1z6gp5R88n2G X-Received: by 2002:a17:907:1c93:b0:97d:f8aa:6d37 with SMTP id nb19-20020a1709071c9300b0097df8aa6d37mr15912544ejc.61.1686742809806; Wed, 14 Jun 2023 04:40:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686742809; cv=none; d=google.com; s=arc-20160816; b=n4coM+M1N5YJeWK76BTQUNFsS6RQUE/nJrQ6UwCcudgzF91Q+hqWDH6/6jHv/wHozV OrQ3hVkVCFgRnFjT2gTevfoNsxsq40YZsz+bw6AkcPDlp1FjFhUx8Txffbi1uNrF8FJt 93NlsmyymjLwopplHZ68+0F5rus98LI58euAmmMKusBlDOJvnV6hOjhHdD5DgVWNEJ7j xBNIPsLD/jV5Am8dvhJVVEsGtiT587T+C7+4OM0nnVbw5t6yDoz37A720GmMUwagNOvA ABYC7D4PNQEYJyVZMYfZWTWSLs8f/RmERlj86+92cY5cIdf5Fw7chFfaS2bCCp5gcLla COTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=BT0FhlQTqZJwPJ3Zh5frLeDreQMYYDJ2nQ7BrmaR2ho=; b=BAMDU5d6l0mHAAwZNKQ0ZmA8jWt7AeO/cVHeq6V8Oieq+nhS+wIWU/33BPWv96zEE4 xj4CkdY5lURw5BadnfxQtbOuNG/dEdjzHYc79QEUybePxvn2BnhdSePSfdz/In8/VCIJ kG/CrV+qShU0CQlgdvqjDhXhLo54nmzLnGfIF0v6dCSyzb2bKYZJLee1whAcAM1DjAyd IVrilreWEhB+bhc5KGZQo+t8GPzPmh44rTB++f8fbca0u+jzdL+KFE0wUCY7dgqD04oj 2cU/jyeRQqh4Hi0Catl96QYjDtd9lFtctAixYdtmiECBR6+gySrqWe/Y53Ewt+kL2KNG lW+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YEDYdRbk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index fd35810bcfb5..c0f34bc1d78c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -805,6 +805,18 @@ ipcc: mailbox@408000 { #mbox-cells = <2>; }; + qfprom: qfprom@784000 { + compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@2015 { + reg = <0x2015 0x1>; + bits = <0 8>; + }; + }; + rng: rng@793000 { compatible = "qcom,prng-ee"; reg = <0 0x00793000 0 0x1000>; From patchwork Wed Jun 14 11:35:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 107920 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1186522vqr; Wed, 14 Jun 2023 04:57:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4owISl5AsD4SprraQ9hflmfiD9WwYUKQxH9VdUbdFBVh5ooFxnPsXPKHfFOWWGiZWlFcP4 X-Received: by 2002:a17:907:5cc:b0:96a:9467:1dc7 with SMTP id wg12-20020a17090705cc00b0096a94671dc7mr13453221ejb.25.1686743866881; Wed, 14 Jun 2023 04:57:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686743866; cv=none; d=google.com; s=arc-20160816; b=LeeLtnYJK5+SOWZVz4YqIyxzUsZN8H1JswJywEFL1c+E2b/MJWrcUMfid/AsvD6H+4 BnLUlHew/b0ZGIzExn0U9mY0umFkS4Y2NPhbWsKG2t+GT4JAjQv6r46p7DtohpRuSC0d /NgRT1WidC0ICtgHiLuowBkoR6g7zQirwwcl8uovQaTtQe2cWzZ+AxulC53ntfbLBRMR Tlp8BKp+qXflX62uzLybphzU6n7dBGuTTOQGrhapRmSSFNsgjfJUv+xiCcL5oO4ghcvQ B1m7vh7k25BSz7Z9X1zufLZvZZ/prg5tBY4eavS/Uds1bq4KkmBNAQVt+I4ySA54EyiN y3nA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=5jaKkGkIsypo/HND0DbQ6vruiMEF8kdTc0ValZyEYo8=; b=YSN5nGQoUqkmBJqzBM1yrr8ZBROtAzimG02hyw6ka2iwBW04zw60FzwTTVGcmKNs3n LoE/kLdwcBSGazQ1jD82F1F435ipd9YeCdVH2nHjgFTXGe8sjwFjoqjCq2g1vmzELSwr FkGfHNVKXnJbX4aLtL9wP6KCsMYFaYBPPOd1zkM86YstkscMm2Y4uFd9kMdEPgfqpyL8 zLIK3TVFTOuxOEmcUgBxIkad/IOXVQMy5RrubRrzktrQLYsXiu47KheEJSmdGspO4bjP Wst+sR2H9w91/1nDxD33HjWC5nNWVgpA7AjvAPFNTKdwKfC04Wm8ntIGNn9DC0DFwx+A EG1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iCkpWb6E; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:56 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:36 +0200 Subject: [PATCH v2 5/7] arm64: dts: qcom: sm6350: Add GPU nodes MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v2-5-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=4658; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hebgvqDxcP5/jpVdGp5qyd6v0S/XcOR8k6z5qijdwvg=; b=Vslq+h8v6Ug4FxssYmahe0vqA8WKjBotTiq84VPW7dcNRIX6r6L/p5w1L/JqBNLQ9ccdcHfHC XFE2LLf5NqAB4fOBJiSiZCUrfoBZbcLGpgMireMDLERCvldwhzEOGVF X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768679136831669989?= X-GMAIL-MSGID: =?utf-8?q?1768679136831669989?= From: Konrad Dybcio Add Adreno, GPU SMMU and GMU nodes to hook up everything that the A619 needs to function properly. Co-developed-by: Luca Weiss Signed-off-by: Konrad Dybcio Signed-off-by: Luca Weiss Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 139 +++++++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index c0f34bc1d78c..d928e64e33ae 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1321,6 +1321,145 @@ compute-cb@5 { }; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-619.0", "qcom,adreno"; + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem"; + interrupts = ; + + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-level = ; + opp-supported-hw = <0x02>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = ; + opp-supported-hw = <0x04>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = ; + opp-supported-hw = <0x08>; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = ; + opp-supported-hw = <0x10>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + + opp-253000000 { + opp-hz = /bits/ 64 <253000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + }; + }; + + adreno_smmu: iommu@3d40000 { + compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; + reg = <0 0x03d40000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", + "bus", + "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; + reg = <0 0x03d6a000 0 0x31000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", + "gmu_pdc", + "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", + "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + status = "disabled"; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm6350-gpucc"; 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:58 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:37 +0200 Subject: [PATCH v2 6/7] arm64: dts: qcom: sm6350: Fix ZAP region MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v2-6-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=1250; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wA9dheoyA1ln4NvQBVP3cvzvxEDd9mOV0aNi6Nn+GZc=; b=jpOGbEnm0du6ha9Dcj9SzfnJzFLTmhh2bU0tQrKoZpzbTa8fxnpwnKcaeYhjNrLL1MxllBZxs I+/waT1dv17BdkxDs6nu341aPbP793c+5b2GtbPrSYjqkseyh55ky7G X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768679185012558059?= X-GMAIL-MSGID: =?utf-8?q?1768679185012558059?= From: Konrad Dybcio The previous ZAP region definition was wrong. Fix it. Note this is not a device-specific fixup, but a fixup to the generic PIL load address. Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index d928e64e33ae..cc72c4b4e7c0 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -634,11 +634,6 @@ pil_ipa_gsi_mem: memory@8b710000 { no-map; }; - pil_gpu_mem: memory@8b715400 { - reg = <0 0x8b715400 0 0x2000>; - no-map; - }; - pil_modem_mem: memory@8b800000 { reg = <0 0x8b800000 0 0xf800000>; no-map; @@ -659,6 +654,11 @@ removed_region: memory@c0000000 { no-map; }; + pil_gpu_mem: memory@f0d00000 { + reg = <0 0xf0d00000 0 0x1000>; + no-map; + }; + debug_region: memory@ffb00000 { reg = <0 0xffb00000 0 0xc0000>; no-map; From patchwork Wed Jun 14 11:35:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 107915 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1184580vqr; Wed, 14 Jun 2023 04:54:13 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6TG5ISt1rp4+1Y4ZtcC8pYh1FzfD4+XdLaJ1FERStVXyEHLzNNRY9rbUo9o9xrEt+fBaZF X-Received: by 2002:a17:907:d2a:b0:97d:cda7:f0c4 with SMTP id gn42-20020a1709070d2a00b0097dcda7f0c4mr15428052ejc.61.1686743653698; Wed, 14 Jun 2023 04:54:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686743653; cv=none; d=google.com; s=arc-20160816; b=HxEwI10i8DboC+th99448l8Vu4guIway5jFFbZibOD5Bv0nL3J7d9JQpzdotXt/flg 5hq+vGIeGQ/NWWd4yQ4HNGsIBQ7KqOtjp+0U7gAVR9gcsNEzkEE2l3ZjjkOSdXzeVXAC 1mhuRjcgCILJWUhlNwyjkNtiVaSw+gU1zH4htR+ANRVJoBR8OT2GAx/D5EsirBQnByIv QSub0DtTmGMh69uuwWcpR3VU7m+Al5ZpG3mpkEc43AkjAK6rpng8J0XoCnTgr36rL+UV xyd4GvXeZzOqnPlCmybhVkIWdKyVIlZ+KjBqAG7cqQkKWt+hQBp6BMvJ61JJNvJSnHKl X4Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=OK0KHsEEJflt/PIWV1+p8wHbMvB3nj/Mo8p4VCQArys=; b=NwRfEdDqBb8n1dXfw9vdUR2rAFmxvA3a6EEGtIMSzuoA3fQSyY7HEdFUqXaxxMizIi mmeIW/kJWA9X9KV1XGkgVfXs+39z7lA1j2H6HE3Sa4YlmWg8+2Sucevyvrm7dwyI6K1m CrC83yhdIAxecz+JSAQgDBP13wxL6HrzYBtMATmPldXCogPoPBTStp8vjYVmbxYKmX4l iY45FqEDqdXps7zIbidETJRBBMoonDqhy2IgB6ESuYFUIQXiX4KZSHH/8Zof+Tsw6jnL r3V8733Tv1N7I6jfLkpWfDn3itPNON888/hbxu1XYEfGJ+ykD/MPuCe9aQEq5AGBw9pU sq1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wkPePS6i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:36:00 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:38 +0200 Subject: [PATCH v2 7/7] arm64: dts: qcom: sm6350: Add DPU1 nodes MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v2-7-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=6597; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=bsnWCyLq477XRxbXa0duMpQVLlZ96KNWwe53+HWkyB8=; b=5m91ZIomh7uCzHHK4pGHxRokpxD7jUD6gGr3KVRapmAWyvlSqLoShF+hl2KJrjb+QO+wBNG7V 65EWxfz0B2OC0J30+k8Cf1KXcWsgHojKoEZFel1vB4H6/3fwpK8+Sre X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768678913219599361?= X-GMAIL-MSGID: =?utf-8?q?1768678913219599361?= From: Konrad Dybcio Add nodes required to enable MDSS/DPU1 on SM6350. There seem to be no additional changes required to support the derivative SoCs, such as SM7225. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 218 +++++++++++++++++++++++++++++++++++ 1 file changed, 218 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index cc72c4b4e7c0..7af6278d6b23 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2022, Luca Weiss */ +#include #include #include #include @@ -1869,6 +1870,223 @@ camcc: clock-controller@ad00000 { #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm6350-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "core"; + + power-domains = <&dispcc MDSS_GDSC>; + iommus = <&apps_smmu 0x800 0x2>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm6350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "rot", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM6350_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-373333333 { + opp-hz = /bits/ 64 <373333333>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-448000000 { + opp-hz = /bits/ 64 <448000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM6350_MX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm6350-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm6350-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;