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Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../bindings/display/mediatek/mediatek,ethdr.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml index 801fa66ae615..677882348ede 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -23,7 +23,11 @@ description: properties: compatible: - const: mediatek,mt8195-disp-ethdr + oneOf: + - const: mediatek,mt8195-disp-ethdr + - items: + - const: mediatek,mt8188-disp-ethdr + - const: mediatek,mt8195-disp-ethdr reg: maxItems: 7 From patchwork Wed Jun 14 07:31:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107793 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1072530vqr; Wed, 14 Jun 2023 01:04:52 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5JTbVRnqn6HRfDi9CePD9ZBreyIi5ZLK5zOkmA9NXA3aYpcmLo3dOHOxxiqThnEuNRX5ce X-Received: by 2002:a17:903:248:b0:1b2:4e00:a3a9 with SMTP id j8-20020a170903024800b001b24e00a3a9mr10409138plh.41.1686729892625; Wed, 14 Jun 2023 01:04:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686729892; cv=none; d=google.com; s=arc-20160816; b=hmUNTaJ06o+vcGlETGEjjY6iwH1RYVlyE9EFvIAZZaJO9VEQpb5z+AKbty/AiKNLdg uYHpF8fbK1vrhEAfKzDZRFupmobhqnyuAlJZyURcMQJ5nzJT+AdwlznujzrBc9HFSr+E iGR+mXGApl1TRdaxoRnAhkKn8JsIekfB3nBpgAyRHq07gTjxA8XN/tKDWC6mgj+G9F67 5dAnzsr34ssVS8vVzMzWWDvpwEJngG0SeipIVYeYV6yvfYt8u4DygFfaUNhLp7YL0kwG ljC6hXnqtDu+DBWxdWXO/sPVtQQdJNPSf0O/ceoDtUIcUJx80nr+kg1CooI8rxDd3kHc 2CWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Cfz9sH9lwt6+qccNYgMipqkrGxtN0q3GwRdSjw0DauA=; b=uT2sUVUk8o/9zKC2mJJ/ZrYuQ8/KmeoWfAxUYz6PaEo1tICB4+xyZ95z/MtTKiw7AA V3d0NrA+PWVgvq7IhtRiWUuBP8vRJhE/08R776Z+QZwk9k12a2MlRVla24RBkMth+Zsh jc6s4k8NHawnnaOE5X7aPFKxFfQrFacw6rKGUn6HT5Gfh9suvoXbs+ULh7rQf+11atF+ oHH4V8rdP1lOMA+sYJJQfMJEvntxl6F8nwzimcWlbVIcDXcRgcns20xjG/QhzUcaeln3 DTquc7boXIXAxCgPXNBv1laKY5EzjXnB4+JnmkFmlTwZB2MEc/FWso4xn44GujTF1pLS 73zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=vF4cMdzh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../bindings/display/mediatek/mediatek,mdp-rdma.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml index dd12e2ff685c..7570a0684967 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml @@ -21,7 +21,11 @@ description: properties: compatible: - const: mediatek,mt8195-vdo1-rdma + oneOf: + - const: mediatek,mt8195-vdo1-rdma + - items: + - const: mediatek,mt8188-vdo1-rdma + - const: mediatek,mt8195-vdo1-rdma reg: maxItems: 1 From patchwork Wed Jun 14 07:31:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107807 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1077718vqr; Wed, 14 Jun 2023 01:16:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5A1WMaj7yuKPhDXBqTBqsue+20BKopU9R02I6+zsK53tRfwaUV6hWybPxKsMjqPdaVH9AE X-Received: by 2002:a17:902:b416:b0:1b2:2c0c:d400 with SMTP id x22-20020a170902b41600b001b22c0cd400mr9417128plr.52.1686730597339; Wed, 14 Jun 2023 01:16:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686730597; cv=none; d=google.com; s=arc-20160816; b=z4OJYA4aiHA3ZsPxnw15ZxQ3MbcOz6r5qEK3jzSn3szdmrCAWLI+LhrrRSjyQLTACd CuWdwiEXSgpjqdUANra/y/4WArhBEttqXO40RC8fl/RRmGW2nrmacrh3HSdCS7UE4RyO dXGqAbTL8CbUzTBm55lzrkF4vFlPXA/l9hVzhc4TICS7dN2bD5xyeUXhBPYrFymHZRZA sMQbASmyfeWs9O82KGw2+88Tk9wsFTMi5tmntQ9QeQ8sXrtoaxyCRVjnAsPsBT5O2rYu GwxLMh4vL853AEzk7z/FLCY1eLQloRdwo8eFhuMEncZOOh49TUPA5wvCFvjOJdnksKRW LdMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=OVVWiQdAhDsoVl7MPahx1qZhjGtpKxL5lhbVi8FSpWw=; b=ZQlGLe2CHYOF/RBzzG79Dal5Q6y7IAp1LDX2/BGRv9IyO2LWA39H8JpIbI5kF31GVq HJvIpkoChTDkDEZPYCzUnklCo9OlXl0ZrFZ5Lyny4cEJfVMiGA20VDqfm0BWjzcq1mUE O7skAFS0AXCVP4RKBFOCj6K4R7CYjFf5qsJTbEuFyqtseaqUFjgy3wyh6IhqaGg1YTGI wfKC+E1uEC6psBHgF/HCpY3t3lLgzo78Xs6NW/gnavERHPVcC7HMD+tc7gsjxNFoHSHg Rh/vV7XoAar1QZEsxuv8082Q7bLm12lAyoVzkT+OjrXzXGPJLipuXLSvHM5CFGSiK0zv Dt8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=AEGkzgsq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++ 1 file changed, 3 insertions(+) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index eead5cb8636e..5c678695162e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -27,6 +27,9 @@ properties: - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge + - items: + - const: mediatek,mt8188-disp-merge + - const: mediatek,mt8195-disp-merge reg: maxItems: 1 From patchwork Wed Jun 14 07:31:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107800 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1076125vqr; Wed, 14 Jun 2023 01:12:55 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5t3rMG2drgtbbvGLkcZfhstXkzqyV49N1SBqyy+37kdwDwqt2DcMfq24kKX+4xD9h72LjW X-Received: by 2002:a17:907:36ca:b0:978:6b18:e935 with SMTP id bj10-20020a17090736ca00b009786b18e935mr12990238ejc.23.1686730375702; Wed, 14 Jun 2023 01:12:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686730375; cv=none; d=google.com; s=arc-20160816; b=FY3S9l4jAv+PNOMueSNNE3V0s8gDjgdqqWrLWxN56TCoyN4Arl+2WJPNPEVNeKjT2W +n/ZZXH0UH8n3VLjvUlao0PVU5TUOVONB0kmYph1kj9w/YjOJbLL9bDqV9MuIgNvgBUa 6s7jnp65B+qYuDHurk2zX5uS7tNc5MUK0QSRRQmB7DIV+QEA2A5eLQXbBaFnewMe47/v oHcS+qIxNp62SM3fwNp1fMCbTuaEK9vIK0E+4VG0yLwMnBbTCT6et4YbmYhzq0CgENI3 AuYVzi/nRBxihDAH12124K1VExbFVOTV3uCeKkWvEQGtnR0Fdx+3WxtyvabeYsK3fnhC iwug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=FkEHz1HvqkgwBa8saRQQZi20/yHJXurrVKHsWWSGwMk=; b=n12ryQ35hp0ad4ErktliKEd4guCd5fVStwI2VILAyMuxLTEzcMhStH2gcJqABghm/N vn4JMvinMEDpsVhNCRx8yTrebPrF93mcajodQZTlsT3a4PQ53tu+/c0CmkSwtdWvTsog gdSII5qG8hkDXTJLAQStr40FmkpgI5eeMTZNFQuRaYroV8CYPvWrWioRtkLyuW8glLZv iYByzzNS5+Q+9Ofs0vqQGteUf8vqjfTItm1j0VsbnLgrKVOzSp/yrqtvhIH4d7X0c3F+ Sc3jPSWUjjj+V4fUoqOlujljmi5GUT82mqQPjPUGDMUyge0UBD4DIAcPaVttuxt8Wq/g L18Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=sABsMQoQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id rp7-20020a170906d96700b0094f4ba4bcf6si7406029ejb.582.2023.06.14.01.12.31; Wed, 14 Jun 2023 01:12:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=sABsMQoQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243366AbjFNIA2 (ORCPT + 99 others); Wed, 14 Jun 2023 04:00:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243512AbjFNH7z (ORCPT ); Wed, 14 Jun 2023 03:59:55 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4E291FC9; Wed, 14 Jun 2023 00:59:35 -0700 (PDT) X-UUID: 83cda7dc0a8511ee9cb5633481061a41-20230614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FkEHz1HvqkgwBa8saRQQZi20/yHJXurrVKHsWWSGwMk=; b=sABsMQoQmRGRhHTmlGldAF2Zdyl5hyacI5Ih5ZQu5fUs4wITWyoFrtRj8qkQz5mREoww9uX1gPAD+iL8wQtBgNuPXkYURyc3S3K2vG3DKCz411cu1ql019aAHtLtA3K27Z73b1i89nD02GohaaOUlHFICIZeSqgxbrQ5YexSRME=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.26,REQID:0f52b03d-bc99-4cf2-8ddf-06211ef8f833,IP:0,U RL:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:20 X-CID-META: VersionHash:cb9a4e1,CLOUDID:1749933e-7aa7-41f3-a6bd-0433bee822f3,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 83cda7dc0a8511ee9cb5633481061a41-20230614 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 394784495; Wed, 14 Jun 2023 15:31:45 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 14 Jun 2023 15:31:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 14 Jun 2023 15:31:44 +0800 From: Hsiao Chien Sung To: Chun-Kuang Hu , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v2 04/15] dt-bindings: display: mediatek: padding: Add documentation for MT8188 Date: Wed, 14 Jun 2023 15:31:14 +0800 Message-ID: <20230614073125.17958-5-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230614073125.17958-1-shawn.sung@mediatek.com> References: <20230614073125.17958-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768664990748385382?= X-GMAIL-MSGID: =?utf-8?q?1768664990748385382?= PADDING is a new hardware module on MediaTek MT8188, Add device tree bindings documentation for it. Signed-off-by: Hsiao Chien Sung --- .../display/mediatek/mediatek,padding.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml -- 2.18.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml new file mode 100644 index 000000000000..390a518fa2cf --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PADDING + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: + MediaTek PADDING provides ability to VDOSYS1 to add pixels to width and height + of a layer with a specified color. + Since MIXER in VDOSYS1 requires the width of a layer to be 2-pixel-align, or + 4-pixel-align when ETHDR is enabled, we need PADDING to deal with odd width. + Please notice that even if the PADDING is in bypass mode, settings in the + registers must be cleared to 0, or undefined behaviors could happen. + +properties: + compatible: + const: mediatek,mt8188-padding + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: RDMA Clock + + mediatek,gce-client-reg: + description: + GCE (Global Command Engine) is a multi-core micro processor that helps + its clients to execute commands without interrupting CPU. This property + describes GCE client's information that is composed by 4 fields. + 1. pHandle of the GCE (there may be several GCE processors) + 2. Sub-system ID defined in the dt-binding like a user ID + (Please refer to include/dt-bindings/gce/-gce.h) + 3. Offset from base address of the subsys you are at + 4. Size of the register the client needs + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: pHandle of the GCE + - description: Subsys ID defined in the dt-binding + - description: Offset from base address of the subsys + - description: Size of register + maxItems: 1 + +required: + - compatible + - reg + - power-domains + - clocks + - mediatek,gce-client-reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + padding0: padding@1c11d000 { + compatible = "mediatek,mt8188-padding"; + reg = <0 0x1c11d000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; + }; + }; From patchwork Wed Jun 14 07:31:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107803 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1076805vqr; Wed, 14 Jun 2023 01:14:29 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7PNlW86y4Ze4/aXnxKob4l320AvAJcZHjRnMuvp6fMx6Lqz7KfPZuoVP2tO4tNRjq7W7U9 X-Received: by 2002:aa7:d350:0:b0:518:7af9:787d with SMTP id m16-20020aa7d350000000b005187af9787dmr1859498edr.15.1686730469618; Wed, 14 Jun 2023 01:14:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686730469; cv=none; d=google.com; s=arc-20160816; b=hoyk6fxYWjTaLUazFe1SOse4t4ciCb0F2fBFMtm6+aDMAKosAgRLOQ0Ti1VYVIOKuU NrN7B3V/i8gazrdjYzQqV3JRNiqtTvIzq70DcnRa1D8STQl0k/Oby0eSK820qID+I6hQ AJtFg83/8yevFTa8wKQKVEYLRgSWKEtlWfswjHQjq+iPmzgmL1Mph5bOqW7SomaHszjC fw0mTvpf5IDGpseackzjcJextknI/xGpDrTgkaVXtXgDhcADm+/6khQ3JxpZmeclTOh+ PyXbA4snTNk4jmAfRL2YnHhf/f223MM9EyzU6e+Isw4htiY8U/Qv9/RDrjo0KoIudqw/ oDBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=63zz3OIWKmol1iGJYfPdhwr3BoyTS3LsSeYyIjQ+eck=; b=GRJVE2J+79GlVMDxPLAMTpeAlW4m9qvTkXnqMjFmL/lerrVuf2nyx38Zn1MyQNsBc7 eOMxiB3bG0iFnwD/8xbHRnXHsXue7SNtJx2KXE3yqp1JWUQPBjIG8j3iEAw1Tf55voVb T8FJCuyyYZALzjnprQCWFk+mSkL2HhX3HJMEN6PRbJjpc9T1Mx066mgOFoFrQFO5Zpn+ QhiLgRnxgYRzNHh6qyjCmsjGCTlJskVzovcMXnKv1ZidxlYZTbxpWqA2hx/OdE790OaA sjEdyTmMkFVc+/WL4q1RYO4cVuBIie+PGem4BLujb1X1FKRD2EmoBpCqKLQyUYvqKYVV wdJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=KlKuZ8Jm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 536f5a5ebd24..642fa2e4736e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8188-vdosys0 + - mediatek,mt8188-vdosys1 - mediatek,mt8192-mmsys - mediatek,mt8195-vdosys1 - mediatek,mt8195-vppsys0 From patchwork Wed Jun 14 07:31:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107797 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1075466vqr; Wed, 14 Jun 2023 01:11:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4jgSLK2cK02AIlZyOVXfDsa9HBwj90QBleoID///1XSHATp4Mzsr1P8xD0JdXCN+vaOfPM X-Received: by 2002:a17:907:78c:b0:966:dd1:bae2 with SMTP id xd12-20020a170907078c00b009660dd1bae2mr12418763ejb.73.1686730283907; Wed, 14 Jun 2023 01:11:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686730283; cv=none; d=google.com; s=arc-20160816; b=di875kHI8W72f9f6gMtpxyEzxDKjzMd+IcLCYfM+sN/Tqkmij005FVVvc0EwaGZltp wF5ZTbqlpMTzzqx9sYqhy450T52y5Gk2XQ6o3OzuSYkymoF70ETdt7YbeIv/ISEOjGrb +EndAoq27PMSNDGMJkg3/Aqu8tpyBTBQIBYzecYKR6Q2OnBvtizieEgDeMI/4626uSl7 1dAQAIfFSfm01daRnmbLXQHMfc1XGy3t7wOTu7zDFqptCNAdp4MoiVrDMiCnNEx5+MaF QCc3E9i8oBqlOGTeUn6JH/2Q2oX8OJw890PaGxaAMK7redQgogLpK8q2/ePP8lBfJODB UFzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=oKWK5LrmhDnbk0er4ULE0uTrV/b11W3wR17dg++v3FA=; b=jA3GwJuLDrdAeAKlmz6EwK/QhijZFZLCNjlEWYpaufmoz9oYeWJDj5z8w7g322mRax yRp4vpmf/+Q5CdCfjflaS2nHKkzxLD2VDcgwXtUV4P0Vt5QnftyvrCwnvP3n1YBIcBe3 SSsU7Cr8hlcgkcd8OTC3i0vYzYPZcCwhqOnK5y6DsCPOg01Sum3vyfZGQ+DZ+wfId4c8 CRwAY69TbWYrPSnZ8kiw58sw7hEEWylGcMqU8fr/whYBNeIx7+wlWnz079DcSgUHqzn7 0ZNyCdtQfVw8eEhhQJ9k16Orps4j19P4LNq0Ki62PurBueGSWtUP6Qq0dEgJCJY7vWLw Gn6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=ZgiqZbD6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- include/dt-bindings/reset/mt8188-resets.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.18.0 diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h index 377cdfda82a9..1d92759dc67d 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -33,4 +33,24 @@ #define MT8188_TOPRGU_SW_RST_NUM 24 +#define MT8188_VDO0_RST_DISP_OVL0 0 +#define MT8188_VDO0_RST_FAKE_ENG0 1 +#define MT8188_VDO0_RST_DISP_CCORR0 2 +#define MT8188_VDO0_RST_DISP_MUTEX0 3 +#define MT8188_VDO0_RST_DISP_GAMMA0 4 +#define MT8188_VDO0_RST_DISP_DITHER0 5 +#define MT8188_VDO0_RST_DISP_WDMA0 6 +#define MT8188_VDO0_RST_DISP_RDMA0 7 +#define MT8188_VDO0_RST_DSI0 8 +#define MT8188_VDO0_RST_DSI1 9 +#define MT8188_VDO0_RST_DSC_WRAP0 10 +#define MT8188_VDO0_RST_VPP_MERGE0 11 +#define MT8188_VDO0_RST_DP_INTF0 12 +#define MT8188_VDO0_RST_DISP_AAL0 13 +#define MT8188_VDO0_RST_INLINEROT0 14 +#define MT8188_VDO0_RST_APB_BUS 15 +#define MT8188_VDO0_RST_DISP_COLOR0 16 +#define MT8188_VDO0_RST_MDP_WROT0 17 +#define MT8188_VDO0_RST_DISP_RSZ0 18 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ From patchwork Wed Jun 14 07:31:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107809 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1078398vqr; Wed, 14 Jun 2023 01:18:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ57D0w1v8i4nop9dMCl5hC6fiabaviIgvSJG/C4wcNRGbjYIhXSF1fsZdqvWVenCRXGb+rE X-Received: by 2002:a05:6a20:244a:b0:10c:b9ed:6a38 with SMTP id t10-20020a056a20244a00b0010cb9ed6a38mr1362066pzc.28.1686730705360; Wed, 14 Jun 2023 01:18:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686730705; cv=none; d=google.com; s=arc-20160816; b=TNnJHk2DUV75/Rw+NmixTTHsKSoKBlz96rwprZLaNkSo1Ed3J7A1q8MAcBJIvRW/ck Gu0yJiwuhzAtw6+TkspNNVwuKOwz/kwyaYR6lsn+Q4Jw4L4C/KJIF3W+VNtFCmMYb57n XYpkZ4dCtmH7qAvLsacOnckJ9nlhmQlXifI5QduvYoAJkrzlnvfVTgm2GVjKXyd/qEI/ RFpepAzPbK/+JlTC4IYQXBE0/hYU6F1r65SGkBEXyVSC//WhsBBkwDXzbbMX4ZZYXvSz QDrIHI2QVJ/roai1KnF56aBxCsnisZGYIRcbGcnFDnw7QEzw+5w83BnvPIPab/ba5vga gwAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=0M87TAcsA1CGccZfZA7+kYP/PoF+TJll+Ozq2jEyMrQ=; b=r7mq1MZal4dEJmu/WhygmLgD1lMU81h7J6XT08IdjSKdWwWEHNU0A32/YVh0MYmzcz tbJ45tkfAFBhMM4JNw4FQLjORV7fLubazJknoJovm+iHFPWElpRKHfEJMyVoxY1SV8mb CUanZC3rPDUVIB/NcQARq6Y4htCXsIRvTtfA7MXGBPO1DUPcCC1s/jEeG53ur78wrhcq im5ZLGjGKex5h1QfCe/LJRq1wsKugxLL63KPCfXwkgM/1KWs0p0SDkwjo7Tlgz4lBa4n YGLb12RskjpgQpTeyqFveDnEgt7DWasbD0/ovPoBM9MdEicFtqo8MwmE+3Blc7ApMfB/ ZMqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=pQ3hWe3a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- include/dt-bindings/reset/mt8188-resets.h | 55 +++++++++++++++++++++++ 1 file changed, 55 insertions(+) -- 2.18.0 diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h index 1d92759dc67d..377cf62cded2 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -53,4 +53,59 @@ #define MT8188_VDO0_RST_MDP_WROT0 17 #define MT8188_VDO0_RST_DISP_RSZ0 18 +#define MT8188_VDO1_RST_SMI_LARB2 0 +#define MT8188_VDO1_RST_SMI_LARB3 1 +#define MT8188_VDO1_RST_GALS 2 +#define MT8188_VDO1_RST_FAKE_ENG0 3 +#define MT8188_VDO1_RST_FAKE_ENG1 4 +#define MT8188_VDO1_RST_MDP_RDMA0 5 +#define MT8188_VDO1_RST_MDP_RDMA1 6 +#define MT8188_VDO1_RST_MDP_RDMA2 7 +#define MT8188_VDO1_RST_MDP_RDMA3 8 +#define MT8188_VDO1_RST_VPP_MERGE0 9 +#define MT8188_VDO1_RST_VPP_MERGE1 10 +#define MT8188_VDO1_RST_VPP_MERGE2 11 +#define MT8188_VDO1_RST_VPP_MERGE3 12 +#define MT8188_VDO1_RST_VPP_MERGE4 13 +#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14 +#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15 +#define MT8188_VDO1_RST_DISP_MUTEX 16 +#define MT8188_VDO1_RST_MDP_RDMA4 17 +#define MT8188_VDO1_RST_MDP_RDMA5 18 +#define MT8188_VDO1_RST_MDP_RDMA6 19 +#define MT8188_VDO1_RST_MDP_RDMA7 20 +#define MT8188_VDO1_RST_DP_INTF1_MMCK 21 +#define MT8188_VDO1_RST_DPI0_MM_CK 22 +#define MT8188_VDO1_RST_DPI1_MM_CK 23 +#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24 +#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25 +#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26 +#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27 +#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28 +#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29 +#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30 +#define MT8188_VDO1_RST_PADDING0 31 +#define MT8188_VDO1_RST_PADDING1 32 +#define MT8188_VDO1_RST_PADDING2 33 +#define MT8188_VDO1_RST_PADDING3 34 +#define MT8188_VDO1_RST_PADDING4 35 +#define MT8188_VDO1_RST_PADDING5 36 +#define MT8188_VDO1_RST_PADDING6 37 +#define MT8188_VDO1_RST_PADDING7 38 +#define MT8188_VDO1_RST_DISP_RSZ0 39 +#define MT8188_VDO1_RST_DISP_RSZ1 40 +#define MT8188_VDO1_RST_DISP_RSZ2 41 +#define MT8188_VDO1_RST_DISP_RSZ3 42 +#define MT8188_VDO1_RST_HDR_VDO_FE0 43 +#define MT8188_VDO1_RST_HDR_GFX_FE0 44 +#define MT8188_VDO1_RST_HDR_VDO_BE 45 +#define MT8188_VDO1_RST_HDR_VDO_FE1 46 +#define MT8188_VDO1_RST_HDR_GFX_FE1 47 +#define MT8188_VDO1_RST_DISP_MIXER 48 +#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49 +#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50 +#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51 +#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52 +#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ From patchwork Wed Jun 14 07:31:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107808 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1077763vqr; Wed, 14 Jun 2023 01:16:45 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4dxSwa/613vihw3dlsxhG+w+Kl9qEBAEUsOM7+eJRaQ7WYY/m+jr4f94X+e/TS8gOSfvPN X-Received: by 2002:a05:6a21:7899:b0:10c:ef9f:ddbd with SMTP id bf25-20020a056a21789900b0010cef9fddbdmr946563pzc.8.1686730605204; Wed, 14 Jun 2023 01:16:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686730605; cv=none; d=google.com; s=arc-20160816; b=N2e1RA0WIuOS2PDV5VXpsxPeTxkQ4LxIMjGmZto28LMq8ydWl1Vvjo7RTWvalks/hl Ueggnx8pkbtapjEKeF0CsuonSDCVoKXD9NsnSqlQ86JqeGlPLF9u9SbF3jK/5xbWP3wC TvB9HyTCGJ2ePMLvZLjsj0tzoD93Brt8aCCHu/Or6kAgPy34woT3nXFkh3cmEExQ6Zd1 AEOYKwxUlY1XDkE2pyIX44f3h92Hk4X71ESmjgED36/nRB4+B2GwDTXvtHfJW+NKQlg9 J9bse8kGrQUbdBjNLoDpkdlaaM5LaZO+sQmC8s/sRJJ/4wsafFhTLDLx6fDvja7OA0p+ 2uIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ICAkUkgY6yxm15UL8AyBy6w3Wyg7mdP+Ggt499kC1WQ=; b=TNgwb9rst3+ORT0scrWyDuMDMfFUA8TaM7vUW/q1aZIMnjTGeeoxyP5ZoeBzi15+S/ nFuM2fS+fXmgNlyzY1MwvFdnsjnZ2aovAs2CpgSYDol69UjLjgwiHPb6bhuPuK8lvp0a r/oUwscVWVKeGfnYudRJDS3epJzxPm9t6bqwyUQQRSfGmh3er1sM7eaJOaleey4j5Ikf yoaa5o/J0JDisIYzOyDxl+09ZGyJkYOy5w1lnBmMsi1RgYiN1leLdj2caXFNR37lUTXN hXAXfi9XrlSDt6xSvmGkukpwYKgSChoaNwPHq3w18ylydX1XQizFrg9tO8qsr1+GAMRO xmBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="Xpx24/bi"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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(172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 14 Jun 2023 15:31:44 +0800 From: Hsiao Chien Sung To: Chun-Kuang Hu , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v2 08/15] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys Date: Wed, 14 Jun 2023 15:31:18 +0800 Message-ID: <20230614073125.17958-9-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230614073125.17958-1-shawn.sung@mediatek.com> References: <20230614073125.17958-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768665231418957781?= X-GMAIL-MSGID: =?utf-8?q?1768665231418957781?= - Add register definitions for MT8188 - Add VDOSYS1 routing table - Update MUTEX definitions accordingly - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt8188-mmsys.h | 127 ++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 13 +++ drivers/soc/mediatek/mtk-mmsys.h | 29 +++++++ drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++ 4 files changed, 204 insertions(+) -- 2.18.0 diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h index 448cc3761b43..447afb72d95f 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -67,6 +67,57 @@ #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) +#define MT8188_VDO1_SW0_RST_B 0x1d0 +#define MT8188_VDO1_HDR_TOP_CFG 0xd00 +#define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 +#define MT8188_VDO1_MIXER_IN1_PAD 0xd40 +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 +#define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10 +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 +#define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18 +#define MT8188_MERGE4_SOUT_TO_DPI1_SEL BIT(2) +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL BIT(3) +#define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24 +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28 +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30 +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34 +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 +#define MT8188_SOUT_TO_MIXER_IN1_SEL 1 +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 +#define MT8188_SOUT_TO_MIXER_IN2_SEL 1 +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 +#define MT8188_SOUT_TO_MIXER_IN3_SEL 1 +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c +#define MT8188_SOUT_TO_MIXER_IN4_SEL 1 +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58 +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60 +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64 +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, @@ -146,4 +197,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { }, }; +static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = { + { + DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, + MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 + }, { + DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, + MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 + }, { + DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, + MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN1_SEL + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN2_SEL + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN3_SEL + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN4_SEL + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), + MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), + MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), + MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8188_MERGE4_SOUT_TO_DPI1_SEL + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), + MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL + } +}; + #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 9619faa796e8..3a81ef2bcc3c 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), }; +static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { + .clk_driver = "clk-mt8188-vdo1", + .routes = mmsys_mt8188_vdo1_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), + .sw0_rst_offset = MT8188_VDO1_SW0_RST_B, + .num_resets = 96, + .vsync_len = 1, +}; + static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table, @@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha_sel << (19 + idx), cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt); + if (mmsys->data->vsync_len) + mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0, + mmsys->data->vsync_len, cmdq_pkt); } EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config); @@ -431,6 +443,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data }, { .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data }, { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data }, + { .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data }, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data }, /* "mediatek,mt8195-mmsys" compatible is deprecated */ { .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data }, diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 6725403d2e3a..e4ab46017430 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -86,6 +86,34 @@ struct mtk_mmsys_routes { u32 val; }; +/** + * struct mtk_mmsys_driver_data - settings for the mmsys + * @clk_driver: Clock driver name that the mmsys is using + * (defined in drivers/clk/mediatek/clk-*.c). + * @routes: Routing table of the mmsys. + * It provides mux settings from one module to another. + * @num_routes: Array size of the routes. + * @sw0_rst_offset: Register offset for the reset control. + * @num_resets: Number of reset bits that are defined + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe) + * or VDOSYS (Video). Only VDOSYS needs to be added to drm driver. + * @vsync_len: VSYNC length of the MIXER. + * VSYNC is usually triggered by the connector, so its length is + * a fixed value as long as the frame rate is decided, but ETDHR and + * MIXER generate their own VSYNC due to hardware design, therefore + * MIXER has to sync with ETHDR by adjusting VSYNC length. + * On MT8195, there is no such setting so we use the gap between + * falling edge and rising edge of SOF (Start of Frame) signal to + * do the job, but since MT8188, VSNYC_LEN setting is introduced to + * solve the problem and is given 0x40 (ticks) as the default value. + * Please notice that this value has to be set to 1 (minimum) if + * ETHDR is bypassed, otherwise MIXER could wait too long and causing + * underflow. + * + * Each MMSYS (multi-media system) may have different settings, they may use + * different clock sources, mux settings, reset control ...etc., and these + * differences are all stored here. + */ struct mtk_mmsys_driver_data { const char *clk_driver; const struct mtk_mmsys_routes *routes; @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data { const u16 sw0_rst_offset; const u32 num_resets; const bool is_vppsys; + const u8 vsync_len; }; /* diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 26f3d9a41496..11dda20eb462 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -134,6 +134,22 @@ #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 #define MT8188_MUTEX_MOD2_DISP_PWM0 33 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24 +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30 +#define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 + #define MT8195_MUTEX_MOD_DISP_OVL0 0 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 @@ -265,6 +281,7 @@ #define MT8183_MUTEX_SOF_DPI0 2 #define MT8188_MUTEX_SOF_DSI0 1 #define MT8188_MUTEX_SOF_DP_INTF0 3 +#define MT8188_MUTEX_SOF_DP_INTF1 4 #define MT8195_MUTEX_SOF_DSI0 1 #define MT8195_MUTEX_SOF_DSI1 2 #define MT8195_MUTEX_SOF_DP_INTF0 3 @@ -276,6 +293,7 @@ #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) +#define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7) #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) @@ -446,6 +464,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0, + [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1, + [DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2, + [DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3, + [DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4, + [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, + [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, + [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, + [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, + [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, + [DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3, + [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4, + [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1, }; static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { @@ -606,6 +639,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = { MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, [MUTEX_SOF_DP_INTF0] = MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, + [MUTEX_SOF_DP_INTF1] = + MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1, }; static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { From patchwork Wed Jun 14 07:31:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107802 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1076213vqr; Wed, 14 Jun 2023 01:13:10 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6C0wSnN9GaJvM3m0Sv7E0AVAXjdOIeZ6pTyNO62+B9cCsEyTwfHdU7M52W3TmRgKUgc4kG X-Received: by 2002:a17:907:984:b0:974:1c99:7d3 with SMTP id bf4-20020a170907098400b009741c9907d3mr12510743ejc.25.1686730390117; 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Wed, 14 Jun 2023 15:31:46 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 14 Jun 2023 15:31:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 14 Jun 2023 15:31:45 +0800 From: Hsiao Chien Sung To: Chun-Kuang Hu , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v2 09/15] soc: mediatek: Support MT8188 VDOSYS1 PADDING in mtk-mmsys Date: Wed, 14 Jun 2023 15:31:19 +0800 Message-ID: <20230614073125.17958-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230614073125.17958-1-shawn.sung@mediatek.com> References: <20230614073125.17958-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,UPPERCASE_50_75,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768665005726522195?= X-GMAIL-MSGID: =?utf-8?q?1768665005726522195?= - Add PADDING components - Add MUTEX definitions for PADDING Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mutex.c | 16 ++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 8 ++++++++ 2 files changed, 24 insertions(+) -- 2.18.0 diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 11dda20eb462..6031c7012f22 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -142,6 +142,14 @@ #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_PADDING0 8 +#define MT8188_MUTEX_MOD_DISP1_PADDING1 9 +#define MT8188_MUTEX_MOD_DISP1_PADDING2 10 +#define MT8188_MUTEX_MOD_DISP1_PADDING3 11 +#define MT8188_MUTEX_MOD_DISP1_PADDING4 12 +#define MT8188_MUTEX_MOD_DISP1_PADDING5 13 +#define MT8188_MUTEX_MOD_DISP1_PADDING6 14 +#define MT8188_MUTEX_MOD_DISP1_PADDING7 15 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 @@ -472,6 +480,14 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0, + [DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1, + [DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2, + [DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3, + [DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4, + [DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5, + [DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6, + [DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7, [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 37544ea6286d..2584c1159d8d 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -50,6 +50,14 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_MDP_RDMA5, DDP_COMPONENT_MDP_RDMA6, DDP_COMPONENT_MDP_RDMA7, + DDP_COMPONENT_PADDING0, + DDP_COMPONENT_PADDING1, + DDP_COMPONENT_PADDING2, + DDP_COMPONENT_PADDING3, + DDP_COMPONENT_PADDING4, + DDP_COMPONENT_PADDING5, + DDP_COMPONENT_PADDING6, + DDP_COMPONENT_PADDING7, DDP_COMPONENT_MERGE0, DDP_COMPONENT_MERGE1, DDP_COMPONENT_MERGE2, From patchwork Wed Jun 14 07:31:20 2023 Content-Type: text/plain; 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Wed, 14 Jun 2023 15:31:46 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 14 Jun 2023 15:31:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 14 Jun 2023 15:31:45 +0800 From: Hsiao Chien Sung To: Chun-Kuang Hu , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v2 10/15] soc: mediatek: Support reset bit mapping in mmsys driver Date: Wed, 14 Jun 2023 15:31:20 +0800 Message-ID: <20230614073125.17958-11-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230614073125.17958-1-shawn.sung@mediatek.com> References: <20230614073125.17958-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768665368346824729?= X-GMAIL-MSGID: =?utf-8?q?1768665368346824729?= - Reset ID must starts from 0 and be consecutive, but the reset bits in our hardware design is not continuous, some bits are left unused, we need a map to solve the problem - Use old style 1-to-1 mapping if .rst_tb is not defined Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++ drivers/soc/mediatek/mtk-mmsys.h | 1 + 2 files changed, 10 insertions(+) -- 2.18.0 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 3a81ef2bcc3c..13249658721f 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -314,6 +314,15 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l u32 offset; u32 reg; + if (mmsys->data->rst_tb) { + if (id >= mmsys->data->num_resets) { + dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n", + id, mmsys->data->num_resets); + return -EINVAL; + } + id = mmsys->data->rst_tb[id]; + } + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); id = id % MMSYS_SW_RESET_PER_REG; reg = mmsys->data->sw0_rst_offset + offset; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index e4ab46017430..e18b355527de 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -119,6 +119,7 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; + const u8 *rst_tb; const u32 num_resets; const bool is_vppsys; const u8 vsync_len; From patchwork Wed Jun 14 07:31:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107804 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1076834vqr; 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Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt8188-mmsys.h | 26 ++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 3 +++ 2 files changed, 29 insertions(+) -- 2.18.0 diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h index 447afb72d95f..c3e3c5cfe931 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -3,6 +3,10 @@ #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H #define __SOC_MEDIATEK_MT8188_MMSYS_H +#include + +#define MT8188_VDO0_SW0_RST_B 0x190 + #define MT8188_VDO0_OVL_MOUT_EN 0xf14 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) @@ -118,6 +122,28 @@ #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 #define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c +static const u8 mmsys_mt8188_vdo0_rst_tb[] = { + [MT8188_VDO0_RST_DISP_OVL0] = 0, + [MT8188_VDO0_RST_FAKE_ENG0] = 2, + [MT8188_VDO0_RST_DISP_CCORR0] = 4, + [MT8188_VDO0_RST_DISP_MUTEX0] = 6, + [MT8188_VDO0_RST_DISP_GAMMA0] = 8, + [MT8188_VDO0_RST_DISP_DITHER0] = 10, + [MT8188_VDO0_RST_DISP_WDMA0] = 17, + [MT8188_VDO0_RST_DISP_RDMA0] = 19, + [MT8188_VDO0_RST_DSI0] = 21, + [MT8188_VDO0_RST_DSI1] = 22, + [MT8188_VDO0_RST_DSC_WRAP0] = 23, + [MT8188_VDO0_RST_VPP_MERGE0] = 24, + [MT8188_VDO0_RST_DP_INTF0] = 25, + [MT8188_VDO0_RST_DISP_AAL0] = 26, + [MT8188_VDO0_RST_INLINEROT0] = 27, + [MT8188_VDO0_RST_APB_BUS] = 28, + [MT8188_VDO0_RST_DISP_COLOR0] = 29, + [MT8188_VDO0_RST_MDP_WROT0] = 30, + [MT8188_VDO0_RST_DISP_RSZ0] = 31, +}; + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 13249658721f..88029500ed4d 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -87,6 +87,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .clk_driver = "clk-mt8188-vdo0", .routes = mmsys_mt8188_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), + .sw0_rst_offset = MT8188_VDO0_SW0_RST_B, + .rst_tb = mmsys_mt8188_vdo0_rst_tb, + .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb), }; static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { From patchwork Wed Jun 14 07:31:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107806 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1077671vqr; Wed, 14 Jun 2023 01:16:32 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7UqwGfyVNJbak/9olymS3BVb6uCQODRRHLHuBxgUNxoKrYXq0CNssK5QfoAUkp6Vv/8wg5 X-Received: by 2002:a17:907:9724:b0:979:7624:1f70 with SMTP id jg36-20020a170907972400b0097976241f70mr18053818ejc.18.1686730592017; Wed, 14 Jun 2023 01:16:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686730592; cv=none; d=google.com; s=arc-20160816; b=zLGqueQSkWGK4z3jqBKn02Ylj5q+GYqof8gQKKAQx8G7193CPezTKidCYRpS0+X8Ud /yhWG/bMn9GzwJEqIzC6udcr2JsQ4KZesjJY8PWBVu7n2sljtF4jY5ANyYP+JBXVVL2k ECHpQqD5z7lkaNCcaBLVR0EtqC7lHsdohoKs35JIzk2x2U0uSvs8F/N1B7sohIFtiRpf efd/RgvR2qM4XjDfsWVYrSNPM/urm/6Wu8DRB3Y3xnHqj8QeQNNBq7F/oLJkoGvJZciR OPg969cWw5NsZ7gVT0q0MDCC+TuXKN8JNET67kMcaxPGTW3avYDrQHkSZ1IvHCHLhwRx AOQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=sS/rh0HESZs7GJFffsey9XWbaMAteRe0fmkfhn5dPWY=; b=XS2AOuJzXL9WGKTxj/kBeFIB8Ya4YGsRQxbve2kySpc8mFskSLnjWo33AEOIZ3B6jj p1JN8locyp8zlb6Yj+3vIutRm/xWjoRWmz4nkF5U89aMfKTArpS9BtIWEcoPewTj0Xdn LKBxkXSJA/Au9MMTE2OWz8u2V2UJpDud5bc8ZlTm7fwPQowd8YLuYqBGS2O0VrW2vw7k HoZ+Y702hWpaUsG9xXQ4bsnq0u32CzvipjC9b67svSR6MCAyqN2MQg0A4KM8bQSsVxGU zkWl8b6ruBQ+uoLNJfunu0n13Hc4kMdcYXmqd7q+71YG+9xHu6gekK57lcmlMDXqDE10 xC+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=I4BJ1IgZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mt8188-mmsys.h | 57 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 3 +- 2 files changed, 59 insertions(+), 1 deletion(-) -- 2.18.0 diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h index c3e3c5cfe931..208d4dfedc1a 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = { [MT8188_VDO0_RST_DISP_RSZ0] = 31, }; +static const u8 mmsys_mt8188_vdo1_rst_tb[] = { + [MT8188_VDO1_RST_SMI_LARB2] = 0, + [MT8188_VDO1_RST_SMI_LARB3] = 1, + [MT8188_VDO1_RST_GALS] = 2, + [MT8188_VDO1_RST_FAKE_ENG0] = 3, + [MT8188_VDO1_RST_FAKE_ENG1] = 4, + [MT8188_VDO1_RST_MDP_RDMA0] = 5, + [MT8188_VDO1_RST_MDP_RDMA1] = 6, + [MT8188_VDO1_RST_MDP_RDMA2] = 7, + [MT8188_VDO1_RST_MDP_RDMA3] = 8, + [MT8188_VDO1_RST_VPP_MERGE0] = 9, + [MT8188_VDO1_RST_VPP_MERGE1] = 10, + [MT8188_VDO1_RST_VPP_MERGE2] = 11, + [MT8188_VDO1_RST_VPP_MERGE3] = 32 + 0, + [MT8188_VDO1_RST_VPP_MERGE4] = 32 + 1, + [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] = 32 + 2, + [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] = 32 + 3, + [MT8188_VDO1_RST_DISP_MUTEX] = 32 + 4, + [MT8188_VDO1_RST_MDP_RDMA4] = 32 + 5, + [MT8188_VDO1_RST_MDP_RDMA5] = 32 + 6, + [MT8188_VDO1_RST_MDP_RDMA6] = 32 + 7, + [MT8188_VDO1_RST_MDP_RDMA7] = 32 + 8, + [MT8188_VDO1_RST_DP_INTF1_MMCK] = 32 + 9, + [MT8188_VDO1_RST_DPI0_MM_CK] = 32 + 10, + [MT8188_VDO1_RST_DPI1_MM_CK] = 32 + 11, + [MT8188_VDO1_RST_MERGE0_DL_ASYNC] = 32 + 13, + [MT8188_VDO1_RST_MERGE1_DL_ASYNC] = 32 + 14, + [MT8188_VDO1_RST_MERGE2_DL_ASYNC] = 32 + 15, + [MT8188_VDO1_RST_MERGE3_DL_ASYNC] = 32 + 16, + [MT8188_VDO1_RST_MERGE4_DL_ASYNC] = 32 + 17, + [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] = 32 + 18, + [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] = 32 + 19, + [MT8188_VDO1_RST_PADDING0] = 32 + 20, + [MT8188_VDO1_RST_PADDING1] = 32 + 21, + [MT8188_VDO1_RST_PADDING2] = 32 + 22, + [MT8188_VDO1_RST_PADDING3] = 32 + 23, + [MT8188_VDO1_RST_PADDING4] = 32 + 24, + [MT8188_VDO1_RST_PADDING5] = 32 + 25, + [MT8188_VDO1_RST_PADDING6] = 32 + 26, + [MT8188_VDO1_RST_PADDING7] = 32 + 27, + [MT8188_VDO1_RST_DISP_RSZ0] = 32 + 28, + [MT8188_VDO1_RST_DISP_RSZ1] = 32 + 29, + [MT8188_VDO1_RST_DISP_RSZ2] = 32 + 30, + [MT8188_VDO1_RST_DISP_RSZ3] = 32 + 31, + [MT8188_VDO1_RST_HDR_VDO_FE0] = 64 + 0, + [MT8188_VDO1_RST_HDR_GFX_FE0] = 64 + 1, + [MT8188_VDO1_RST_HDR_VDO_BE] = 64 + 2, + [MT8188_VDO1_RST_HDR_VDO_FE1] = 64 + 16, + [MT8188_VDO1_RST_HDR_GFX_FE1] = 64 + 17, + [MT8188_VDO1_RST_DISP_MIXER] = 64 + 18, + [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] = 64 + 19, + [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] = 64 + 20, + [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] = 64 + 21, + [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] = 64 + 22, + [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = 64 + 23, +}; + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 88029500ed4d..7a6221f87669 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -97,7 +97,8 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { .routes = mmsys_mt8188_vdo1_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), .sw0_rst_offset = MT8188_VDO1_SW0_RST_B, - .num_resets = 96, + .rst_tb = mmsys_mt8188_vdo1_rst_tb, + .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb), .vsync_len = 1, }; From patchwork Wed Jun 14 07:31:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107798 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1075521vqr; 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Increase it to support VDOSYS1 in display driver. - Add compatible name for MT8188 VDOSYS1 (shares the same driver data with MT8195 VDOSYS1) Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.18.0 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6dcb4ba2466c..613093068bb4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -287,6 +287,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .main_path = mt8188_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), + .mmsys_dev_num = 2, }; static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { @@ -327,6 +328,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8186_mmsys_driver_data}, { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data}, + { .compatible = "mediatek,mt8188-vdosys1", + .data = &mt8195_vdosys1_driver_data}, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data}, { .compatible = "mediatek,mt8195-mmsys", From patchwork Wed Jun 14 07:31:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107799 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1075780vqr; Wed, 14 Jun 2023 01:12:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5k1hLQ2/K5DhmvIpZo7ErBqrs6B8ISh9et+mPEon25vWryDKTDZh6uooHvPJoD19PBYeO/ X-Received: by 2002:a17:906:58cb:b0:978:66bd:d771 with SMTP id e11-20020a17090658cb00b0097866bdd771mr16075479ejs.55.1686730331796; Wed, 14 Jun 2023 01:12:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686730331; cv=none; d=google.com; s=arc-20160816; b=XcmwBX+U4rfmEEY2mFlmIpjv0B4j699s1u53RksjDKek1lsuWiKZX9oqs7ztkVhgx4 xncQOEHATvTNu6Xcn48Xwb+93ZEA+FwHafs4f+ZLFshO3y+usvYi3Mrs+7A/8cOoUTPT 8TDU+aE6/kEXc3YPgUqPn0J/Uv+N0RLh08lCW11kEL2A0RVLTRz+YOl2wwz5HrWLuCoC owS6kGXX4/x7/iwpwK9CaRxUpXvAv8dhlLKwPqhXFx5pKmZzstzYX67vIXHXx8+gnKge 6x9qUcVZt9T6u/kQsj86gBBfAEu0WEfCZ5hYfuaE+Z37GbSh1h+eHXbMQ/2r0CeK4m7O bKkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=uJrhqEVUl+JgSBLetX8UvH1e137N/lC8nLdCIORzaaA=; b=WB7CQF8HkeE26ty8nlc2C4+M0fSLWdOqGrvnGuMnkR8oG71ljPh/gujLY8ab1q+Hv7 fApUaGuzOJut92fSYdAVO+qhynUzcfTLCJbKd2RRs/BO/8XnO9vaII2MH2uegIJxxAWi +pMKCGGtUrjKJgE9pBcaULy96FSoqDyCT+WZBl4AZoLBYx0/czflqU55fj759yqkoZsX kw9jG9S7lRIKXoyBDLC2KuhFniRNliMKrfqmVqlolNuPrnCipUnfchOMyemdK4I4mMA7 vRKMD7OqVkK74hYjZ05+qQFKT+KGEDPzFA01Yvlle49CvQ2cR0mUpLskLkux7AAp6eCG QI+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=awG1uaAs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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PADDING) - Use a for-loop to add/remove components in an arrays, so we can only maintain this array to make sure every component will be initialized properly Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 128 +++++++++++------- 1 file changed, 78 insertions(+), 50 deletions(-) -- 2.18.0 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index c0a38f5217ee..a5f5a0f8ea85 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -51,6 +51,7 @@ enum mtk_ovl_adaptor_comp_id { struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; + enum mtk_ddp_comp_id comp_id; int alias_id; }; @@ -67,19 +68,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = { }; static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = { - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 }, - [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 }, - [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 }, - [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 }, - [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 }, - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 }, + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 }, + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 }, + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 }, + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 }, + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 }, + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 }, + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 }, + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 }, + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 }, + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 }, + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 }, + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 }, + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 }, }; void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -192,6 +193,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) { comp = ovl_adaptor->ovl_adaptor_comp[i]; + if (!comp) + continue; ret = pm_runtime_get_sync(comp); if (ret < 0) { dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret); @@ -202,12 +205,23 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { comp = ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) + if (!comp) + continue; + + switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_RDMA: ret = mtk_mdp_rdma_clk_enable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) + break; + case OVL_ADAPTOR_TYPE_MERGE: ret = mtk_merge_clk_enable(comp); - else + break; + case OVL_ADAPTOR_TYPE_ETHDR: ret = mtk_ethdr_clk_enable(comp); + break; + default: + dev_err(dev, "Unknown type: %d\n", comp_matches[i].type); + } + if (ret) { dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret); goto clk_err; @@ -219,18 +233,33 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) clk_err: while (--i >= 0) { comp = ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) + + if (!comp) + continue; + + switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_RDMA: mtk_mdp_rdma_clk_disable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) + break; + case OVL_ADAPTOR_TYPE_MERGE: mtk_merge_clk_disable(comp); - else + break; + case OVL_ADAPTOR_TYPE_ETHDR: mtk_ethdr_clk_disable(comp); + break; + default: + dev_err(dev, "Unknown type: %d\n", comp_matches[i].type); + } } i = OVL_ADAPTOR_MERGE0; pwr_err: - while (--i >= 0) - pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]); + while (--i >= 0) { + comp = ovl_adaptor->ovl_adaptor_comp[i]; + if (!comp) + continue; + pm_runtime_put(comp); + } return ret; } @@ -244,13 +273,22 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev) for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { comp = ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) { + if (!comp) + continue; + + switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_RDMA: mtk_mdp_rdma_clk_disable(comp); pm_runtime_put(comp); - } else if (i < OVL_ADAPTOR_ETHDR0) { + break; + case OVL_ADAPTOR_TYPE_MERGE: mtk_merge_clk_disable(comp); - } else { + break; + case OVL_ADAPTOR_TYPE_ETHDR: mtk_ethdr_clk_disable(comp); + break; + default: + dev_err(dev, "Unknown type: %d\n", comp_matches[i].type); } } } @@ -313,36 +351,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev) void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex) { - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + int i; + + for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_add_comp(mutex, comp_matches[i].comp_id); + } } void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex) { - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + int i; + + for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id); + } } void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next) From patchwork Wed Jun 14 07:31:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 107794 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1072729vqr; Wed, 14 Jun 2023 01:05:14 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4QwGX+zQPCEgpSP+FR69ZqJUfP0kx9FUZ7vLP6bPGKKr7vcZnFSbgGEwdhTyGr7sROJFlA X-Received: by 2002:a05:6214:f26:b0:625:aa49:9ab5 with SMTP id iw6-20020a0562140f2600b00625aa499ab5mr19516538qvb.57.1686729914077; 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Since MIXER in VDOSYS1 requires the width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled, we need PADDING to deal with odd width. Please notice that even if the PADDING is in bypass mode, settings in the registers must be cleared to 0, or undefined behaviors could happen. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 + .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 42 +++++- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_padding.c | 127 ++++++++++++++++++ 6 files changed, 175 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c -- 2.18.0 diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index d4d193f60271..5e4436403b8d 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -16,7 +16,8 @@ mediatek-drm-y := mtk_disp_aal.o \ mtk_dsi.o \ mtk_dpi.o \ mtk_ethdr.o \ - mtk_mdp_rdma.o + mtk_mdp_rdma.o \ + mtk_padding.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 2254038519e1..f9fdb1268aa5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg, const u32 *mtk_mdp_rdma_get_formats(struct device *dev); size_t mtk_mdp_rdma_get_num_formats(struct device *dev); +int mtk_padding_clk_enable(struct device *dev); +void mtk_padding_clk_disable(struct device *dev); +void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt); #endif diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index a5f5a0f8ea85..58db0d4cb5b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -26,13 +26,22 @@ #define MTK_OVL_ADAPTOR_LAYER_NUM 4 enum mtk_ovl_adaptor_comp_type { - OVL_ADAPTOR_TYPE_RDMA = 0, + OVL_ADAPTOR_TYPE_PADDING, + OVL_ADAPTOR_TYPE_RDMA, OVL_ADAPTOR_TYPE_MERGE, OVL_ADAPTOR_TYPE_ETHDR, OVL_ADAPTOR_TYPE_NUM, }; enum mtk_ovl_adaptor_comp_id { + OVL_ADAPTOR_PADDING0, + OVL_ADAPTOR_PADDING1, + OVL_ADAPTOR_PADDING2, + OVL_ADAPTOR_PADDING3, + OVL_ADAPTOR_PADDING4, + OVL_ADAPTOR_PADDING5, + OVL_ADAPTOR_PADDING6, + OVL_ADAPTOR_PADDING7, OVL_ADAPTOR_MDP_RDMA0, OVL_ADAPTOR_MDP_RDMA1, OVL_ADAPTOR_MDP_RDMA2, @@ -62,6 +71,7 @@ struct mtk_disp_ovl_adaptor { }; static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = { + [OVL_ADAPTOR_TYPE_PADDING] = "padding", [OVL_ADAPTOR_TYPE_RDMA] = "vdo1-rdma", [OVL_ADAPTOR_TYPE_MERGE] = "merge", [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr", @@ -76,6 +86,14 @@ static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = { [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 }, [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 }, [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 }, + [OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING0, 0 }, + [OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING1, 1 }, + [OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING2, 2 }, + [OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING3, 3 }, + [OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING4, 4 }, + [OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING5, 5 }, + [OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING6, 6 }, + [OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING7, 7 }, [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 }, [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 }, [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 }, @@ -90,6 +108,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); struct mtk_plane_pending_state *pending = &state->pending; struct mtk_mdp_rdma_cfg rdma_config = {0}; + struct device *padding_l; + struct device *padding_r; struct device *rdma_l; struct device *rdma_r; struct device *merge; @@ -106,6 +126,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, &pending->addr, (pending->pitch / fmt_info->cpp[0]), pending->x, pending->y, pending->width, pending->height); + padding_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx]; + padding_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx + 1]; rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx]; rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1]; merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; @@ -143,10 +165,15 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, rdma_config.color_encoding = pending->color_encoding; mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt); + if (padding_l) + mtk_padding_config(padding_l, cmdq_pkt); + if (use_dual_pipe) { rdma_config.x_left = l_w; rdma_config.width = r_w; mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt); + if (padding_r) + mtk_padding_config(padding_r, cmdq_pkt); } mtk_merge_start_cmdq(merge, cmdq_pkt); @@ -209,6 +236,9 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) continue; switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_PADDING: + ret = mtk_padding_clk_enable(comp); + break; case OVL_ADAPTOR_TYPE_RDMA: ret = mtk_mdp_rdma_clk_enable(comp); break; @@ -238,6 +268,9 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) continue; switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_PADDING: + mtk_padding_clk_disable(comp); + break; case OVL_ADAPTOR_TYPE_RDMA: mtk_mdp_rdma_clk_disable(comp); break; @@ -277,6 +310,10 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev) continue; switch (comp_matches[i].type) { + case OVL_ADAPTOR_TYPE_PADDING: + mtk_padding_clk_disable(comp); + pm_runtime_put(comp); + break; case OVL_ADAPTOR_TYPE_RDMA: mtk_mdp_rdma_clk_disable(comp); pm_runtime_put(comp); @@ -414,6 +451,9 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node, static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = { { + .compatible = "mediatek,mt8188-padding", + .data = (void *)OVL_ADAPTOR_TYPE_PADDING, + }, { .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_RDMA, }, { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 613093068bb4..ed5b5b8d6c2e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -977,6 +977,7 @@ static struct platform_driver * const mtk_drm_drivers[] = { &mtk_dsi_driver, &mtk_ethdr_driver, &mtk_mdp_rdma_driver, + &mtk_padding_driver, }; static int __init mtk_drm_init(void) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index eb2fd45941f0..562f2db47add 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -64,5 +64,5 @@ extern struct platform_driver mtk_dpi_driver; extern struct platform_driver mtk_dsi_driver; extern struct platform_driver mtk_ethdr_driver; extern struct platform_driver mtk_mdp_rdma_driver; - +extern struct platform_driver mtk_padding_driver; #endif /* MTK_DRM_DRV_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c b/drivers/gpu/drm/mediatek/mtk_padding.c new file mode 100644 index 000000000000..bb32325287f6 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_padding.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +struct mtk_padding { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; +}; + +int mtk_padding_clk_enable(struct device *dev) +{ + struct mtk_padding *padding = dev_get_drvdata(dev); + + return clk_prepare_enable(padding->clk); +} + +void mtk_padding_clk_disable(struct device *dev) +{ + struct mtk_padding *padding = dev_get_drvdata(dev); + + clk_disable_unprepare(padding->clk); +} + +void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_padding *padding = dev_get_drvdata(dev); + + /* bypass padding */ + mtk_ddp_write_mask(cmdq_pkt, GENMASK(1, 0), &padding->cmdq_reg, padding->regs, 0, + GENMASK(1, 0)); +} + +static int mtk_padding_bind(struct device *dev, struct device *master, void *data) +{ + return 0; +} + +static void mtk_padding_unbind(struct device *dev, struct device *master, void *data) +{ +} + +static const struct component_ops mtk_padding_component_ops = { + .bind = mtk_padding_bind, + .unbind = mtk_padding_unbind, +}; + +static int mtk_padding_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_padding *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get clk\n"); + return PTR_ERR(priv->clk); + } + + priv->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to do ioremap\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) { + dev_err(dev, "failed to get gce client reg\n"); + return ret; + } +#endif + + platform_set_drvdata(pdev, priv); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret = component_add(dev, &mtk_padding_component_ops); + if (ret) { + pm_runtime_disable(dev); + return dev_err_probe(dev, ret, "failed to add component\n"); + } + + return 0; +} + +static int mtk_padding_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_padding_component_ops); + return 0; +} + +static const struct of_device_id mtk_padding_driver_dt_match[] = { + { .compatible = "mediatek,mt8188-padding" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match); + +struct platform_driver mtk_padding_driver = { + .probe = mtk_padding_probe, + .remove = mtk_padding_remove, + .driver = { + .name = "mediatek-disp-padding", + .owner = THIS_MODULE, + .of_match_table = mtk_padding_driver_dt_match, + }, +};