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Signed-off-by: Shenwei Wang Reviewed-by: Peng Fan Reviewed-by: Linus Walleij --- .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi index 815bd987b09b..5306d2b3fc3f 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -6,41 +6,82 @@ &lsio_gpio0 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 47 13>, + <&iomuxc 13 61 4>, + <&iomuxc 19 67 4>, + <&iomuxc 24 72 1>; }; &lsio_gpio1 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 4 74 5>, + <&iomuxc 9 80 16>; }; &lsio_gpio2 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 1 98 2>, + <&iomuxc 3 101 1>, + <&iomuxc 5 107 8>; }; &lsio_gpio3 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 115 4>, + <&iomuxc 9 121 1>, + <&iomuxc 10 120 1>, + <&iomuxc 11 123 1>, + <&iomuxc 12 122 1>, + <&iomuxc 13 125 1>, + <&iomuxc 14 124 1>, + <&iomuxc 16 126 1>, + <&iomuxc 17 128 1>, + <&iomuxc 18 131 1>, + <&iomuxc 19 130 1>, + <&iomuxc 20 133 1>, + <&iomuxc 21 132 1>, + <&iomuxc 22 129 1>, + <&iomuxc 23 134 1>; }; &lsio_gpio4 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 7 9 12>, + <&iomuxc 19 22 2>, + <&iomuxc 21 25 2>, + <&iomuxc 29 29 3>; }; &lsio_gpio5 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 32 3>, + <&iomuxc 3 36 6>, + <&iomuxc 9 43 3>; }; &lsio_gpio6 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 53 7>, + <&iomuxc 8 86 10>, + <&iomuxc 19 107 8>; }; &lsio_gpio7 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 8 22 2>, + <&iomuxc 10 25 2>, + <&iomuxc 16 44 2>; }; &lsio_mu0 { From patchwork Thu Oct 27 13:08:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 11791 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp226938wru; Thu, 27 Oct 2022 06:20:27 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7J7/duciw7FO9JZoBy39IsPWwu1fCm7vF83t6m4CpTqllLNndSWQ/sRjiY91fAocMVjh9W X-Received: by 2002:a17:907:8a1c:b0:78d:ef44:7759 with SMTP id sc28-20020a1709078a1c00b0078def447759mr43583175ejc.441.1666876816928; Thu, 27 Oct 2022 06:20:16 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666876816; cv=pass; d=google.com; s=arc-20160816; b=yIafUdIz5Gi17bUVpDGKOE59+W5/thCotvgtrEIX24xM4rUYwacaFHVmX6PRb2w1pE rni9rqkpy3LMlBoLuJCQneGRFqhEZkSwLF0/EhL4SYxhhoTRGwn+YE8tB0xs+uN1udRS NBAAwAjH1KC1kqWD/PIXN2x/t3O5q1oX5Ip/aaS2u1mi6L9pPVs/NrD8C+Niy0PiTuSZ boW9tO0IPKOmFtz4nmfEpNBHZWcVkO/MMlL40dEzAduAeNoqid4oIgZt0vAEn5/rA6cR 4qjuAF3AIohRjcK1Zg73+rDE9P5PwXXK67RszNdllygZURBKYV5a3JCXrrATIIAxTGis p0tQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ccpkmu4RpDemxBVUE3oS9vV8awijWMsffBawrv3GSqA=; b=abATbOgdk3hhHm/Xv6VGW4+dBINgruGnolKUfJpF3FuXnmiXO/bbdU3t3htUA5oskV Omug+1KnmZuMKsLAnjAlZr0k4s6x483GBXLL6Pnf0mhRcaDMetJ7fO0T+j2/QFfkN1lK lzqNP8Zi1/ONKAUSJapwkm/EnEy/StBZK1QdITBi/fNnICYVHS0XcrOTeFTpxexDG8p2 q28l+ciSseD434R5aAdUs+X/o0l3eMenBCfMaVxmKmc9G6aqWtWbeoS8JJELN6ss65wc pWz/5fL3chpL/6wDiMqvofarT7ZsjQSb99Rn7lwe1HcdCTazyEZidA05iDIqZFbOYBWK mj4w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=ZykI1cWM; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Shenwei Wang Reviewed-by: Peng Fan Reviewed-by: Linus Walleij --- .../boot/dts/freescale/imx8qm-ss-lsio.dtsi | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi index 669aa14ce9f7..b483134f84d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -6,30 +6,68 @@ &lsio_gpio0 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 0 6>, + <&iomuxc 6 7 22>, + <&iomuxc 28 36 4>; }; &lsio_gpio1 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 40 4>, + <&iomuxc 4 50 12>, + <&iomuxc 16 63 8>, + <&iomuxc 24 72 8>; }; &lsio_gpio2 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 80 4>, + <&iomuxc 4 85 18>, + <&iomuxc 22 104 10>; }; &lsio_gpio3 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 114 2>, + <&iomuxc 2 117 16>, + <&iomuxc 18 141 1>, + <&iomuxc 19 140 1>, + <&iomuxc 20 139 1>, + <&iomuxc 21 138 1>, + <&iomuxc 22 137 1>, + <&iomuxc 23 136 1>, + <&iomuxc 24 135 1>, + <&iomuxc 25 134 1>, + <&iomuxc 26 142 3>, + <&iomuxc 29 146 3>; }; &lsio_gpio4 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 149 3>, + <&iomuxc 3 153 4>, + <&iomuxc 7 158 6>, + <&iomuxc 13 165 6>, + <&iomuxc 19 172 8>, + <&iomuxc 27 198 5>; }; &lsio_gpio5 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 203 1>, + <&iomuxc 1 205 2>, + <&iomuxc 3 210 11>, + <&iomuxc 14 223 3>, + <&iomuxc 17 227 2>, + <&iomuxc 19 230 5>, + <&iomuxc 24 236 6>, + <&iomuxc 30 243 2>; }; &lsio_gpio6 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 245 10>, + <&iomuxc 10 256 12>; }; &lsio_gpio7 { From patchwork Thu Oct 27 13:08:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 11790 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp226858wru; Thu, 27 Oct 2022 06:20:17 -0700 (PDT) X-Google-Smtp-Source: AMsMyM75Ijr3JXnch48y1967rmFPCzcZkLADAyy/kTe0X191k/ObZq/QWfEHfMeUhR3Nf5saJrc2 X-Received: by 2002:a17:906:9746:b0:798:baec:3a80 with SMTP id o6-20020a170906974600b00798baec3a80mr31793376ejy.610.1666876817699; Thu, 27 Oct 2022 06:20:17 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666876817; cv=pass; d=google.com; s=arc-20160816; b=QaxXhVYbyNUf4NW0uD+NUIl6372tlnVPD9r5hrLHYieJjuZlC1Ug49kbDAH2JILCcv Gdim2bhxWFSY/18bjqHj0EqgX+rh/dexq+O8UwODghLWH0NGbpyk9FccJ2jOBJXFg//F 4XqoDRLYezQdvX8vS9Az4cxP0o+/cnkq7EXuLa2m8oPVsoRjfRsnOorzXTqfNOR7hGsz l6TcLatbUoNt6ZtCTCkUVcyPMe1+SH0iK/GLxtjNWcPyG0WDH9QLnJ3fRkiCzt+U5Kqa EpICIZMp5xnAXHxvnsMHQxoPEldALoW9Dr1vjFJLeKJwhRVWHjCk8MvYSBBGvCCZmAgi 7hpA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pt6pEJ4tFgXysBoOilvGa8i9zK5mFNHm3eCr37GOGd0=; b=IIzP04aHNoLCTYyQp8ufYdX15+rauUT5iTyHG1GcGGSdXofcoNG7JwBtS8X7NKvoUt dBE0GlNMieH5eJY2zmTn1bFLtgakE+cvsowUpZ6U49Fahj7ZVVlm3Rp+vR7TOQMxcvfq KW0Yms1k9vitsDE5yOYo24wkXBJTQZdE5QRrjQy1RlsSzDnWSBbqXH15VCRrsvgKGAwF IjqzOwNXCi8opiVvV2HRX2Uc88+6iL12s48BHnaU9DC4rzTEsh1vZGeMiGKGOiegqNzZ L3VKByVsNNkkwz7R532ptsts6TRzlZmrBcE4PHe0TznIJJ+Imb8uIMOyc29Vt27JRSGv s0Iw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=jxt6nXc7; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Shenwei Wang Reviewed-by: Peng Fan Reviewed-by: Linus Walleij --- .../boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index 8e2152c6eb88..8f722b1dd078 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -6,26 +6,51 @@ &lsio_gpio0 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 1 56 12>, + <&iomuxc 13 69 4>, + <&iomuxc 19 75 4>, + <&iomuxc 24 80 1>, + <&iomuxc 25 82 7>; }; &lsio_gpio1 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 89 9>, + <&iomuxc 9 99 16>, + <&iomuxc 25 116 7>; }; &lsio_gpio2 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 123 1>, + <&iomuxc 1 126 2>, + <&iomuxc 3 129 1>; }; &lsio_gpio3 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 146 4>, + <&iomuxc 4 151 13>, + <&iomuxc 17 165 8>; }; &lsio_gpio4 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 7 9 6>, + <&iomuxc 13 16 6>, + <&iomuxc 19 23 2>, + <&iomuxc 21 26 2>, + <&iomuxc 23 30 6>, + <&iomuxc 29 37 3>; }; &lsio_gpio5 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 40 3>, + <&iomuxc 3 44 6>, + <&iomuxc 9 51 3>; }; &lsio_gpio6 { From patchwork Thu Oct 27 13:08:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 11792 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp227328wru; Thu, 27 Oct 2022 06:21:08 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6Q4+EpPLmLOdf3xgmUpLNq3nJ56gd8aWbWdOAscY8PTqaPB/YcVbYFGvzdoWFp8HNDwsGk X-Received: by 2002:a17:906:730f:b0:791:9b75:2ca1 with SMTP id di15-20020a170906730f00b007919b752ca1mr40365184ejc.140.1666876868266; Thu, 27 Oct 2022 06:21:08 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666876868; cv=pass; d=google.com; s=arc-20160816; b=XKmvoO5hqoRSrzMAbahLBz9tbs4afgsMb8DJUbQdlWoAw5GGCKPNtEFz9xNYC7/a/9 5efKkMB6TsOyRB0HstLCa3zgy+P/gKppG1DPefy+4FWk5PW8dDpojUvgQDvj1EhuRhVO 6dlzeu21KQ8iQukY54CCoUBDwRgTtI8Ur5xzgTCQk+VSWSjZxH0h0y+qR2AMlI8Q8HNG 6vDOk5Vw121uajN2EUFfe0MdKAXwO0fO3hpl0TEJlSNvCMa4vGCXsq5fzANph3K8yBsj 6sGCmr53mm1UxFNwF0K6f+27qCMiuumqb7+EOdZiPle9fNNePAonzoU034p7wEekRaMZ rX2Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Zx7rvzpGKveheuABrjJhPyG94a0owwancSk7/48YbcE=; b=VhKtJ3UpaxYDBcsNmQ8GPFnExXFDbqUcQmNrCZFvaB6WaAkcsUePDpFwfBSC7m2wUB 8JgIKFHCNbMA5g/znGuHVsTklWLcLq5ebCfJ/pT1UW5PG70HnUwg84XgRgj4z+0X5HEY HXKc3cBVuUrreeSaExmMuOjnOsZvMBeGJIHuVTyjjwM1I4hc56ZcaA4M9UcrEpUn1r6W eYo59kxrJwxxZtW2C/Dd+5CrjQ1SCRVcpJ2JU+zicWEDGuQm8NWKct9OCbT9rkGUjvkJ E9uTDUOLhqg5P7SsHsc5L1O2sh2rzwwD00AhBj+gqPZHi946q6C7GLMR52TDHz5gQ3Xv uEuA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=BHPE+tVw; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Shenwei Wang Reported-by: kernel test robot Reviewed-by: Peng Fan --- drivers/pinctrl/freescale/pinctrl-scu.c | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c index 59b5f8a35111..ea261b6e7458 100644 --- a/drivers/pinctrl/freescale/pinctrl-scu.c +++ b/drivers/pinctrl/freescale/pinctrl-scu.c @@ -15,6 +15,11 @@ #include "../core.h" #include "pinctrl-imx.h" +#define IMX_SC_PAD_FUNC_GET_WAKEUP 9 +#define IMX_SC_PAD_FUNC_SET_WAKEUP 4 +#define IMX_SC_IRQ_GROUP_WAKE 3 /* Wakeup interrupts */ +#define IMX_SC_IRQ_PAD 2 /* Pad wakeup */ + enum pad_func_e { IMX_SC_PAD_FUNC_SET = 15, IMX_SC_PAD_FUNC_GET = 16, @@ -36,10 +41,18 @@ struct imx_sc_msg_resp_pad_get { u32 val; } __packed; +struct imx_sc_msg_gpio_set_pad_wakeup { + struct imx_sc_rpc_msg hdr; + u16 pad; + u8 wakeup; +} __packed __aligned(4); + static struct imx_sc_ipc *pinctrl_ipc_handle; int imx_pinctrl_sc_ipc_init(struct platform_device *pdev) { + imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_WAKE, + IMX_SC_IRQ_PAD, true); return imx_scu_get_handle(&pinctrl_ipc_handle); } EXPORT_SYMBOL_GPL(imx_pinctrl_sc_ipc_init); @@ -81,6 +94,23 @@ int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned int val; int ret; + if (num_configs == 1) { + struct imx_sc_msg_gpio_set_pad_wakeup wmsg; + + hdr = &wmsg.hdr; + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_PAD; + hdr->func = IMX_SC_PAD_FUNC_SET_WAKEUP; + hdr->size = 2; + wmsg.pad = pin_id; + wmsg.wakeup = *configs; + ret = imx_scu_call_rpc(pinctrl_ipc_handle, &wmsg, true); + + dev_dbg(ipctl->dev, "wakeup pin_id: %d type: %ld\n", + pin_id, *configs); + return ret; + } + /* * Set mux and conf together in one IPC call */ From patchwork Thu Oct 27 13:08:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 11795 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp228451wru; Thu, 27 Oct 2022 06:23:22 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5A6QgdRD+gBviiewCMbAXCXQnLOkphk4c69gPeQ1oNakWvOCGYbCr5caTOZgMYBz7pxy1o X-Received: by 2002:a17:907:d10:b0:79a:a1fe:8be5 with SMTP id gn16-20020a1709070d1000b0079aa1fe8be5mr29001581ejc.125.1666877002672; Thu, 27 Oct 2022 06:23:22 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666877002; cv=pass; d=google.com; s=arc-20160816; b=zOkrpGq5oz6/AGmC0kMlfo2LUVbD/c0IX117nVdU/nJke0INQZJ2M9jMUkG05niFVJ JcTWajC4Swt8az3Ce/86Iy+jkZ79Q8crWDHR/kTD18NsutTWKUiUiq917Sb65MU20JjY 9Ylhe1fS5YpppYJktWtfPG3Z0qnl7upf2PejH+wcJgDYLUUpIwdgCYIzhIePFsM+26IP f2hbJ3RQXQX5yqRa6lFoU3EQpFglfRlhylSllGWdGMZQdZn0P7LdfMuIUga9LUeG0iy2 lF9sl9IIyGwunSkQtlmjYGbIp7/FoFEJUwKkfSk3E5zzNwg+UiBWshlI0ckuVqgCbS+2 /k8g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RQZfuvJnXI/eFijRUp7QGqWSIetSaEZLmeIl9T5qHUQ=; b=FG44smP8PtHF7Pw1+4XGUNqeWVIBR8Rp5zNaJOba5oPKe5+xmWqTV1I6/o5hB19AkU C1Q9Hw01U4I6PFDZ0dln0MET9KWtE6QP1S/5gsjPVIPaJKCrqxrwxwS48MVRMHhd5PdT hTgWt9kMaSWa2CLodvT9PZDMr0//ACwKatlGe+vdL3a3U45cDNkR0H+ILjV9hn3rUrdP aSQpNWVi8ekzMJsYr5oMaI2sdfQiVoo2iRx3c/6XkasGC5vGMPNsV2sGxdigL7/5RKSK H/A3YPUdEkZDKaMeMfV+BsbBypZ7F5zPra68zZQu895FO0J1rRJM3kUeVlBuwPe0NjHW /5Og== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=Zwsu+sAg; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Received: from PAXPR04MB9185.eurprd04.prod.outlook.com (2603:10a6:102:231::11) by AM7PR04MB6807.eurprd04.prod.outlook.com (2603:10a6:20b:104::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.21; Thu, 27 Oct 2022 13:10:18 +0000 Received: from PAXPR04MB9185.eurprd04.prod.outlook.com ([fe80::b1ab:dd4f:9237:d9f8]) by PAXPR04MB9185.eurprd04.prod.outlook.com ([fe80::b1ab:dd4f:9237:d9f8%3]) with mapi id 15.20.5769.014; Thu, 27 Oct 2022 13:10:18 +0000 From: Shenwei Wang To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Linus Walleij , Bartosz Golaszewski , Dong Aisheng , Jacky Bai Cc: Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Shenwei Wang , Peng Fan , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v4 5/5] gpio: mxc: enable pad wakeup on i.MX8x platforms Date: Thu, 27 Oct 2022 08:08:59 -0500 Message-Id: <20221027130859.1444412-6-shenwei.wang@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027130859.1444412-1-shenwei.wang@nxp.com> References: <20221027130859.1444412-1-shenwei.wang@nxp.com> X-ClientProxiedBy: SJ0PR05CA0044.namprd05.prod.outlook.com (2603:10b6:a03:33f::19) To PAXPR04MB9185.eurprd04.prod.outlook.com (2603:10a6:102:231::11) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9185:EE_|AM7PR04MB6807:EE_ X-MS-Office365-Filtering-Correlation-Id: bbe4d484-b5b5-4daf-9c43-08dab81c980e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This can greatly reduce the power consumption of suspend state because the whole partition can be shutdown. This is called PAD wakeup feature on i.MX8x platform. This patch adds the noirq suspend/resume hooks and uses the pad wakeup feature as the default wakeup method for GPIO modules on i.MX8QM/QXP/DXL platforms. Signed-off-by: Shenwei Wang Reviewed-by: Peng Fan Acked-by: Bartosz Golaszewski --- drivers/gpio/gpio-mxc.c | 92 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index c871602fc5ba..d5626c572d24 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -24,6 +24,12 @@ #include #include +#define IMX_SCU_WAKEUP_OFF 0 +#define IMX_SCU_WAKEUP_LOW_LVL 4 +#define IMX_SCU_WAKEUP_FALL_EDGE 5 +#define IMX_SCU_WAKEUP_RISE_EDGE 6 +#define IMX_SCU_WAKEUP_HIGH_LVL 7 + /* device type dependent stuff */ struct mxc_gpio_hwdata { unsigned dr_reg; @@ -61,6 +67,9 @@ struct mxc_gpio_port { u32 both_edges; struct mxc_gpio_reg_saved gpio_saved_reg; bool power_off; + u32 wakeup_pads; + bool is_pad_wakeup; + u32 pad_type[32]; const struct mxc_gpio_hwdata *hwdata; }; @@ -130,6 +139,9 @@ static const struct of_device_id mxc_gpio_dt_ids[] = { { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata }, { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata }, { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); @@ -203,6 +215,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) } writel(1 << gpio_idx, port->base + GPIO_ISR); + port->pad_type[gpio_idx] = type; return 0; } @@ -254,6 +267,9 @@ static void mx3_gpio_irq_handler(struct irq_desc *desc) struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); + if (port->is_pad_wakeup) + return; + chained_irq_enter(chip, desc); irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); @@ -306,11 +322,13 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable) ret = enable_irq_wake(port->irq_high); else ret = enable_irq_wake(port->irq); + port->wakeup_pads |= (1 << gpio_idx); } else { if (port->irq_high && (gpio_idx >= 16)) ret = disable_irq_wake(port->irq_high); else ret = disable_irq_wake(port->irq); + port->wakeup_pads &= ~(1 << gpio_idx); } return ret; @@ -365,7 +383,6 @@ static int mxc_gpio_probe(struct platform_device *pdev) return -ENOMEM; port->dev = &pdev->dev; - port->hwdata = device_get_match_data(&pdev->dev); port->base = devm_platform_ioremap_resource(pdev, 0); @@ -498,6 +515,78 @@ static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); } +static bool mxc_gpio_generic_config(struct mxc_gpio_port *port, + unsigned int offset, unsigned long conf) +{ + struct device_node *np = port->dev->of_node; + + if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") || + of_device_is_compatible(np, "fsl,imx8qxp-gpio") || + of_device_is_compatible(np, "fsl,imx8qm-gpio")) + return (gpiochip_generic_config(&port->gc, offset, conf) == 0); + + return false; +} + +static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable) +{ + unsigned long config; + bool ret = false; + int i, type; + + static const u32 pad_type_map[] = { + IMX_SCU_WAKEUP_OFF, /* 0 */ + IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */ + IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */ + IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */ + IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */ + IMX_SCU_WAKEUP_OFF, /* 5 */ + IMX_SCU_WAKEUP_OFF, /* 6 */ + IMX_SCU_WAKEUP_OFF, /* 7 */ + IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */ + }; + + for (i = 0; i < 32; i++) { + if ((port->wakeup_pads & (1 << i))) { + type = port->pad_type[i]; + if (enable) + config = pad_type_map[type]; + else + config = IMX_SCU_WAKEUP_OFF; + ret |= mxc_gpio_generic_config(port, i, config); + } + } + + return ret; +} + +static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + if (port->wakeup_pads > 0) + port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true); + + return 0; +} + +static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + if (port->wakeup_pads > 0) + mxc_gpio_set_pad_wakeup(port, false); + port->is_pad_wakeup = false; + + return 0; +} + +static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume) +}; + static int mxc_gpio_syscore_suspend(void) { struct mxc_gpio_port *port; @@ -537,6 +626,7 @@ static struct platform_driver mxc_gpio_driver = { .name = "gpio-mxc", .of_match_table = mxc_gpio_dt_ids, .suppress_bind_attrs = true, + .pm = &mxc_gpio_dev_pm_ops, }, .probe = mxc_gpio_probe, };