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Tue, 13 Jun 2023 09:12:35 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , , Yazen Ghannam Subject: [PATCH 1/3] x86/MCE/AMD: Split amd_mce_is_memory_error() Date: Tue, 13 Jun 2023 09:11:40 -0500 Message-ID: <20230613141142.36801-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230613141142.36801-1-yazen.ghannam@amd.com> References: <20230613141142.36801-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD2:EE_|SA1PR12MB8742:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c1c540b-b785-49ae-0ac5-08db6c183e3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Dr0S08dREXQY6IH/iGxYLQRP7J0EctZHi7egOw8Qvvs25ZaH3nCXRl7Uk7+BQ/oYRYlm5lr1M0IWR7bFpXrmkRPyO4i5m9NvtiqbXa+XcueQKfeW/tO+xiRIJtmZ6dJvsm1/fpVaxpwzLBH9h2i0Mv1Km9uh5eb9mjLBETqTVU39Rdbop+Bb824asYc7xp6vLH3Y7z/QqaQM45jeGLKGkyib/uEWcYrF2/3e/0NQbqB12bM7dXyfBzenyYjQVBeOghzLfWeuUpQqxgz8PFpSuzp5a1d8SmHeMMw7mYken5S5/MMxFdjq3UzJll+Hlyzpdt5yUYFSmb+y6HD0SiYEGaJB1VoJ/DX/Ch6M0z7b+LdNGJkn+JGXE+KXzoX1PukZDTS0qUrtRyhkATYpjKD+pi05Ec0THmT8iBefMR6hs+6c9DopedIEiCAlBy+V36d42mU/kUysfkGysK2o9NoL2vcTvWOj1ylyxlYFuiU+HqrCf/YSMJB23b7zQtY9UoORvVqJlB9zq9S0H8FeZY/0yu7yM80K4ZeyNVIUYLwlj+njKPTdf6vcWP9fKfFc6aBQ8s5ROQqew+HnJ3V/6/qasQ8MSu5xWtq1eRuy5sRNMJ5qfuok/klUfxvlJWJghdFCwyGVhCZECe38oKbX/0W8dtJCFdR1h6hELNCWz9pfyzNZ51yXinfi+cR5gK2sHlnc5QAAIquW8aQmHBqfn0fKrS1DTlos9KDmaEYYqvFQGdByNX8Caizz56OT6gFtdittoRQI+FuzjTlHyVqCjiZTLQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(39860400002)(346002)(396003)(376002)(451199021)(36840700001)(40470700004)(46966006)(41300700001)(7696005)(6666004)(81166007)(356005)(70586007)(82740400003)(70206006)(2906002)(8936002)(36756003)(8676002)(5660300002)(54906003)(44832011)(6916009)(316002)(86362001)(40480700001)(4326008)(478600001)(40460700003)(336012)(426003)(2616005)(1076003)(16526019)(26005)(186003)(82310400005)(47076005)(83380400001)(36860700001)(36900700001);DIR:OUT;SFP:1101; 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Describe what each function is checking for, and correct the XEC bitmask for SMCA. No functional change intended. Signed-off-by: Yazen Ghannam Reviewed-by: Shuai Xue --- arch/x86/kernel/cpu/mce/amd.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 5e74610b39e7..1ccfb0c9257f 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -713,17 +713,37 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) deferred_error_interrupt_enable(c); } -bool amd_mce_is_memory_error(struct mce *m) +/* + * DRAM ECC errors are reported in the Northbridge (bank 4) with + * Extended Error Code 8. + */ +static bool legacy_mce_is_memory_error(struct mce *m) +{ + return m->bank == 4 && XEC(m->status, 0x1f) == 8; +} + +/* + * DRAM ECC errors are reported in Unified Memory Controllers with + * Extended Error Code 0. + */ +static bool smca_mce_is_memory_error(struct mce *m) { enum smca_bank_types bank_type; - /* ErrCodeExt[20:16] */ - u8 xec = (m->status >> 16) & 0x1f; + + if (XEC(m->status, 0x3f)) + return false; bank_type = smca_get_bank_type(m->extcpu, m->bank); + + return bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2; +} + +bool amd_mce_is_memory_error(struct mce *m) +{ if (mce_flags.smca) - return (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2) && xec == 0x0; + return smca_mce_is_memory_error(m); - return m->bank == 4 && xec == 0x8; + return legacy_mce_is_memory_error(m); } static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) From patchwork Tue Jun 13 14:11:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 107423 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp592966vqr; Tue, 13 Jun 2023 07:35:06 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7SiIJkzLn2fwLw+IyUKcbBI2xCc1jXTdw7EEIJHZ7q0l2LiIyqWrEWcP+4KbIKsNaI2Hp5 X-Received: by 2002:a17:907:320c:b0:976:8fdd:9046 with SMTP id xg12-20020a170907320c00b009768fdd9046mr11925444ejb.12.1686666906521; Tue, 13 Jun 2023 07:35:06 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1686666906; cv=pass; d=google.com; s=arc-20160816; b=Fp4LTRqNr/eIMzLrF+8gJKaKMZUrwvh7n8O3oLyvcKVN0WEn4n5UP2+EortiG0vkq+ 5sDO8cGzLbv1JbnuexeIaR9bZspRZAU+Oxp5X1b2Y+0AAiqTaafqp0QMIMB2n9jBHJaA CdPcS9gppaCwaMF3+jK3cqLlQh1v7s6S5WXcz/Hh9KD9xBS7v2evou0FM/ZqCKMD4NHS pf2Rm33BJa05I/2DcqzogALd4xDSCZXUwFElTGh8hkdXIcBqfqnsxNVOX8Inaff4IKvl S0HocJbvdddXYQuSEkJKkCiLVWDdcapVXm3/eXvCmNKyQX+smjZTqDxL7QT8SXMvHYu/ ZIog== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ojQqC0qddD8G5FXTR5qks1DdG7zqIt43NUW5+yr0/Mw=; b=PFYlNYH0/CtMzvLMIk6+0WD4uZ+RE+uY/YWouL8hxdkRW4V9DWaFB1YzxGi7aoI/lW sN8P75o674J9CX87aBiRVdb/cmZVtj2brBmKtSyLpUpuCmpVzO1GWd48us/KDHPd2Jer XQK5NNBSBmzuKgK+Uh2MMOqBPughYnqd0fIOWxXIkkkMiiFu6WDuMCwupCC/q9wfMCUK IFkevWA8lfPrWqlJpQSI/pU/n2G8YjZikRZe4gvMogju4tf05a210eL5cxEeux5J/EyX yBXnbhMX3jf0+H5NbOFRppgmeo7Ft7UaRNjjLQydYt2TvYwk1Pmy6ZFfdqYb22RM+Fjn 10Rg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=qgYGQNWe; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 13 Jun 2023 09:12:36 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , , Yazen Ghannam Subject: [PATCH 2/3] x86/mce: Define amd_mce_usable_address() Date: Tue, 13 Jun 2023 09:11:41 -0500 Message-ID: <20230613141142.36801-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230613141142.36801-1-yazen.ghannam@amd.com> References: <20230613141142.36801-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD2:EE_|PH7PR12MB8156:EE_ X-MS-Office365-Filtering-Correlation-Id: d4097d72-9aac-47d9-b85b-08db6c183e8a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fYpa3JzSgr4HAOSTtVq44TNA5cNBwje1LLqM/uvhe/jBPBA2Pxc4IMcToM/U3LsVdRjlXqLSV9x1QeC8j6+Qu059bAS9on4cAWyj7SVR2xKj7EehmBqRVxvdYKofEwDASXklHivZ94mNIinbpTK8Tv44gyK7WMQEunNW8yfak1JxB/JvEu+U+1Z/cAy4VHjHH5jBhSXevHed0dU7JYzfzgp7Ww0+MWavPu1/auD18LXnIGTINTU9iRuGNkXsDTOKzT7r4JhYxVpw3N6o2ggEiSSWr2huqyEiuqhaCwZ88QvNVq5uqzw8YoDrTBhOoopUAnIe+KjmTptC9O30U8BRI2DUfSsauoxJCzjO+a4T4k3aOKvGhmS+Di/VYcnWiYSUA1ozIzY+NaJ5vrArSh/+4ioKnkiAruJMyT+YHLMhiEeh0/lMYn+8CbWP6tndFx5Ya8mkJYmixVdR4I0i72BAvv8GuLLg5pnrn1HsASxy2z+GRAnyJ8NDrXILDotAeEl556q7bG9Mbx6aworipHTkzBUImdKkQ+uWAmldgVLV+h3UFGR3tv8yY/ZkvDOFxxKPCeMU3gP19OZ7EO6AzXi8URq4Tr8EMepZIzwbgTDLlM1/rFPwn4zo+kg7gXws/2mdy97H805/EBqbAXpsdwQICESjvc3BOKgmDjVLUauAnwPb+QwOuH9MWu1EEz3bGF9k4eUCf0LS0cEz3msj7GEboMpdLRupp5hmyjr74X1XUXZ2oEJ6FGkYQyoP7VfUrsVHFqnHLhjVllZ/BrMl9oHdXQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199021)(46966006)(40470700004)(36840700001)(7696005)(316002)(40460700003)(41300700001)(336012)(83380400001)(426003)(86362001)(82310400005)(36860700001)(2616005)(186003)(26005)(1076003)(44832011)(47076005)(2906002)(16526019)(82740400003)(81166007)(40480700001)(356005)(5660300002)(36756003)(8936002)(8676002)(70206006)(70586007)(478600001)(54906003)(6666004)(4326008)(6916009)(36900700001);DIR:OUT;SFP:1101; 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However, this is not correct in most cases. Notifiers expecting usable addresses may then operate on inappropriate values. Define a helper function to do AMD-specific checks for a usable memory address. List out all known cases. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 38 ++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mce/core.c | 3 +++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 43 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 1ccfb0c9257f..ca79fa10b844 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -746,6 +746,44 @@ bool amd_mce_is_memory_error(struct mce *m) return legacy_mce_is_memory_error(m); } +/* + * AMD systems do not have an explicit indicator that the value in MCA_ADDR is + * a system physical address. Therefore individual cases need to be detected. + * Future cases and checks will be added as needed. + * + * 1) General case + * a) Assume address is not usable. + * 2) "Poison" errors + * a) Indicated by MCA_STATUS[43]: POISON. Defined for all banks except legacy + * Northbridge (bank 4). + * b) Refers to poison consumption in the Core. Does not include "no action", + * "action optional", or "deferred" error severities. + * c) Will include a usuable address so that immediate action can be taken. + * 3) Northbridge DRAM ECC errors + * a) Reported in legacy bank 4 with XEC 8. + * b) MCA_STATUS[43] is *not* defined as POISON in legacy bank 4. Therefore, + * this bit should not be checked. + * + * NOTE: SMCA UMC memory errors fall into case #1. + */ +bool amd_mce_usable_address(struct mce *m) +{ + /* Check special Northbridge case first. */ + if (!mce_flags.smca) { + if (legacy_mce_is_memory_error(m)) + return true; + else if (m->bank == 4) + return false; + } + + /* Check Poison bit for all other bank types. */ + if (m->status & MCI_STATUS_POISON) + return true; + + /* Assume address is not usable for all others. */ + return false; +} + static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) { struct mce m; diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 89e2aab5d34d..859ce20dd730 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -464,6 +464,9 @@ int mce_usable_address(struct mce *m) if (!(m->status & MCI_STATUS_ADDRV)) return 0; + if (m->cpuvendor == X86_VENDOR_AMD) + return amd_mce_usable_address(m); + /* Checks after this one are Intel/Zhaoxin-specific: */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index d2412ce2d312..0d4c5b83ed93 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -207,6 +207,7 @@ extern bool filter_mce(struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m); +bool amd_mce_usable_address(struct mce *m); /* * If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits @@ -234,6 +235,7 @@ static __always_inline void smca_extract_err_addr(struct mce *m) #else static inline bool amd_filter_mce(struct mce *m) { return false; } +static inline bool amd_mce_usable_address(struct mce *m) { return false; } static inline void smca_extract_err_addr(struct mce *m) { } #endif From patchwork Tue Jun 13 14:11:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 107425 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp593994vqr; Tue, 13 Jun 2023 07:36:41 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7y/ScKMZYxD5K4Z/P6bmBLxFZ3dvwN1kGq7FQSRHEDcXvqOBCrLRrpOq6/EmqQUlff09kn X-Received: by 2002:a17:903:22c6:b0:1b3:d4ed:8306 with SMTP id y6-20020a17090322c600b001b3d4ed8306mr5116191plg.19.1686667001293; Tue, 13 Jun 2023 07:36:41 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1686667001; cv=pass; d=google.com; s=arc-20160816; b=1ILng2iPNnnz6y3b6aPWn298QrbB7agkUSgBeu+bjAxSPHIFHzlh/QLOPw6uPqZf12 86oIgno7IbCMWNCNUmE4zLbe+rPXxQ+CIvuUVoY/EIt4f33Yb1YDgXBnXC4UBoahnR7o uXvCNGpQN5oEoEwOmhrtzwPsCNpdn9niNHA1GmRsrLmRvlgDV7q6OxI33SQgTwrTy96N spk+9/GwhIrTrief0tJ9n/vfmU9Eki6iE69chskZLRBzod5xRIT81nO8UG0ElVxvXA6T THLu4Ms8y6u37IUxCyGHcdHhKRzUxnors7fuYaKJT39c5ME/fPhkpoXswS9xJIEuYQPt QiMw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OknFUpUS6NV3oSK+Q5pt3OHk6ugygcYsNI6Yrx1Ldqc=; b=k1MDeNyfb307QDn+igDA/Ily31nY2EN4wPf7Uf20L3Uypqow76HFljUHpalxLUh9q2 tKB7maNhclshVbfoQnEWELWchH4JgHdYFdKd7YbLYK2RFyxVPGOpa4maLjaGyhR6GEqL 82yvYlyQj99J3KuOZrNy1ReD+GcB0p8FID8iNCC9JgtwQ5bGOt8bklSBBP9SJMI+X7Bs zUVcUYCkCDF3zTTkbg1Eux3q1mTfgEeO9laWqeFqiifa2VoVlEnAPsmWbrvUnyUUb1x9 YmPWH1c88QJkoJulbHEyPnCOV1gkdNhZ461qc0JIhpWPtGK/m9WEtvNlRWAltN/24Dvv qJwQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=oltlhZRw; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 13 Jun 2023 09:12:37 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , , Yazen Ghannam Subject: [PATCH 3/3] x86/mce: Fixup mce_usable_address() Date: Tue, 13 Jun 2023 09:11:42 -0500 Message-ID: <20230613141142.36801-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230613141142.36801-1-yazen.ghannam@amd.com> References: <20230613141142.36801-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD2:EE_|PH7PR12MB6657:EE_ X-MS-Office365-Filtering-Correlation-Id: eff67e79-7c29-47ca-82f6-08db6c183fb9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iWmorLm9h0RpcA3WaU66TsHRwsmipw1dHH3kL0jk9/Zmb64a9r2/IaH2HWyLEt+xLujDj2W0xB3ruSHhXw/bXslRW5BYM523AxSdxv2ZbcC/WhQ+jZWT+trXpEd/8kbUfGs98pIP0KtZ0KdlPzf19mhIKE8nTQ+6PofYkJzg0cp2SDj2sVzZ3+41MTZiUxy1nvJCwCk3CD8MQov9NLB19U8/QAuxlclCin1LoUDnQ7yqNm2UKk1RRiTdiFjrbebfO6MDi3TRCRxTa1M9etfHP4WHbxT3yqcjJVQAX9I0uVcH/QCDtpkkttI4WATSsWQAfTyHiKuLVMjn4p8mEZUlQ8z+h1/iKI4ev5Cwl/77+Vj6h3Exr85AJ1Mdg3G+3hNIlRhFPbjKm6gabQobctBu37H+1w6GyYLiREYGQWZoFT8KrptbUuSJIepoCqNfYPamyLu1YMMKN8vEA9HviafrIRzuJMtsya9lyQ+4pR0CxAcl9cDyKlclZ3xuCbmy+QBlQOc74GCmhIIwHsZKqmFeZsz3tMvWGGm4G1GKrqv5Sd01FDY8vtXsgyLswVGs8ENZ3VbwejeRb6sk9aoY38Fo1iRVSD5+EmEzjMz3MAnKsG/5Dk6Fd22XiPUPE5jI4TDscr+dw/R580n0xohL7A2T5z8gxorN927B63C6rXKyU0iQB1AGm02WJSP6HfSkf6235HOieQJeRV+Nkz79glSmBFed8bAvbSsiIHmUMDkz/3MuZswFMQ7T0j9SmEocXJzvxKeZCT/laW2JQdn0H186Tw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(39860400002)(396003)(376002)(136003)(451199021)(40470700004)(36840700001)(46966006)(8936002)(8676002)(44832011)(5660300002)(4326008)(70586007)(70206006)(6916009)(316002)(54906003)(2906002)(41300700001)(36860700001)(40460700003)(6666004)(478600001)(7696005)(356005)(81166007)(40480700001)(426003)(336012)(36756003)(186003)(16526019)(83380400001)(1076003)(47076005)(2616005)(26005)(82740400003)(86362001)(82310400005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2023 14:12:40.6100 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eff67e79-7c29-47ca-82f6-08db6c183fb9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6657 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768598537417894911?= X-GMAIL-MSGID: =?utf-8?q?1768598537417894911?= Move Intel-specific checks into a helper function. Explicitly use "bool" for return type. No functional change intended. Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 2 +- arch/x86/kernel/cpu/mce/core.c | 33 +++++++++--------------------- arch/x86/kernel/cpu/mce/intel.c | 20 ++++++++++++++++++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 4 files changed, 33 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 180b1cbfcc4e..6de6e1d95952 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -245,7 +245,7 @@ static inline void cmci_recheck(void) {} int mce_available(struct cpuinfo_x86 *c); bool mce_is_memory_error(struct mce *m); bool mce_is_correctable(struct mce *m); -int mce_usable_address(struct mce *m); +bool mce_usable_address(struct mce *m); DECLARE_PER_CPU(unsigned, mce_exception_count); DECLARE_PER_CPU(unsigned, mce_poll_count); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 859ce20dd730..c17e2b54853b 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -453,35 +453,22 @@ static void mce_irq_work_cb(struct irq_work *entry) mce_schedule_work(); } -/* - * Check if the address reported by the CPU is in a format we can parse. - * It would be possible to add code for most other cases, but all would - * be somewhat complicated (e.g. segment offset would require an instruction - * parser). So only support physical addresses up to page granularity for now. - */ -int mce_usable_address(struct mce *m) +bool mce_usable_address(struct mce *m) { if (!(m->status & MCI_STATUS_ADDRV)) - return 0; + return false; - if (m->cpuvendor == X86_VENDOR_AMD) + switch (m->cpuvendor) { + case X86_VENDOR_AMD: return amd_mce_usable_address(m); - /* Checks after this one are Intel/Zhaoxin-specific: */ - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && - boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) - return 1; - - if (!(m->status & MCI_STATUS_MISCV)) - return 0; - - if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) - return 0; - - if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) - return 0; + case X86_VENDOR_INTEL: + case X86_VENDOR_ZHAOXIN: + return intel_mce_usable_address(m); - return 1; + default: + return true; + } } EXPORT_SYMBOL_GPL(mce_usable_address); diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index 95275a5e57e0..56ecf128a534 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -519,3 +519,23 @@ bool intel_filter_mce(struct mce *m) return false; } + +/* + * Check if the address reported by the CPU is in a format we can parse. + * It would be possible to add code for most other cases, but all would + * be somewhat complicated (e.g. segment offset would require an instruction + * parser). So only support physical addresses up to page granularity for now. + */ +bool intel_mce_usable_address(struct mce *m) +{ + if (!(m->status & MCI_STATUS_MISCV)) + return false; + + if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) + return false; + + if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) + return false; + + return true; +} diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 0d4c5b83ed93..962b3134991d 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -49,6 +49,7 @@ void intel_init_cmci(void); void intel_init_lmce(void); void intel_clear_lmce(void); bool intel_filter_mce(struct mce *m); +bool intel_mce_usable_address(struct mce *m); #else # define cmci_intel_adjust_timer mce_adjust_timer_default static inline bool mce_intel_cmci_poll(void) { return false; } @@ -58,6 +59,7 @@ static inline void intel_init_cmci(void) { } static inline void intel_init_lmce(void) { } static inline void intel_clear_lmce(void) { } static inline bool intel_filter_mce(struct mce *m) { return false; } +static inline bool intel_mce_usable_address(struct mce *m) { return false; } #endif void mce_timer_kick(unsigned long interval);