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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ay1-20020a056402202100b00514b8d2b1e2si7267674edb.260.2023.06.13.06.40.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 06:40:17 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8DD7F3856DF4 for ; Tue, 13 Jun 2023 13:39:57 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTPS id 90EEB38582BD for ; Tue, 13 Jun 2023 13:39:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 90EEB38582BD Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-05 (Coremail) with SMTP id zQCowAA3kix7cYhkSPDkAQ--.2766S2; Tue, 13 Jun 2023 21:39:08 +0800 (CST) From: Jiawei To: binutils@sourceware.org Cc: nelson@rivosinc.com, kito.cheng@sifive.com, palmer@dabbelt.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, mary.bennett@embecosm.com, nandni.jamnadas@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, tariq.kurd@codasip.com, ibrahim.abu.kharmeh1@huawei.com, gaofei@eswincomputing.com, sinan.lin@linux.alibaba.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Jiawei Subject: [PATCH 1/2] RISC-V: Add Zcb extension supports. Date: Tue, 13 Jun 2023 21:38:50 +0800 Message-Id: <20230613133851.786238-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: zQCowAA3kix7cYhkSPDkAQ--.2766S2 X-Coremail-Antispam: 1UD129KBjvAXoWfCr4DCrWDAr1ktry8trW3trb_yoW8uF4fXo WxKr47Z3sxK3sakayF9F4fWayUAFyY9wn2vw4Fv392vF98AryUGr1fKw4jvryUKryIq3yU C397Wrn5GFZ3JF4Dn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUY-7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2 x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWx JVW8Jr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lc2xSY4AK67A8MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r 4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF 67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2I x0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2 z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvj DU0xZFpf9x0JUbeOJUUUUU= X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCgABAGSISY548QAAsp X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768594989268572286?= X-GMAIL-MSGID: =?utf-8?q?1768594989268572286?= This patch support instructions of zcb extension, some instructions depend on other extension, like `zbb` or `zmmul`. Co-Authored by: Charlie Keaney Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Sinan Lin Co-Authored by: Simon Cook Co-Authored by: Shihua Liao Co-Authored by: Yulong Shi bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. include/ChangeLog: * opcode/riscv-opc.h (MATCH_C_LBU): New opcode. (MASK_C_LBU): New mask. (MATCH_C_LHU): New opcode. (MASK_C_LHU): New mask. (MATCH_C_LH): New opcode. (MASK_C_LH): New mask. (MATCH_C_SB): New opcode. (MASK_C_SB): New mask. (MATCH_C_SH): New opcode. (MASK_C_SH): New mask. (MATCH_C_ZEXT_B): New opcode. (MASK_C_ZEXT_B): New mask. (MATCH_C_SEXT_B): New opcode. (MASK_C_SEXT_B): New mask. (MATCH_C_ZEXT_H): New opcode. (MASK_C_ZEXT_H): New mask. (MATCH_C_SEXT_H): New opcode. (MASK_C_SEXT_H): New mask. (MATCH_C_ZEXT_W): New opcode. (MASK_C_ZEXT_W): New mask. (MATCH_C_NOT): New opcode. (MASK_C_NOT): New mask. (MATCH_C_MUL): New opcode. (MASK_C_MUL): New mask. (DECLARE_INSN): New insn declare. * opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func. (EXTRACT_ZCB_HALFWORD_UIMM): Ditto. (ENCODE_ZCB_BYTE_UIMM): Ditto. (ENCODE_ZCB_HALFWORD_UIMM): Ditto. (VALID_ZCB_BYTE_UIMM): Ditto. (VALID_ZCB_HALFWORD_UIMM): Ditto. (enum riscv_insn_class): New extension class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New New operators. * riscv-opc.c: New instructions. --- bfd/elfxx-riscv.c | 19 +++++++++++ gas/config/tc-riscv.c | 65 ++++++++++++++++++++++++++++++++++++++ include/opcode/riscv-opc.h | 38 ++++++++++++++++++++++ include/opcode/riscv.h | 20 ++++++++++++ opcodes/riscv-dis.c | 14 ++++++++ opcodes/riscv-opc.c | 28 ++++++++++++++++ 6 files changed, 184 insertions(+) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 4a7407b8a34..60f1cfde047 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2431,6 +2431,17 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zve64d") || riscv_subset_supports (rps, "zve64f") || riscv_subset_supports (rps, "zve32f")); + case INSN_CLASS_ZCB: + return riscv_subset_supports (rps, "zcb"); + case INSN_CLASS_ZCB_AND_ZBB: + return riscv_subset_supports (rps, "zcb") + && riscv_subset_supports (rps, "zbb"); + case INSN_CLASS_ZCB_AND_ZBA: + return riscv_subset_supports (rps, "zcb") + && riscv_subset_supports (rps, "zba"); + case INSN_CLASS_ZCB_AND_ZMMUL: + return riscv_subset_supports (rps, "zcb") + && riscv_subset_supports (rps, "zmmul"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2591,6 +2602,14 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("v' or `zve64x' or `zve32x"); case INSN_CLASS_ZVEF: return _("v' or `zve64d' or `zve64f' or `zve32f"); + case INSN_CLASS_ZCB: + return "zcb"; + case INSN_CLASS_ZCB_AND_ZBA: + return _("zcb' and `zba"); + case INSN_CLASS_ZCB_AND_ZBB: + return _("zcb' and `zbb"); + case INSN_CLASS_ZCB_AND_ZMMUL: + return _("zcb' and `zmmul', or `zcb' and `m"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 1d3860b332f..436936a6fac 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1304,6 +1304,17 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) goto unknown_validate_operand; } break; + case 'Z': /* Zcb extension operators. */ + switch (*++oparg) + { + /* byte immediate operators, load/store byte insns. */ + case 'h': used_bits |= ENCODE_ZCB_HALFWORD_UIMM (-1U); break; + /* halfword immediate operators, load/store halfword insns. */ + case 'b': used_bits |= ENCODE_ZCB_BYTE_UIMM (-1U); break; + default: + goto unknown_validate_operand; + } + break; default: goto unknown_validate_operand; } @@ -1406,6 +1417,14 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) goto unknown_validate_operand; } break; + case 'n': /* Zcb extension. */ + switch (*++oparg) + { + case 'f': break; + default: + goto unknown_validate_operand; + } + break; case 'X': /* Integer immediate. */ { size_t n; @@ -2911,7 +2930,35 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, goto unknown_riscv_ip_operand; } break; + case 'Z': /* Zcb extension. */ + switch (*++oparg) + { + case 'h': /* immediate field for c.lh/c.lhu/c.sh. */ + /* handle cases, such as c.sh rs2', (rs1') */ + if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) + continue; + if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) + || imm_expr->X_op != O_constant + || !VALID_ZCB_HALFWORD_UIMM ((valueT) imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_ZCB_HALFWORD_UIMM (imm_expr->X_add_number); + goto rvc_imm_done; + + case 'b': /* immediate field for c.lbu/c.sb. */ + /* handle cases, such as c.lbu rd', (rs1') */ + if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) + continue; + if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) + || imm_expr->X_op != O_constant + || !VALID_ZCB_BYTE_UIMM ((valueT) imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_ZCB_BYTE_UIMM (imm_expr->X_add_number); + goto rvc_imm_done; + default: + goto unknown_riscv_ip_operand; + } + break; default: goto unknown_riscv_ip_operand; } @@ -3499,6 +3546,24 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, } break; + case 'n': + switch (*++oparg) + { + case 'f': /* operand for matching immediate 255. */ + if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) + || imm_expr->X_op != O_constant + || imm_expr->X_add_number != 255) + break; + /* this operand is used for matching immediate 255, and + we do not write anything to encoding by this operand. */ + asarg = expr_end; + imm_expr->X_op = O_absent; + continue; + default: + goto unknown_riscv_ip_operand; + } + break; + case 'X': /* Integer immediate. */ { size_t n; diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 91e56c03191..14f3b3829f0 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2055,6 +2055,31 @@ #define MASK_VDOTUVV 0xfc00707f #define MATCH_VFDOTVV 0xe4001057 #define MASK_VFDOTVV 0xfc00707f +/* Zcb instructions. */ +#define MATCH_C_LBU 0x8000 +#define MASK_C_LBU 0xfc03 +#define MATCH_C_LHU 0x8400 +#define MASK_C_LHU 0xfc43 +#define MATCH_C_LH 0x8440 +#define MASK_C_LH 0xfc43 +#define MATCH_C_SB 0x8800 +#define MASK_C_SB 0xfc03 +#define MATCH_C_SH 0x8c00 +#define MASK_C_SH 0xfc43 +#define MATCH_C_ZEXT_B 0x9c61 +#define MASK_C_ZEXT_B 0xfc7f +#define MATCH_C_SEXT_B 0x9c65 +#define MASK_C_SEXT_B 0xfc7f +#define MATCH_C_ZEXT_H 0x9c69 +#define MASK_C_ZEXT_H 0xfc7f +#define MATCH_C_SEXT_H 0x9c6d +#define MASK_C_SEXT_H 0xfc7f +#define MATCH_C_ZEXT_W 0x9c71 +#define MASK_C_ZEXT_W 0xfc7f +#define MATCH_C_NOT 0x9c75 +#define MASK_C_NOT 0xfc7f +#define MATCH_C_MUL 0x9c41 +#define MASK_C_MUL 0xfc63 /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3123,6 +3148,19 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO); /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) +/* Zcb instructions. */ +DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B) +DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H) +DECLARE_INSN(c_zext_b, MATCH_C_ZEXT_B, MASK_C_ZEXT_B) +DECLARE_INSN(c_zext_h, MATCH_C_ZEXT_H, MASK_C_ZEXT_H) +DECLARE_INSN(c_zext_w, MATCH_C_ZEXT_W, MASK_C_ZEXT_W) +DECLARE_INSN(c_mul, MATCH_C_MUL, MASK_C_MUL) +DECLARE_INSN(c_not, MATCH_C_NOT, MASK_C_NOT) +DECLARE_INSN(c_lbu, MATCH_C_LBU, MASK_C_LBU) +DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) +DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) +DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) +DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 877ec66b957..f84d3d2ef3d 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -107,6 +107,12 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define EXTRACT_RVV_VC_IMM(x) \ (RV_X(x, 20, 11)) +/* Zcb extension. */ +#define EXTRACT_ZCB_BYTE_UIMM(x) \ + (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1)) +#define EXTRACT_ZCB_HALFWORD_UIMM(x) \ + (RV_X(x, 5, 1) << 1) + #define ENCODE_ITYPE_IMM(x) \ (RV_X(x, 0, 12) << 20) #define ENCODE_STYPE_IMM(x) \ @@ -152,6 +158,12 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define ENCODE_RVV_VC_IMM(x) \ (RV_X(x, 0, 11) << 20) +/* Zcb extenison. */ +#define ENCODE_ZCB_BYTE_UIMM(x) \ + ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5)) +#define ENCODE_ZCB_HALFWORD_UIMM(x) \ + (RV_X(x, 1, 1) << 5) + #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) #define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x)) @@ -177,6 +189,10 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x)) #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x)) +/* Zcb extension. */ +#define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x)) +#define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x)) + #define RISCV_RTYPE(insn, rd, rs1, rs2) \ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) #define RISCV_ITYPE(insn, rd, rs1, imm) \ @@ -409,6 +425,10 @@ enum riscv_insn_class INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, INSN_CLASS_ZICBOZ, + INSN_CLASS_ZCB, + INSN_CLASS_ZCB_AND_ZBA, + INSN_CLASS_ZCB_AND_ZBB, + INSN_CLASS_ZCB_AND_ZMMUL, INSN_CLASS_H, INSN_CLASS_XTHEADBA, INSN_CLASS_XTHEADBB, diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 108baeb32ef..a470a381986 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -329,6 +329,20 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info print (info->stream, dis_style_register, "%s", riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); break; + case 'Z': /* Zcb extension 16 bits length instruction fields. */ + switch (*++oparg) + { + case 'b': + print (info->stream, dis_style_immediate, "%d", + (int)EXTRACT_ZCB_BYTE_UIMM (l)); + break; + case 'h': + print (info->stream, dis_style_immediate, "%d", + (int)EXTRACT_ZCB_HALFWORD_UIMM (l)); + break; + default: break; + } + break; } break; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 57e7b90e480..861058812a7 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -359,12 +359,14 @@ const struct riscv_opcode riscv_opcodes[] = {"mv", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS }, {"move", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, {"move", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS }, +{"zext.b", 0, INSN_CLASS_ZCB, "Cs,Cw", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, INSN_ALIAS }, {"zext.b", 0, INSN_CLASS_I, "d,s", MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS }, {"and", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, {"and", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, {"and", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, {"and", 0, INSN_CLASS_I, "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 }, {"and", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS }, +{"andi", 0, INSN_CLASS_ZCB, "Cs,Cw,nf",MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, INSN_ALIAS }, {"andi", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, {"andi", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 }, {"beqz", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, @@ -428,16 +430,20 @@ const struct riscv_opcode riscv_opcodes[] = {"sub", 0, INSN_CLASS_I, "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 }, {"lb", 0, INSN_CLASS_I, "d,o(s)", MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE }, {"lb", 0, INSN_CLASS_I, "d,A", 0, (int) M_LB, match_never, INSN_MACRO }, +{"lbu", 0, INSN_CLASS_ZCB, "Ct,CZb(Cs)", MATCH_C_LBU, MASK_C_LBU, match_opcode, INSN_ALIAS|INSN_DREF|INSN_1_BYTE }, {"lbu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, INSN_DREF|INSN_1_BYTE }, {"lbu", 0, INSN_CLASS_I, "d,A", 0, (int) M_LBU, match_never, INSN_MACRO }, +{"lh", 0, INSN_CLASS_ZCB, "Ct,CZh(Cs)", MATCH_C_LH, MASK_C_LH, match_opcode, INSN_ALIAS|INSN_DREF|INSN_2_BYTE }, {"lh", 0, INSN_CLASS_I, "d,o(s)", MATCH_LH, MASK_LH, match_opcode, INSN_DREF|INSN_2_BYTE }, {"lh", 0, INSN_CLASS_I, "d,A", 0, (int) M_LH, match_never, INSN_MACRO }, +{"lhu", 0, INSN_CLASS_ZCB, "Ct,CZh(Cs)", MATCH_C_LHU, MASK_C_LHU, match_opcode, INSN_ALIAS|INSN_DREF|INSN_2_BYTE }, {"lhu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, INSN_DREF|INSN_2_BYTE }, {"lhu", 0, INSN_CLASS_I, "d,A", 0, (int) M_LHU, match_never, INSN_MACRO }, {"lw", 0, INSN_CLASS_C, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, +{"not", 0, INSN_CLASS_ZCB, "Cs,Cw", MATCH_C_NOT, MASK_C_NOT, match_opcode, INSN_ALIAS }, {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS }, {"or", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, @@ -457,8 +463,10 @@ const struct riscv_opcode riscv_opcodes[] = {"sltu", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS }, {"sgt", 0, INSN_CLASS_I, "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS }, {"sgtu", 0, INSN_CLASS_I, "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS }, +{"sb", 0, INSN_CLASS_ZCB, "Ct,CZb(Cs)", MATCH_C_SB, MASK_C_SB, match_opcode, INSN_DREF|INSN_1_BYTE|INSN_ALIAS }, {"sb", 0, INSN_CLASS_I, "t,q(s)", MATCH_SB, MASK_SB, match_opcode, INSN_DREF|INSN_1_BYTE }, {"sb", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO }, +{"sh", 0, INSN_CLASS_ZCB, "Ct,CZh(Cs)", MATCH_C_SH, MASK_C_SH, match_opcode, INSN_DREF|INSN_2_BYTE|INSN_ALIAS }, {"sh", 0, INSN_CLASS_I, "t,q(s)", MATCH_SH, MASK_SH, match_opcode, INSN_DREF|INSN_2_BYTE }, {"sh", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO }, {"sw", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, @@ -605,6 +613,7 @@ const struct riscv_opcode riscv_opcodes[] = {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, /* Multiply/Divide instruction subset. */ +{"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS }, {"mul", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, {"mulh", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, {"mulhu", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, @@ -948,10 +957,13 @@ const struct riscv_opcode riscv_opcodes[] = {"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 }, {"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 }, {"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 }, +{"sext.b", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_SEXT_B, MASK_C_SEXT_B, match_opcode, INSN_ALIAS }, {"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 }, {"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO }, +{"sext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_SEXT_H, MASK_C_SEXT_H, match_opcode, INSN_ALIAS }, {"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 }, {"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO }, +{"zext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_ZEXT_H, MASK_C_ZEXT_H, match_opcode, INSN_ALIAS }, {"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 }, {"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 }, {"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO }, @@ -987,6 +999,7 @@ const struct riscv_opcode riscv_opcodes[] = {"sh1add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 }, {"sh2add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 }, {"sh3add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 }, +{"zext.w", 64, INSN_CLASS_ZCB_AND_ZBA, "Cs,Cw", MATCH_C_ZEXT_W, MASK_C_ZEXT_W, match_opcode, INSN_ALIAS }, {"zext.w", 64, INSN_CLASS_ZBA, "d,s", MATCH_ADD_UW, MASK_ADD_UW | MASK_RS2, match_opcode, INSN_ALIAS }, {"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO }, {"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 }, @@ -1816,6 +1829,21 @@ const struct riscv_opcode riscv_opcodes[] = {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0}, {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0}, +/* ZCB instructions. */ +{"c.lbu", 0, INSN_CLASS_ZCB, "Ct,CZb(Cs)", MATCH_C_LBU, MASK_C_LBU, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"c.lhu", 0, INSN_CLASS_ZCB, "Ct,CZh(Cs)", MATCH_C_LHU, MASK_C_LHU, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"c.lh", 0, INSN_CLASS_ZCB, "Ct,CZh(Cs)", MATCH_C_LH, MASK_C_LH, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"c.sb", 0, INSN_CLASS_ZCB, "Ct,CZb(Cs)", MATCH_C_SB, MASK_C_SB, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"c.sh", 0, INSN_CLASS_ZCB, "Ct,CZh(Cs)", MATCH_C_SH, MASK_C_SH, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"c.not", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_NOT, MASK_C_NOT, match_opcode, 0 }, +{"c.mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, 0 }, +{"c.sext.b", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs", MATCH_C_SEXT_B, MASK_C_SEXT_B, match_opcode, 0 }, +{"c.sext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs", MATCH_C_SEXT_H, MASK_C_SEXT_H, match_opcode, 0 }, +{"c.zext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs", MATCH_C_ZEXT_H, MASK_C_ZEXT_H, match_opcode, 0 }, +{"c.zext.w", 64, INSN_CLASS_ZCB_AND_ZBA, "Cs", MATCH_C_ZEXT_W, MASK_C_ZEXT_W, match_opcode, 0 }, +{"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 }, +{"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, 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[8.43.85.97]) by mx.google.com with ESMTPS id s21-20020aa7cb15000000b00515e8effca6si4942451edt.386.2023.06.13.06.39.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 06:39:40 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A18733858404 for ; Tue, 13 Jun 2023 13:39:37 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTPS id 7088E3858D32 for ; Tue, 13 Jun 2023 13:39:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7088E3858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-05 (Coremail) with SMTP id zQCowAA3kix7cYhkSPDkAQ--.2766S3; Tue, 13 Jun 2023 21:39:11 +0800 (CST) From: Jiawei To: binutils@sourceware.org Cc: nelson@rivosinc.com, kito.cheng@sifive.com, palmer@dabbelt.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, mary.bennett@embecosm.com, nandni.jamnadas@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, tariq.kurd@codasip.com, ibrahim.abu.kharmeh1@huawei.com, gaofei@eswincomputing.com, sinan.lin@linux.alibaba.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Jiawei Subject: [PATCH 2/2] RISC-V: Add Zcb extension testcases. Date: Tue, 13 Jun 2023 21:38:51 +0800 Message-Id: <20230613133851.786238-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613133851.786238-1-jiawei@iscas.ac.cn> References: <20230613133851.786238-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowAA3kix7cYhkSPDkAQ--.2766S3 X-Coremail-Antispam: 1UD129KBjvAXoWDGw15KFyrtFW5Ar47ZFy3XFb_yoWruw18Go WxGF43uayrWF1akrnYvw45Jay2yFn7Cay3Xa98uayUAa18uw45ZwnIqws0934xGr1fXw1k WFZ5JFy8WFyUJwsrn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOO7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r18M28IrcIa0x kI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr 1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lc2xSY4AK67A8MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I 3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxV W8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8I cVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aV AFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZF pf9x0pRItCwUUUUU= X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCgQBAGSISY549QAAsp X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768594950490791077?= X-GMAIL-MSGID: =?utf-8?q?1768594950490791077?= Add all zcb instructions testcases. Fail testcases check missing depend extensions cases. Co-Authored by: Charlie Keaney Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Sinan Lin Co-Authored by: Simon Cook Co-Authored by: Shihua Liao Co-Authored by: Yulong Shi gas/ChangeLog: * testsuite/gas/riscv/zc-zcb-fail-arch-0.d: New test. * testsuite/gas/riscv/zc-zcb-fail-arch-0.l: New test. * testsuite/gas/riscv/zc-zcb-fail-arch-0.s: New test. * testsuite/gas/riscv/zc-zcb-fail-arch-1.d: New test. * testsuite/gas/riscv/zc-zcb-fail-arch-1.l: New test. * testsuite/gas/riscv/zc-zcb-fail-arch-1.s: New test. * testsuite/gas/riscv/zc-zcb-fail-operand-0.d: New test. * testsuite/gas/riscv/zc-zcb-fail-operand-0.l: New test. * testsuite/gas/riscv/zc-zcb-fail-operand-0.s: New test. * testsuite/gas/riscv/zc-zcb-fail-operand-1.d: New test. * testsuite/gas/riscv/zc-zcb-fail-operand-1.l: New test. * testsuite/gas/riscv/zc-zcb-fail-operand-1.s: New test. * testsuite/gas/riscv/zc-zcb-fail-xlen.d: New test. * testsuite/gas/riscv/zc-zcb-fail-xlen.l: New test. * testsuite/gas/riscv/zc-zcb-fail-xlen.s: New test. * testsuite/gas/riscv/zc-zcb-lbu.d: New test. * testsuite/gas/riscv/zc-zcb-lbu.s: New test. * testsuite/gas/riscv/zc-zcb-lh.d: New test. * testsuite/gas/riscv/zc-zcb-lh.s: New test. * testsuite/gas/riscv/zc-zcb-lhu.d: New test. * testsuite/gas/riscv/zc-zcb-lhu.s: New test. * testsuite/gas/riscv/zc-zcb-mul.d: New test. * testsuite/gas/riscv/zc-zcb-mul.s: New test. * testsuite/gas/riscv/zc-zcb-not.d: New test. * testsuite/gas/riscv/zc-zcb-not.s: New test. * testsuite/gas/riscv/zc-zcb-sb.d: New test. * testsuite/gas/riscv/zc-zcb-sb.s: New test. * testsuite/gas/riscv/zc-zcb-sext-b.s: New test. * testsuite/gas/riscv/zc-zcb-sext-h.s: New test. * testsuite/gas/riscv/zc-zcb-sextw.d: New test. * testsuite/gas/riscv/zc-zcb-sextw.s: New test. * testsuite/gas/riscv/zc-zcb-sh.d: New test. * testsuite/gas/riscv/zc-zcb-sh.s: New test. * testsuite/gas/riscv/zc-zcb-test-arch-gc.d: New test. * testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d: New test. * testsuite/gas/riscv/zc-zcb-test-arch.s: New test. * testsuite/gas/riscv/zc-zcb-test-operand-0.d: New test. * testsuite/gas/riscv/zc-zcb-test-operand-0.s: New test. * testsuite/gas/riscv/zc-zcb-test-operand-1.d: New test. * testsuite/gas/riscv/zc-zcb-test-operand-1.s: New test. * testsuite/gas/riscv/zc-zcb-test-operand-2.d: New test. * testsuite/gas/riscv/zc-zcb-test-operand-2.s: New test. * testsuite/gas/riscv/zc-zcb-zext-b.d: New test. * testsuite/gas/riscv/zc-zcb-zext-b.s: New test. * testsuite/gas/riscv/zc-zcb-zext-h.d: New test. * testsuite/gas/riscv/zc-zcb-zext-h.s: New test. * testsuite/gas/riscv/zc-zcb-zextw.d: New test. * testsuite/gas/riscv/zc-zcb-zextw.s: New test. --- gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.d | 3 ++ gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.l | 9 +++++ gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.s | 10 ++++++ gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.d | 3 ++ gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.l | 6 ++++ gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.s | 17 +++++++++ .../gas/riscv/zc-zcb-fail-operand-0.d | 3 ++ .../gas/riscv/zc-zcb-fail-operand-0.l | 13 +++++++ .../gas/riscv/zc-zcb-fail-operand-0.s | 17 +++++++++ .../gas/riscv/zc-zcb-fail-operand-1.d | 3 ++ .../gas/riscv/zc-zcb-fail-operand-1.l | 11 ++++++ .../gas/riscv/zc-zcb-fail-operand-1.s | 14 ++++++++ gas/testsuite/gas/riscv/zc-zcb-fail-xlen.d | 3 ++ gas/testsuite/gas/riscv/zc-zcb-fail-xlen.l | 4 +++ gas/testsuite/gas/riscv/zc-zcb-fail-xlen.s | 5 +++ gas/testsuite/gas/riscv/zc-zcb-lbu.d | 26 ++++++++++++++ gas/testsuite/gas/riscv/zc-zcb-lbu.s | 22 ++++++++++++ gas/testsuite/gas/riscv/zc-zcb-lh.d | 26 ++++++++++++++ gas/testsuite/gas/riscv/zc-zcb-lh.s | 22 ++++++++++++ gas/testsuite/gas/riscv/zc-zcb-lhu.d | 26 ++++++++++++++ gas/testsuite/gas/riscv/zc-zcb-lhu.s | 22 ++++++++++++ gas/testsuite/gas/riscv/zc-zcb-mul.d | 21 +++++++++++ gas/testsuite/gas/riscv/zc-zcb-mul.s | 19 ++++++++++ gas/testsuite/gas/riscv/zc-zcb-not.d | 21 +++++++++++ gas/testsuite/gas/riscv/zc-zcb-not.s | 19 ++++++++++ gas/testsuite/gas/riscv/zc-zcb-sb.d | 26 ++++++++++++++ gas/testsuite/gas/riscv/zc-zcb-sb.s | 22 ++++++++++++ gas/testsuite/gas/riscv/zc-zcb-sext-b.s | 14 ++++++++ gas/testsuite/gas/riscv/zc-zcb-sext-h.s | 14 ++++++++ gas/testsuite/gas/riscv/zc-zcb-sextw.d | 18 ++++++++++ gas/testsuite/gas/riscv/zc-zcb-sextw.s | 13 +++++++ gas/testsuite/gas/riscv/zc-zcb-sh.d | 26 ++++++++++++++ gas/testsuite/gas/riscv/zc-zcb-sh.s | 22 ++++++++++++ gas/testsuite/gas/riscv/zc-zcb-test-arch-gc.d | 28 +++++++++++++++ .../gas/riscv/zc-zcb-test-arch-no-zcb.d | 28 +++++++++++++++ gas/testsuite/gas/riscv/zc-zcb-test-arch.s | 22 ++++++++++++ .../gas/riscv/zc-zcb-test-operand-0.d | 36 +++++++++++++++++++ .../gas/riscv/zc-zcb-test-operand-0.s | 32 +++++++++++++++++ .../gas/riscv/zc-zcb-test-operand-1.d | 18 ++++++++++ .../gas/riscv/zc-zcb-test-operand-1.s | 11 ++++++ .../gas/riscv/zc-zcb-test-operand-2.d | 28 +++++++++++++++ .../gas/riscv/zc-zcb-test-operand-2.s | 21 +++++++++++ gas/testsuite/gas/riscv/zc-zcb-zext-b.d | 20 +++++++++++ gas/testsuite/gas/riscv/zc-zcb-zext-b.s | 14 ++++++++ gas/testsuite/gas/riscv/zc-zcb-zext-h.d | 20 +++++++++++ gas/testsuite/gas/riscv/zc-zcb-zext-h.s | 14 ++++++++ gas/testsuite/gas/riscv/zc-zcb-zextw.d | 20 +++++++++++ gas/testsuite/gas/riscv/zc-zcb-zextw.s | 16 +++++++++ 48 files changed, 828 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.l create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.l create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.l create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.l create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-xlen.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-xlen.l create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-xlen.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lbu.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lbu.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lh.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lh.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lhu.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lhu.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-mul.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-mul.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-not.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-not.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sb.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sb.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sext-b.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sext-h.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sextw.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sextw.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sh.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sh.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-arch-gc.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-arch.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-0.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-0.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-1.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-1.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-2.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-2.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zext-b.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zext-b.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zext-h.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zext-h.s create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zextw.d create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zextw.s diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.d b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.d new file mode 100644 index 00000000000..a5f6a1eb5cb --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.d @@ -0,0 +1,3 @@ +#as: -march=rv64g_zca_zba_zbb +#source: zc-zcb-fail-arch-0.s +#error_output: zc-zcb-fail-arch-0.l diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.l b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.l new file mode 100644 index 00000000000..010186461c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.l @@ -0,0 +1,9 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `c.mul a0,a1', extension `zcb' and `zmmul', or `zcb' and `m' required +.*: Error: unrecognized opcode `c.sext.b a0', extension `zcb' and `zbb' required +.*: Error: unrecognized opcode `c.sext.h a0', extension `zcb' and `zbb' required +.*: Error: unrecognized opcode `c.zext.h a0', extension `zcb' and `zbb' required +.*: Error: unrecognized opcode `c.zext.w a0', extension `zcb' and `zba' required +.*: Error: unrecognized opcode `c.zext.b a0', extension `zcb' required +.*: Error: unrecognized opcode `c.sext.w a0', extension `zcb' required +.*: Error: unrecognized opcode `c.not a1', extension `zcb' required diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.s b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.s new file mode 100644 index 00000000000..eecb58b9835 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.s @@ -0,0 +1,10 @@ +# test cases when zcb arch string is missing +zcb: + c.mul a0,a1 + c.sext.b a0 + c.sext.h a0 + c.zext.h a0 + c.zext.w a0 + c.zext.b a0 + c.sext.w a0 + c.not a1 diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.d b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.d new file mode 100644 index 00000000000..47bb55270f5 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_zca_zcb +#source: zc-zcb-fail-operand-1.s +#error_output: zc-zcb-fail-operand-1.l diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.l b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.l new file mode 100644 index 00000000000..2fddd66c362 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.l @@ -0,0 +1,6 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `c.mul a0,a1' +.*: Error: unrecognized opcode `c.sext.b a0' +.*: Error: unrecognized opcode `c.sext.h a0' +.*: Error: unrecognized opcode `c.zext.h a0' +.*: Error: unrecognized opcode `c.zext.w a0' diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.s b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.s new file mode 100644 index 00000000000..bbe76c240a8 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.s @@ -0,0 +1,17 @@ +# test missing prerequisites cases +zcb: + # prerequisites of c.mul: M ext + c.mul a0,a1 + + # prerequisites of c.sext.b, c.sext.h, c.zext.h: ZBB ext + c.sext.b a0 + c.sext.h a0 + c.zext.h a0 + + # prerequisites of c.zext.w: ZBA ext + c.zext.w a0 + + # c.zext.b, c.sext.w and c.not have no prerequisites + c.zext.b a0 + c.sext.w a0 + c.not a1 diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.d b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.d new file mode 100644 index 00000000000..0a473c47590 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.d @@ -0,0 +1,3 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-fail-operand-0.s +#error_output: zc-zcb-fail-operand-0.l diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.l b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.l new file mode 100644 index 00000000000..dd62dab08ba --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*: Error: illegal operands `c.sb x9,5\(x9\)' +.*: Error: illegal operands `c.lbu x15,-1\(x15\)' +.*: Error: illegal operands `c.lbu x8,8\(x8\)' +.*: Error: illegal operands `c.sb x9,-2\(x9\)' +.*: Error: illegal operands `c.lbu x12,8\(x12\)' +.*: Error: illegal operands `c.sb x12,x0\(x12\)' +.*: Error: illegal operands `c.sh x9,4\(x9\)' +.*: Error: illegal operands `c.sh x15,-4\(x15\)' +.*: Error: illegal operands `c.lh x8,1\(x8\)' +.*: Error: illegal operands `c.lh x9,-2\(x9\)' +.*: Error: illegal operands `c.lhu x12,8\(x12\)' +.*: Error: illegal operands `c.lhu x12,x2\(x12\)' diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.s b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.s new file mode 100644 index 00000000000..6831325cccc --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.s @@ -0,0 +1,17 @@ +# test imm operands of load and save instructions in zcb +target: + # the valid immediate operand of c.sb, c.lbu is 2-bit unsigned immediate from 0 to 3. + c.sb x9,5(x9) + c.lbu x15,-1(x15) + c.lbu x8,8(x8) + c.sb x9,-2(x9) + c.lbu x12,8(x12) + c.sb x12,x0(x12) + + # the valid immediate operand of c.sh, c.lhu and c.lh is 0 or 2. + c.sh x9,4(x9) + c.sh x15,-4(x15) + c.lh x8,1(x8) + c.lh x9,-2(x9) + c.lhu x12,8(x12) + c.lhu x12,x2(x12) diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.d b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.d new file mode 100644 index 00000000000..8a3c482e963 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.d @@ -0,0 +1,3 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-fail-operand-1.s +#error_output: zc-zcb-fail-operand-1.l diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.l b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.l new file mode 100644 index 00000000000..0a725be1d56 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.l @@ -0,0 +1,11 @@ +.*: Assembler messages: +.*: Error: illegal operands `c.sb x7,1\(x9\)' +.*: Error: illegal operands `c.sb x17,1\(x17\)' +.*: Error: illegal operands `c.sh x7,4\(x7\)' +.*: Error: illegal operands `c.sh x19,4\(x16\)' +.*: Error: illegal operands `c.lbu x7,1\(x10\)' +.*: Error: illegal operands `c.lbu x16,1\(x16\)' +.*: Error: illegal operands `c.lh x7,4\(x10\)' +.*: Error: illegal operands `c.lh x16,4\(x16\)' +.*: Error: illegal operands `c.lhu x7,4\(x15\)' +.*: Error: illegal operands `c.lhu x15,4\(x16\)' diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.s b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.s new file mode 100644 index 00000000000..e4d92b7fc8f --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.s @@ -0,0 +1,14 @@ +# the register operand of load and save instructions in ZCB +# requires the destination register is the source register and +# the register is ranged from x8 to x15 +target: + c.sb x7,1(x9) + c.sb x17,1(x17) + c.sh x7,4(x7) + c.sh x19,4(x16) + c.lbu x7,1(x10) + c.lbu x16,1(x16) + c.lh x7,4(x10) + c.lh x16,4(x16) + c.lhu x7,4(x15) + c.lhu x15,4(x16) diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.d b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.d new file mode 100644 index 00000000000..d2c0a2cab0b --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.d @@ -0,0 +1,3 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-fail-xlen.s +#error_output: zc-zcb-fail-xlen.l diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.l b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.l new file mode 100644 index 00000000000..7cb91231fe1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.l @@ -0,0 +1,4 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `c.zext.w x8' +.*: Error: unrecognized opcode `c.zext.w x11' +.*: Error: unrecognized opcode `c.sext.w x11' diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.s b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.s new file mode 100644 index 00000000000..52cb9628a80 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.s @@ -0,0 +1,5 @@ +# c.zext.w and c.sext.w are only in rv64 +target: + c.zext.w x8 + c.zext.w x11 + c.sext.w x11 diff --git a/gas/testsuite/gas/riscv/zc-zcb-lbu.d b/gas/testsuite/gas/riscv/zc-zcb-lbu.d new file mode 100644 index 00000000000..f65984eb2db --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-lbu.d @@ -0,0 +1,26 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-lbu.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+8120[ ]+c.lbu[ ]+s0,2\(a0\) +[ ]*[0-9a-f]+:[ ]+825c[ ]+c.lbu[ ]+a5,1\(a2\) +[ ]*[0-9a-f]+:[ ]+80e0[ ]+c.lbu[ ]+s0,3\(s1\) +[ ]*[0-9a-f]+:[ ]+8024[ ]+c.lbu[ ]+s1,2\(s0\) +[ ]*[0-9a-f]+:[ ]+8050[ ]+c.lbu[ ]+a2,1\(s0\) +[ ]*[0-9a-f]+:[ ]+83f4[ ]+c.lbu[ ]+a3,3\(a5\) +[ ]*[0-9a-f]+:[ ]+8398[ ]+c.lbu[ ]+a4,0\(a5\) +[ ]*[0-9a-f]+:[ ]+8044[ ]+c.lbu[ ]+s1,1\(s0\) +[ ]*[0-9a-f]+:[ ]+83bc[ ]+c.lbu[ ]+a5,2\(a5\) +[ ]*[0-9a-f]+:[ ]+8060[ ]+c.lbu[ ]+s0,3\(s0\) +[ ]*[0-9a-f]+:[ ]+80dc[ ]+c.lbu[ ]+a5,1\(s1\) +[ ]*[0-9a-f]+:[ ]+823c[ ]+c.lbu[ ]+a5,2\(a2\) +[ ]*[0-9a-f]+:[ ]+83d4[ ]+c.lbu[ ]+a3,1\(a5\) +[ ]*[0-9a-f]+:[ ]+8398[ ]+c.lbu[ ]+a4,0\(a5\) +[ ]*[0-9a-f]+:[ ]+8380[ ]+c.lbu[ ]+s0,0\(a5\) +[ ]*[0-9a-f]+:[ ]+8004[ ]+c.lbu[ ]+s1,0\(s0\) diff --git a/gas/testsuite/gas/riscv/zc-zcb-lbu.s b/gas/testsuite/gas/riscv/zc-zcb-lbu.s new file mode 100644 index 00000000000..bec4d32fa45 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-lbu.s @@ -0,0 +1,22 @@ +zcb_lbu: + # test to compress lbu + lbu x8,2(x10) + lbu x15,1(x12) + lbu x8,3(x9) + lbu x9,2(x8) + lbu x12,1(x8) + lbu x13,3(x15) + lbu x14,0(x15) + + # test c.lbu + c.lbu x9,1(x8) + c.lbu x15,2(x15) + c.lbu x8,3(x8) + c.lbu x15,1(x9) + c.lbu x15,2(x12) + c.lbu x13,1(x15) + c.lbu x14,0(x15) + + # implicit zero offset + c.lbu x8,(x15) + lbu x9,(x8) diff --git a/gas/testsuite/gas/riscv/zc-zcb-lh.d b/gas/testsuite/gas/riscv/zc-zcb-lh.d new file mode 100644 index 00000000000..66bf0ea1338 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-lh.d @@ -0,0 +1,26 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-lh.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+8460[ ]+c.lh[ ]+s0,2\(s0\) +[ ]*[0-9a-f]+:[ ]+87dc[ ]+c.lh[ ]+a5,0\(a5\) +[ ]*[0-9a-f]+:[ ]+8760[ ]+c.lh[ ]+s0,2\(a4\) +[ ]*[0-9a-f]+:[ ]+86fc[ ]+c.lh[ ]+a5,2\(a3\) +[ ]*[0-9a-f]+:[ ]+8644[ ]+c.lh[ ]+s1,0\(a2\) +[ ]*[0-9a-f]+:[ ]+87e0[ ]+c.lh[ ]+s0,2\(a5\) +[ ]*[0-9a-f]+:[ ]+8750[ ]+c.lh[ ]+a2,0\(a4\) +[ ]*[0-9a-f]+:[ ]+8764[ ]+c.lh[ ]+s1,2\(a4\) +[ ]*[0-9a-f]+:[ ]+87ec[ ]+c.lh[ ]+a1,2\(a5\) +[ ]*[0-9a-f]+:[ ]+8440[ ]+c.lh[ ]+s0,0\(s0\) +[ ]*[0-9a-f]+:[ ]+84c4[ ]+c.lh[ ]+s1,0\(s1\) +[ ]*[0-9a-f]+:[ ]+8660[ ]+c.lh[ ]+s0,2\(a2\) +[ ]*[0-9a-f]+:[ ]+87f4[ ]+c.lh[ ]+a3,2\(a5\) +[ ]*[0-9a-f]+:[ ]+8758[ ]+c.lh[ ]+a4,0\(a4\) +[ ]*[0-9a-f]+:[ ]+844c[ ]+c.lh[ ]+a1,0\(s0\) +[ ]*[0-9a-f]+:[ ]+87c4[ ]+c.lh[ ]+s1,0\(a5\) diff --git a/gas/testsuite/gas/riscv/zc-zcb-lh.s b/gas/testsuite/gas/riscv/zc-zcb-lh.s new file mode 100644 index 00000000000..63894cb8f39 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-lh.s @@ -0,0 +1,22 @@ +zcb_lh: + # test to compress lh + lh x8,2(x8) + lh x15,0(x15) + lh x8,2(x14) + lh x15,2(x13) + lh x9,0(x12) + lh x8,2(x15) + lh x12,0(x14) + + # test c.lh + c.lh x9,2(x14) + c.lh x11,2(x15) + c.lh x8,0(x8) + c.lh x9,0(x9) + c.lh x8,2(x12) + c.lh x13,2(x15) + c.lh x14,0(x14) + + # implicit zero offset + c.lh x11,(x8) + lh x9,(x15) diff --git a/gas/testsuite/gas/riscv/zc-zcb-lhu.d b/gas/testsuite/gas/riscv/zc-zcb-lhu.d new file mode 100644 index 00000000000..6716f42599e --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-lhu.d @@ -0,0 +1,26 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-lhu.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+8420[ ]+c.lhu[ ]+s0,2\(s0\) +[ ]*[0-9a-f]+:[ ]+879c[ ]+c.lhu[ ]+a5,0\(a5\) +[ ]*[0-9a-f]+:[ ]+8720[ ]+c.lhu[ ]+s0,2\(a4\) +[ ]*[0-9a-f]+:[ ]+86bc[ ]+c.lhu[ ]+a5,2\(a3\) +[ ]*[0-9a-f]+:[ ]+8604[ ]+c.lhu[ ]+s1,0\(a2\) +[ ]*[0-9a-f]+:[ ]+87a0[ ]+c.lhu[ ]+s0,2\(a5\) +[ ]*[0-9a-f]+:[ ]+8710[ ]+c.lhu[ ]+a2,0\(a4\) +[ ]*[0-9a-f]+:[ ]+8724[ ]+c.lhu[ ]+s1,2\(a4\) +[ ]*[0-9a-f]+:[ ]+87ac[ ]+c.lhu[ ]+a1,2\(a5\) +[ ]*[0-9a-f]+:[ ]+8400[ ]+c.lhu[ ]+s0,0\(s0\) +[ ]*[0-9a-f]+:[ ]+8484[ ]+c.lhu[ ]+s1,0\(s1\) +[ ]*[0-9a-f]+:[ ]+8620[ ]+c.lhu[ ]+s0,2\(a2\) +[ ]*[0-9a-f]+:[ ]+87b4[ ]+c.lhu[ ]+a3,2\(a5\) +[ ]*[0-9a-f]+:[ ]+8718[ ]+c.lhu[ ]+a4,0\(a4\) +[ ]*[0-9a-f]+:[ ]+840c[ ]+c.lhu[ ]+a1,0\(s0\) +[ ]*[0-9a-f]+:[ ]+8784[ ]+c.lhu[ ]+s1,0\(a5\) diff --git a/gas/testsuite/gas/riscv/zc-zcb-lhu.s b/gas/testsuite/gas/riscv/zc-zcb-lhu.s new file mode 100644 index 00000000000..7a6c4e37312 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-lhu.s @@ -0,0 +1,22 @@ +zcb_lhu: + # test to compress lhu + lhu x8,2(x8) + lhu x15,0(x15) + lhu x8,2(x14) + lhu x15,2(x13) + lhu x9,0(x12) + lhu x8,2(x15) + lhu x12,0(x14) + + # test c.lhu + c.lhu x9,2(x14) + c.lhu x11,2(x15) + c.lhu x8,0(x8) + c.lhu x9,0(x9) + c.lhu x8,2(x12) + c.lhu x13,2(x15) + c.lhu x14,0(x14) + + # implicit zero offset + c.lhu x11,(x8) + lhu x9,(x15) diff --git a/gas/testsuite/gas/riscv/zc-zcb-mul.d b/gas/testsuite/gas/riscv/zc-zcb-mul.d new file mode 100644 index 00000000000..b1f1b305e72 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-mul.d @@ -0,0 +1,21 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-mul.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+9fc1[ ]+c.mul[ ]+a5,s0 +[ ]*[0-9a-f]+:[ ]+9c5d[ ]+c.mul[ ]+s0,a5 +[ ]*[0-9a-f]+:[ ]+9cd1[ ]+c.mul[ ]+s1,a2 +[ ]*[0-9a-f]+:[ ]+9d4d[ ]+c.mul[ ]+a0,a1 +[ ]*[0-9a-f]+:[ ]+9dcd[ ]+c.mul[ ]+a1,a1 +[ ]*[0-9a-f]+:[ ]+9f59[ ]+c.mul[ ]+a4,a4 +[ ]*[0-9a-f]+:[ ]+9fdd[ ]+c.mul[ ]+a5,a5 +[ ]*[0-9a-f]+:[ ]+9c41[ ]+c.mul[ ]+s0,s0 +[ ]*[0-9a-f]+:[ ]+9cd1[ ]+c.mul[ ]+s1,a2 +[ ]*[0-9a-f]+:[ ]+9dd5[ ]+c.mul[ ]+a1,a3 +[ ]*[0-9a-f]+:[ ]+9e51[ ]+c.mul[ ]+a2,a2 diff --git a/gas/testsuite/gas/riscv/zc-zcb-mul.s b/gas/testsuite/gas/riscv/zc-zcb-mul.s new file mode 100644 index 00000000000..9299b2a5c16 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-mul.s @@ -0,0 +1,19 @@ +zcb: + # test to compress mul insturctions(boundary) + mul x15,x15,x8 + mul x8,x8,x15 + + # test to compress mul insturctions + mul x9,x9,x12 + mul x10,x10,x11 + mul x11,x11,x11 + mul x14,x14,x14 + + # test c.mul(boundary) + c.mul x15,x15 + c.mul x8,x8 + + # test c.mul + c.mul x9,x12 + c.mul x11,x13 + c.mul x12,x12 diff --git a/gas/testsuite/gas/riscv/zc-zcb-not.d b/gas/testsuite/gas/riscv/zc-zcb-not.d new file mode 100644 index 00000000000..2ea31078b60 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-not.d @@ -0,0 +1,21 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-not.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+9ff5[ ]+c.not[ ]+a5 +[ ]*[0-9a-f]+:[ ]+9c75[ ]+c.not[ ]+s0 +[ ]*[0-9a-f]+:[ ]+9cf5[ ]+c.not[ ]+s1 +[ ]*[0-9a-f]+:[ ]+9d75[ ]+c.not[ ]+a0 +[ ]*[0-9a-f]+:[ ]+9df5[ ]+c.not[ ]+a1 +[ ]*[0-9a-f]+:[ ]+9f75[ ]+c.not[ ]+a4 +[ ]*[0-9a-f]+:[ ]+9ff5[ ]+c.not[ ]+a5 +[ ]*[0-9a-f]+:[ ]+9c75[ ]+c.not[ ]+s0 +[ ]*[0-9a-f]+:[ ]+9cf5[ ]+c.not[ ]+s1 +[ ]*[0-9a-f]+:[ ]+9df5[ ]+c.not[ ]+a1 +[ ]*[0-9a-f]+:[ ]+9e75[ ]+c.not[ ]+a2 diff --git a/gas/testsuite/gas/riscv/zc-zcb-not.s b/gas/testsuite/gas/riscv/zc-zcb-not.s new file mode 100644 index 00000000000..77f88e70344 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-not.s @@ -0,0 +1,19 @@ +zcb: + # test to compress not insturctions(boundary) + not x15,x15 + not x8,x8 + + # test to compress not insturctions + not x9,x9 + not x10,x10 + not x11,x11 + not x14,x14 + + # test c.not(boundary) + c.not x15 + c.not x8 + + # test c.not + c.not x9 + c.not x11 + c.not x12 diff --git a/gas/testsuite/gas/riscv/zc-zcb-sb.d b/gas/testsuite/gas/riscv/zc-zcb-sb.d new file mode 100644 index 00000000000..a309895c73e --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-sb.d @@ -0,0 +1,26 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-sb.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+8920[ ]+c.sb[ ]+s0,2\(a0\) +[ ]*[0-9a-f]+:[ ]+8a5c[ ]+c.sb[ ]+a5,1\(a2\) +[ ]*[0-9a-f]+:[ ]+88e0[ ]+c.sb[ ]+s0,3\(s1\) +[ ]*[0-9a-f]+:[ ]+8824[ ]+c.sb[ ]+s1,2\(s0\) +[ ]*[0-9a-f]+:[ ]+8850[ ]+c.sb[ ]+a2,1\(s0\) +[ ]*[0-9a-f]+:[ ]+8bf4[ ]+c.sb[ ]+a3,3\(a5\) +[ ]*[0-9a-f]+:[ ]+8b98[ ]+c.sb[ ]+a4,0\(a5\) +[ ]*[0-9a-f]+:[ ]+8844[ ]+c.sb[ ]+s1,1\(s0\) +[ ]*[0-9a-f]+:[ ]+8bbc[ ]+c.sb[ ]+a5,2\(a5\) +[ ]*[0-9a-f]+:[ ]+8860[ ]+c.sb[ ]+s0,3\(s0\) +[ ]*[0-9a-f]+:[ ]+88dc[ ]+c.sb[ ]+a5,1\(s1\) +[ ]*[0-9a-f]+:[ ]+8a3c[ ]+c.sb[ ]+a5,2\(a2\) +[ ]*[0-9a-f]+:[ ]+8bd4[ ]+c.sb[ ]+a3,1\(a5\) +[ ]*[0-9a-f]+:[ ]+8b98[ ]+c.sb[ ]+a4,0\(a5\) +[ ]*[0-9a-f]+:[ ]+8b80[ ]+c.sb[ ]+s0,0\(a5\) +[ ]*[0-9a-f]+:[ ]+8804[ ]+c.sb[ ]+s1,0\(s0\) diff --git a/gas/testsuite/gas/riscv/zc-zcb-sb.s b/gas/testsuite/gas/riscv/zc-zcb-sb.s new file mode 100644 index 00000000000..75a9a9a8227 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-sb.s @@ -0,0 +1,22 @@ +zcb_sb: + # test to compress sb + sb x8,2(x10) + sb x15,1(x12) + sb x8,3(x9) + sb x9,2(x8) + sb x12,1(x8) + sb x13,3(x15) + sb x14,0(x15) + + # test c.sb + c.sb x9,1(x8) + c.sb x15,2(x15) + c.sb x8,3(x8) + c.sb x15,1(x9) + c.sb x15,2(x12) + c.sb x13,1(x15) + c.sb x14,0(x15) + + # implicit zero offset + c.sb x8,(x15) + sb x9,(x8) diff --git a/gas/testsuite/gas/riscv/zc-zcb-sext-b.s b/gas/testsuite/gas/riscv/zc-zcb-sext-b.s new file mode 100644 index 00000000000..9b0c04c0b2d --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-sext-b.s @@ -0,0 +1,14 @@ +zcb: + # test zcb sign/zero extension insturction + c.zext.h x8 + c.zext.h x15 + c.zext.h x10 + c.zext.h x9 + c.zext.h x12 + + # test to compress sign/zero extension insturctions + zext.h x8,x8 + zext.h x15,x15 + zext.h x9,x9 + zext.h x12,x12 + zext.h x14,x14 diff --git a/gas/testsuite/gas/riscv/zc-zcb-sext-h.s b/gas/testsuite/gas/riscv/zc-zcb-sext-h.s new file mode 100644 index 00000000000..f33a7b673cb --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-sext-h.s @@ -0,0 +1,14 @@ +zcb: + # test zcb sign/zero extension insturction + c.zext.b x8 + c.zext.b x15 + c.zext.b x10 + c.zext.b x9 + c.zext.b x12 + + # test to compress sign/zero extension insturctions + zext.b x8,x8 + zext.b x15,x15 + zext.b x9,x9 + zext.b x12,x12 + zext.b x14,x14 diff --git a/gas/testsuite/gas/riscv/zc-zcb-sextw.d b/gas/testsuite/gas/riscv/zc-zcb-sextw.d new file mode 100644 index 00000000000..fb76ae49b82 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-sextw.d @@ -0,0 +1,18 @@ +#as: -march=rv64g_zca_zcb_zbb +#source: zc-zcb-sextw.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+2481[ ]+c.addiw[ ]+s1,0 +[ ]*[0-9a-f]+:[ ]+2081[ ]+c.addiw[ ]+ra,0 +[ ]*[0-9a-f]+:[ ]+2981[ ]+c.addiw[ ]+s3,0 +[ ]*[0-9a-f]+:[ ]+2701[ ]+c.addiw[ ]+a4,0 +[ ]*[0-9a-f]+:[ ]+2781[ ]+c.addiw[ ]+a5,0 +[ ]*[0-9a-f]+:[ ]+2401[ ]+c.addiw[ ]+s0,0 +[ ]*[0-9a-f]+:[ ]+2481[ ]+c.addiw[ ]+s1,0 +[ ]*[0-9a-f]+:[ ]+2581[ ]+c.addiw[ ]+a1,0 diff --git a/gas/testsuite/gas/riscv/zc-zcb-sextw.s b/gas/testsuite/gas/riscv/zc-zcb-sextw.s new file mode 100644 index 00000000000..1b76b058fd3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-sextw.s @@ -0,0 +1,13 @@ +# c.sext.w is an alias of c.addiw +zcb64: + # test to compress zext.w insturctions + sext.w x9,x9 + sext.w x1,x1 + sext.w x19,x19 + sext.w x14,x14 + + # test c.sext.w + c.sext.w x15 + c.sext.w x8 + c.sext.w x9 + c.sext.w x11 diff --git a/gas/testsuite/gas/riscv/zc-zcb-sh.d b/gas/testsuite/gas/riscv/zc-zcb-sh.d new file mode 100644 index 00000000000..5897955357b --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-sh.d @@ -0,0 +1,26 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-sh.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+8c20[ ]+c.sh[ ]+s0,2\(s0\) +[ ]*[0-9a-f]+:[ ]+8f9c[ ]+c.sh[ ]+a5,0\(a5\) +[ ]*[0-9a-f]+:[ ]+8c20[ ]+c.sh[ ]+s0,2\(s0\) +[ ]*[0-9a-f]+:[ ]+8ca4[ ]+c.sh[ ]+s1,2\(s1\) +[ ]*[0-9a-f]+:[ ]+8e10[ ]+c.sh[ ]+a2,0\(a2\) +[ ]*[0-9a-f]+:[ ]+8eb4[ ]+c.sh[ ]+a3,2\(a3\) +[ ]*[0-9a-f]+:[ ]+8f18[ ]+c.sh[ ]+a4,0\(a4\) +[ ]*[0-9a-f]+:[ ]+8ca4[ ]+c.sh[ ]+s1,2\(s1\) +[ ]*[0-9a-f]+:[ ]+8fbc[ ]+c.sh[ ]+a5,2\(a5\) +[ ]*[0-9a-f]+:[ ]+8c00[ ]+c.sh[ ]+s0,0\(s0\) +[ ]*[0-9a-f]+:[ ]+8c84[ ]+c.sh[ ]+s1,0\(s1\) +[ ]*[0-9a-f]+:[ ]+8e30[ ]+c.sh[ ]+a2,2\(a2\) +[ ]*[0-9a-f]+:[ ]+8eb4[ ]+c.sh[ ]+a3,2\(a3\) +[ ]*[0-9a-f]+:[ ]+8f18[ ]+c.sh[ ]+a4,0\(a4\) +[ ]*[0-9a-f]+:[ ]+8c00[ ]+c.sh[ ]+s0,0\(s0\) +[ ]*[0-9a-f]+:[ ]+8c84[ ]+c.sh[ ]+s1,0\(s1\) diff --git a/gas/testsuite/gas/riscv/zc-zcb-sh.s b/gas/testsuite/gas/riscv/zc-zcb-sh.s new file mode 100644 index 00000000000..a7ed266c0fa --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-sh.s @@ -0,0 +1,22 @@ +zcb_sh: + # test to compress sh + sh x8,2(x8) + sh x15,0(x15) + sh x8,2(x8) + sh x9,2(x9) + sh x12,0(x12) + sh x13,2(x13) + sh x14,0(x14) + + # test c.sh + c.sh x9,2(x9) + c.sh x15,2(x15) + c.sh x8,0(x8) + c.sh x9,0(x9) + c.sh x12,2(x12) + c.sh x13,2(x13) + c.sh x14,0(x14) + + # implicit zero offset + c.sh x8,(x8) + sh x9,(x9) diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-arch-gc.d b/gas/testsuite/gas/riscv/zc-zcb-test-arch-gc.d new file mode 100644 index 00000000000..3bda7358ab0 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-test-arch-gc.d @@ -0,0 +1,28 @@ +#as: -march=rv64gc_zba_zbb +#source: zc-zcb-test-arch.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+009480a3+[ ]+sb[ ]+s1,1\(s1\) +[ ]*[0-9a-f]+:[ ]+00f780a3+[ ]+sb[ ]+a5,1\(a5\) +[ ]*[0-9a-f]+:[ ]+0014c483+[ ]+lbu[ ]+s1,1\(s1\) +[ ]*[0-9a-f]+:[ ]+0017c783+[ ]+lbu[ ]+a5,1\(a5\) +[ ]*[0-9a-f]+:[ ]+00449483+[ ]+lh[ ]+s1,4\(s1\) +[ ]*[0-9a-f]+:[ ]+00479783+[ ]+lh[ ]+a5,4\(a5\) +[ ]*[0-9a-f]+:[ ]+0044d483+[ ]+lhu[ ]+s1,4\(s1\) +[ ]*[0-9a-f]+:[ ]+0047d783+[ ]+lhu[ ]+a5,4\(a5\) +[ ]*[0-9a-f]+:[ ]+00949223+[ ]+sh[ ]+s1,4\(s1\) +[ ]*[0-9a-f]+:[ ]+00f79223+[ ]+sh[ ]+a5,4\(a5\) +[ ]*[0-9a-f]+:[ ]+02b50533+[ ]+mul[ ]+a0,a0,a1 +[ ]*[0-9a-f]+:[ ]+60451513+[ ]+sext.b[ ]+a0,a0 +[ ]*[0-9a-f]+:[ ]+60551513+[ ]+sext.h[ ]+a0,a0 +[ ]*[0-9a-f]+:[ ]+0805453b+[ ]+zext.h[ ]+a0,a0 +[ ]*[0-9a-f]+:[ ]+0805053b+[ ]+add.uw[ ]+a0,a0,zero +[ ]*[0-9a-f]+:[ ]+0ff57513+[ ]+andi[ ]+a0,a0,255 +[ ]*[0-9a-f]+:[ ]+fff5c593+[ ]+xori[ ]+a1,a1,-1 +[ ]*[0-9a-f]+:[ ]+2501+[ ]+c.addiw[ ]+a0,0 diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d b/gas/testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d new file mode 100644 index 00000000000..1385503e9f4 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d @@ -0,0 +1,28 @@ +#as: -march=rv64g_zca_zba_zbb +#source: zc-zcb-test-arch.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+009480a3+[ ]+sb[ ]+s1,1\(s1\) +[ ]*[0-9a-f]+:[ ]+00f780a3+[ ]+sb[ ]+a5,1\(a5\) +[ ]*[0-9a-f]+:[ ]+0014c483+[ ]+lbu[ ]+s1,1\(s1\) +[ ]*[0-9a-f]+:[ ]+0017c783+[ ]+lbu[ ]+a5,1\(a5\) +[ ]*[0-9a-f]+:[ ]+00449483+[ ]+lh[ ]+s1,4\(s1\) +[ ]*[0-9a-f]+:[ ]+00479783+[ ]+lh[ ]+a5,4\(a5\) +[ ]*[0-9a-f]+:[ ]+0044d483+[ ]+lhu[ ]+s1,4\(s1\) +[ ]*[0-9a-f]+:[ ]+0047d783+[ ]+lhu[ ]+a5,4\(a5\) +[ ]*[0-9a-f]+:[ ]+00949223+[ ]+sh[ ]+s1,4\(s1\) +[ ]*[0-9a-f]+:[ ]+00f79223+[ ]+sh[ ]+a5,4\(a5\) +[ ]*[0-9a-f]+:[ ]+02b50533+[ ]+mul[ ]+a0,a0,a1 +[ ]*[0-9a-f]+:[ ]+60451513+[ ]+sext.b[ ]+a0,a0 +[ ]*[0-9a-f]+:[ ]+60551513+[ ]+sext.h[ ]+a0,a0 +[ ]*[0-9a-f]+:[ ]+0805453b+[ ]+zext.h[ ]+a0,a0 +[ ]*[0-9a-f]+:[ ]+0805053b+[ ]+add.uw[ ]+a0,a0,zero +[ ]*[0-9a-f]+:[ ]+0ff57513+[ ]+andi[ ]+a0,a0,255 +[ ]*[0-9a-f]+:[ ]+fff5c593+[ ]+xori[ ]+a1,a1,-1 +[ ]*[0-9a-f]+:[ ]+2501+[ ]+c.addiw[ ]+a0,0 diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-arch.s b/gas/testsuite/gas/riscv/zc-zcb-test-arch.s new file mode 100644 index 00000000000..ae7292af598 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-test-arch.s @@ -0,0 +1,22 @@ +# except c.sext.w compressed into c.addiw, no compression happens without zcb +target: + sb x9,1(x9) + sb x15,1(x15) + lbu x9,1(x9) + lbu x15,1(x15) + lh x9,4(x9) + lh x15,4(x15) + lhu x9,4(x9) + lhu x15,4(x15) + sh x9,4(x9) + sh x15,4(x15) + + mul a0,a0,a1 + sext.b a0,a0 + sext.h a0,a0 + zext.h a0,a0 + zext.w a0,a0 # alias of add.uw rd,rd,zero + + zext.b a0,a0 # alias of andi rd,rs,255 + not a1,a1 # alias of xori rd,rs,-1 + sext.w a0,a0 # alias of addiw rd,rs,0 diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.d b/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.d new file mode 100644 index 00000000000..5e7d405c024 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.d @@ -0,0 +1,36 @@ +#as: -march=rv64g_zca_zcb_zba_zbb +#source: zc-zcb-test-operand-0.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+001480a3+[ ]+sb[ ]+ra,1\(s1\) +[ ]*[0-9a-f]+:[ ]+00a980a3+[ ]+sb[ ]+a0,1\(s3\) +[ ]*[0-9a-f]+:[ ]+00f09123+[ ]+sh[ ]+a5,2\(ra\) +[ ]*[0-9a-f]+:[ ]+00f292a3+[ ]+sh[ ]+a5,5\(t0\) +[ ]*[0-9a-f]+:[ ]+0017c003+[ ]+lbu[ ]+zero,1\(a5\) +[ ]*[0-9a-f]+:[ ]+00114503+[ ]+lbu[ ]+a0,1\(sp\) +[ ]*[0-9a-f]+:[ ]+00291483+[ ]+lh[ ]+s1,2\(s2\) +[ ]*[0-9a-f]+:[ ]+00259903+[ ]+lh[ ]+s2,2\(a1\) +[ ]*[0-9a-f]+:[ ]+00285483+[ ]+lhu[ ]+s1,2\(a6\) +[ ]*[0-9a-f]+:[ ]+00255383+[ ]+lhu[ ]+t2,2\(a0\) +[ ]*[0-9a-f]+:[ ]+fff84813+[ ]+xori[ ]+a6,a6,-1 +[ ]*[0-9a-f]+:[ ]+ffffcf93+[ ]+xori[ ]+t6,t6,-1 +[ ]*[0-9a-f]+:[ ]+02b383b3+[ ]+mul[ ]+t2,t2,a1 +[ ]*[0-9a-f]+:[ ]+026484b3+[ ]+mul[ ]+s1,s1,t1 +[ ]*[0-9a-f]+:[ ]+02b80833+[ ]+mul[ ]+a6,a6,a1 +[ ]*[0-9a-f]+:[ ]+030484b3+[ ]+mul[ ]+s1,s1,a6 +[ ]*[0-9a-f]+:[ ]+60429293+[ ]+sext.b[ ]+t0,t0 +[ ]*[0-9a-f]+:[ ]+60401013+[ ]+sext.b[ ]+zero,zero +[ ]*[0-9a-f]+:[ ]+60521213+[ ]+sext.h[ ]+tp,tp +[ ]*[0-9a-f]+:[ ]+60529293+[ ]+sext.h[ ]+t0,t0 +[ ]*[0-9a-f]+:[ ]+0ffb7b13+[ ]+andi[ ]+s6,s6,255 +[ ]*[0-9a-f]+:[ ]+0ffafa93+[ ]+andi[ ]+s5,s5,255 +[ ]*[0-9a-f]+:[ ]+0808c8bb+[ ]+zext.h[ ]+a7,a7 +[ ]*[0-9a-f]+:[ ]+0800403b+[ ]+zext.h[ ]+zero,zero +[ ]*[0-9a-f]+:[ ]+080284bb+[ ]+add.uw[ ]+s1,t0,zero +[ ]*[0-9a-f]+:[ ]+0800003b+[ ]+add.uw[ ]+zero,zero,zero diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.s b/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.s new file mode 100644 index 00000000000..0d0944c7517 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.s @@ -0,0 +1,32 @@ +# test if zcb instructions compress instructions with improper operands +target: + # rs' or rd' not in x8-x15 + sb x1,1(x9) + sb x10,1(x19) + sh x15,2(x1) + sh x15,5(x5) + lbu x0,1(x15) + lbu x10,1(x2) + lh x9,2(x18) + lh x18,2(x11) + lhu x9,2(x16) + lhu x7,2(x10) + # not rd,rs is an alias of xori rd,rs,-1 + not x16,x16 + not x31,x31 + mul x7,x7,x11 + mul x9,x9,x6 + mul x16,x16,x11 + mul x9,x9,x16 + sext.b x5,x5 + sext.b x0,x0 + sext.h x4,x4 + sext.h x5,x5 + # zext.b rd,rs is an alias of andi rd,rs,255 + zext.b x22,x22 + zext.b x21,x21 + zext.h x17,x17 + zext.h x0,x0 + # zext.w rd,rs is an alias of add.uw rd,rs,zero + zext.w x9,x5 + zext.w x0,x0 diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.d b/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.d new file mode 100644 index 00000000000..cd97b94dfa8 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.d @@ -0,0 +1,18 @@ +#as: -march=rv64g_zca_zcb_zba_zbb +#source: zc-zcb-test-operand-1.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+fff54493+[ ]+xori[ ]+s1,a0,-1 +[ ]*[0-9a-f]+:[ ]+02b48533+[ ]+mul[ ]+a0,s1,a1 +[ ]*[0-9a-f]+:[ ]+60449413+[ ]+sext.b[ ]+s0,s1 +[ ]*[0-9a-f]+:[ ]+60549513+[ ]+sext.h[ ]+a0,s1 +[ ]*[0-9a-f]+:[ ]+0004841b+[ ]+addiw[ ]+s0,s1,0 +[ ]*[0-9a-f]+:[ ]+0ff4f593+[ ]+andi[ ]+a1,s1,255 +[ ]*[0-9a-f]+:[ ]+0804c43b+[ ]+zext.h[ ]+s0,s1 +[ ]*[0-9a-f]+:[ ]+0804863b+[ ]+add.uw[ ]+a2,s1,zero diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.s b/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.s new file mode 100644 index 00000000000..e5c46370f42 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.s @@ -0,0 +1,11 @@ +# test if zcb instructions compress instructions with improper operands +target: + # rs' != rd' + not x9,x10 + mul x10,x9,x11 + sext.b x8,x9 + sext.h x10,x9 + sext.w x8,x9 + zext.b x11,x9 + zext.h x8,x9 + zext.w x12,x9 diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.d b/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.d new file mode 100644 index 00000000000..415553f6d4b --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.d @@ -0,0 +1,28 @@ +#as: -march=rv64g_zca_zcb +#source: zc-zcb-test-operand-2.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+fe840fa3+[ ]+sb[ ]+s0,-1\(s0\) +[ ]*[0-9a-f]+:[ ]+00840223+[ ]+sb[ ]+s0,4\(s0\) +[ ]*[0-9a-f]+:[ ]+fe840f23+[ ]+sb[ ]+s0,-2\(s0\) +[ ]*[0-9a-f]+:[ ]+fff44403+[ ]+lbu[ ]+s0,-1\(s0\) +[ ]*[0-9a-f]+:[ ]+00444403+[ ]+lbu[ ]+s0,4\(s0\) +[ ]*[0-9a-f]+:[ ]+ffe44403+[ ]+lbu[ ]+s0,-2\(s0\) +[ ]*[0-9a-f]+:[ ]+00841223+[ ]+sh[ ]+s0,4\(s0\) +[ ]*[0-9a-f]+:[ ]+008411a3+[ ]+sh[ ]+s0,3\(s0\) +[ ]*[0-9a-f]+:[ ]+fe841fa3+[ ]+sh[ ]+s0,-1\(s0\) +[ ]*[0-9a-f]+:[ ]+fe841f23+[ ]+sh[ ]+s0,-2\(s0\) +[ ]*[0-9a-f]+:[ ]+00441403+[ ]+lh[ ]+s0,4\(s0\) +[ ]*[0-9a-f]+:[ ]+00341403+[ ]+lh[ ]+s0,3\(s0\) +[ ]*[0-9a-f]+:[ ]+fff41403+[ ]+lh[ ]+s0,-1\(s0\) +[ ]*[0-9a-f]+:[ ]+ffd41403+[ ]+lh[ ]+s0,-3\(s0\) +[ ]*[0-9a-f]+:[ ]+00445403+[ ]+lhu[ ]+s0,4\(s0\) +[ ]*[0-9a-f]+:[ ]+00345403+[ ]+lhu[ ]+s0,3\(s0\) +[ ]*[0-9a-f]+:[ ]+fff45403+[ ]+lhu[ ]+s0,-1\(s0\) +[ ]*[0-9a-f]+:[ ]+00345403+[ ]+lhu[ ]+s0,3\(s0\) diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.s b/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.s new file mode 100644 index 00000000000..5de7e2e65c8 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.s @@ -0,0 +1,21 @@ +# test if zcb instructions compress instructions with improper operands +target: + # improper imm operands + sb x8,-1(x8) + sb x8,4(x8) + sb x8,-2(x8) + lbu x8,-1(x8) + lbu x8,4(x8) + lbu x8,-2(x8) + sh x8,4(x8) + sh x8,3(x8) + sh x8,-1(x8) + sh x8,-2(x8) + lh x8,4(x8) + lh x8,3(x8) + lh x8,-1(x8) + lh x8,-3(x8) + lhu x8,4(x8) + lhu x8,3(x8) + lhu x8,-1(x8) + lhu x8,3(x8) diff --git a/gas/testsuite/gas/riscv/zc-zcb-zext-b.d b/gas/testsuite/gas/riscv/zc-zcb-zext-b.d new file mode 100644 index 00000000000..16dfad2b620 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-zext-b.d @@ -0,0 +1,20 @@ +#as: -march=rv32g_zca_zcb +#source: zc-zcb-zext-b.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+9c61[ ]+c.zext.b[ ]+s0 +[ ]*[0-9a-f]+:[ ]+9fe1[ ]+c.zext.b[ ]+a5 +[ ]*[0-9a-f]+:[ ]+9d61[ ]+c.zext.b[ ]+a0 +[ ]*[0-9a-f]+:[ ]+9ce1[ ]+c.zext.b[ ]+s1 +[ ]*[0-9a-f]+:[ ]+9e61[ ]+c.zext.b[ ]+a2 +[ ]*[0-9a-f]+:[ ]+9c61[ ]+c.zext.b[ ]+s0 +[ ]*[0-9a-f]+:[ ]+9fe1[ ]+c.zext.b[ ]+a5 +[ ]*[0-9a-f]+:[ ]+9ce1[ ]+c.zext.b[ ]+s1 +[ ]*[0-9a-f]+:[ ]+9e61[ ]+c.zext.b[ ]+a2 +[ ]*[0-9a-f]+:[ ]+9f61[ ]+c.zext.b[ ]+a4 diff --git a/gas/testsuite/gas/riscv/zc-zcb-zext-b.s b/gas/testsuite/gas/riscv/zc-zcb-zext-b.s new file mode 100644 index 00000000000..f33a7b673cb --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-zext-b.s @@ -0,0 +1,14 @@ +zcb: + # test zcb sign/zero extension insturction + c.zext.b x8 + c.zext.b x15 + c.zext.b x10 + c.zext.b x9 + c.zext.b x12 + + # test to compress sign/zero extension insturctions + zext.b x8,x8 + zext.b x15,x15 + zext.b x9,x9 + zext.b x12,x12 + zext.b x14,x14 diff --git a/gas/testsuite/gas/riscv/zc-zcb-zext-h.d b/gas/testsuite/gas/riscv/zc-zcb-zext-h.d new file mode 100644 index 00000000000..e060a1eee85 --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-zext-h.d @@ -0,0 +1,20 @@ +#as: -march=rv32g_zca_zcb_zbb +#source: zc-zcb-zext-h.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+9c69[ ]+c.zext.h[ ]+s0 +[ ]*[0-9a-f]+:[ ]+9fe9[ ]+c.zext.h[ ]+a5 +[ ]*[0-9a-f]+:[ ]+9d69[ ]+c.zext.h[ ]+a0 +[ ]*[0-9a-f]+:[ ]+9ce9[ ]+c.zext.h[ ]+s1 +[ ]*[0-9a-f]+:[ ]+9e69[ ]+c.zext.h[ ]+a2 +[ ]*[0-9a-f]+:[ ]+9c69[ ]+c.zext.h[ ]+s0 +[ ]*[0-9a-f]+:[ ]+9fe9[ ]+c.zext.h[ ]+a5 +[ ]*[0-9a-f]+:[ ]+9ce9[ ]+c.zext.h[ ]+s1 +[ ]*[0-9a-f]+:[ ]+9e69[ ]+c.zext.h[ ]+a2 +[ ]*[0-9a-f]+:[ ]+9f69[ ]+c.zext.h[ ]+a4 diff --git a/gas/testsuite/gas/riscv/zc-zcb-zext-h.s b/gas/testsuite/gas/riscv/zc-zcb-zext-h.s new file mode 100644 index 00000000000..9b0c04c0b2d --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-zext-h.s @@ -0,0 +1,14 @@ +zcb: + # test zcb sign/zero extension insturction + c.zext.h x8 + c.zext.h x15 + c.zext.h x10 + c.zext.h x9 + c.zext.h x12 + + # test to compress sign/zero extension insturctions + zext.h x8,x8 + zext.h x15,x15 + zext.h x9,x9 + zext.h x12,x12 + zext.h x14,x14 diff --git a/gas/testsuite/gas/riscv/zc-zcb-zextw.d b/gas/testsuite/gas/riscv/zc-zcb-zextw.d new file mode 100644 index 00000000000..81a9d5c500d --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-zextw.d @@ -0,0 +1,20 @@ +#as: -march=rv64g_zca_zcb_zba +#source: zc-zcb-zextw.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+9cf1[ ]+c.zext.w[ ]+s1 +[ ]*[0-9a-f]+:[ ]+9d71[ ]+c.zext.w[ ]+a0 +[ ]*[0-9a-f]+:[ ]+9df1[ ]+c.zext.w[ ]+a1 +[ ]*[0-9a-f]+:[ ]+9f71[ ]+c.zext.w[ ]+a4 +[ ]*[0-9a-f]+:[ ]+9ff1[ ]+c.zext.w[ ]+a5 +[ ]*[0-9a-f]+:[ ]+9c71[ ]+c.zext.w[ ]+s0 +[ ]*[0-9a-f]+:[ ]+9ff1[ ]+c.zext.w[ ]+a5 +[ ]*[0-9a-f]+:[ ]+9c71[ ]+c.zext.w[ ]+s0 +[ ]*[0-9a-f]+:[ ]+9cf1[ ]+c.zext.w[ ]+s1 +[ ]*[0-9a-f]+:[ ]+9df1[ ]+c.zext.w[ ]+a1 diff --git a/gas/testsuite/gas/riscv/zc-zcb-zextw.s b/gas/testsuite/gas/riscv/zc-zcb-zextw.s new file mode 100644 index 00000000000..9c40f8fa80f --- /dev/null +++ b/gas/testsuite/gas/riscv/zc-zcb-zextw.s @@ -0,0 +1,16 @@ +zcb64: + # test to compress zext.w insturctions + zext.w x9,x9 + zext.w x10,x10 + zext.w x11,x11 + zext.w x14,x14 + + # test to compress sign/zero extension insturctions(boundary) + zext.w x15,x15 + zext.w x8,x8 + + # test c.zext.w + c.zext.w x15 + c.zext.w x8 + c.zext.w x9 + c.zext.w x11