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(mdns.lwn.net [45.79.72.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ms.lwn.net (Postfix) with ESMTPSA id B5F755BF; Tue, 13 Jun 2023 09:46:21 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 ms.lwn.net B5F755BF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lwn.net; s=20201203; t=1686649586; bh=dWpoeAXMJ/celJyNlHg+oUI0iRRMPpCQdfgVvBB7a8I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L/Y20rYEgtSIsvR1c6iXgLgDQIkA3qUoKYVjLduUFOF3535eDlpUut7Vzp6h2UpOQ lxtPL/PUQnOVY/AiwtZFaLEY+BZ9K13Sd8xvwCXA15KwCdz4F/6lEytPKBfiRLSGG+ R7KUeVAuUA04ZGounbjz2cQgEn/cVFy8i6MRoZ2qEtVthLiVHmyLGtmTOGLGDnXCXy veS3KndFFO9zfddDlcuOH9UpVMYce13mblGLbh9gjJhslXo7T8wbCEvhyKkUqJDPxm +24hmeA2Pn01xWJ9RB5d+8qrFErxvZWPipctrA1WMKVAjd6ttuQ+lAIfxYcOj5LNf/ EELEP9Y+9fWAw== From: Jonathan Corbet To: linux-doc@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonathan Corbet , Catalin Marinas , Will Deacon , Alex Shi , Yanteng Si , Hu Haowen , Paolo Bonzini Subject: [PATCH 1/5] docs: arm64: Move arm64 documentation under Documentation/arch/ Date: Tue, 13 Jun 2023 03:46:02 -0600 Message-Id: <20230613094606.334687-2-corbet@lwn.net> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613094606.334687-1-corbet@lwn.net> References: <20230613094606.334687-1-corbet@lwn.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768581196173644335?= X-GMAIL-MSGID: =?utf-8?q?1768581196173644335?= Architecture-specific documentation is being moved into Documentation/arch/ as a way of cleaning up the top-level documentation directory and making the docs hierarchy more closely match the source hierarchy. Move Documentation/arm64 into arch/ (along with the Chinese equvalent translations) and fix up documentation references. Cc: Catalin Marinas Cc: Will Deacon Cc: Alex Shi Cc: Yanteng Si Cc: Hu Haowen Cc: Paolo Bonzini Signed-off-by: Jonathan Corbet Reviewed-by: Yantengsi Acked-by: Catalin Marinas --- Documentation/ABI/testing/sysfs-devices-system-cpu | 2 +- Documentation/admin-guide/kernel-parameters.txt | 2 +- Documentation/admin-guide/sysctl/kernel.rst | 2 +- Documentation/{ => arch}/arm64/acpi_object_usage.rst | 0 Documentation/{ => arch}/arm64/amu.rst | 0 Documentation/{ => arch}/arm64/arm-acpi.rst | 2 +- Documentation/{ => arch}/arm64/asymmetric-32bit.rst | 0 Documentation/{ => arch}/arm64/booting.rst | 0 .../{ => arch}/arm64/cpu-feature-registers.rst | 0 Documentation/{ => arch}/arm64/elf_hwcaps.rst | 12 ++++++------ Documentation/{ => arch}/arm64/features.rst | 0 Documentation/{ => arch}/arm64/hugetlbpage.rst | 0 Documentation/{ => arch}/arm64/index.rst | 0 Documentation/{ => arch}/arm64/kasan-offsets.sh | 0 .../{ => arch}/arm64/legacy_instructions.rst | 0 .../{ => arch}/arm64/memory-tagging-extension.rst | 2 +- Documentation/{ => arch}/arm64/memory.rst | 0 Documentation/{ => arch}/arm64/perf.rst | 0 .../{ => arch}/arm64/pointer-authentication.rst | 0 Documentation/{ => arch}/arm64/silicon-errata.rst | 0 Documentation/{ => arch}/arm64/sme.rst | 2 +- Documentation/{ => arch}/arm64/sve.rst | 2 +- .../{ => arch}/arm64/tagged-address-abi.rst | 2 +- Documentation/{ => arch}/arm64/tagged-pointers.rst | 2 +- Documentation/arch/index.rst | 2 +- .../translations/zh_CN/{ => arch}/arm64/amu.rst | 4 ++-- .../translations/zh_CN/{ => arch}/arm64/booting.txt | 4 ++-- .../zh_CN/{ => arch}/arm64/elf_hwcaps.rst | 10 +++++----- .../zh_CN/{ => arch}/arm64/hugetlbpage.rst | 4 ++-- .../translations/zh_CN/{ => arch}/arm64/index.rst | 4 ++-- .../zh_CN/{ => arch}/arm64/legacy_instructions.txt | 4 ++-- .../translations/zh_CN/{ => arch}/arm64/memory.txt | 4 ++-- .../translations/zh_CN/{ => arch}/arm64/perf.rst | 4 ++-- .../zh_CN/{ => arch}/arm64/silicon-errata.txt | 4 ++-- .../zh_CN/{ => arch}/arm64/tagged-pointers.txt | 4 ++-- Documentation/translations/zh_CN/arch/index.rst | 2 +- .../translations/zh_TW/{ => arch}/arm64/amu.rst | 4 ++-- .../translations/zh_TW/{ => arch}/arm64/booting.txt | 4 ++-- .../zh_TW/{ => arch}/arm64/elf_hwcaps.rst | 10 +++++----- .../zh_TW/{ => arch}/arm64/hugetlbpage.rst | 4 ++-- .../translations/zh_TW/{ => arch}/arm64/index.rst | 4 ++-- .../zh_TW/{ => arch}/arm64/legacy_instructions.txt | 4 ++-- .../translations/zh_TW/{ => arch}/arm64/memory.txt | 4 ++-- .../translations/zh_TW/{ => arch}/arm64/perf.rst | 4 ++-- .../zh_TW/{ => arch}/arm64/silicon-errata.txt | 4 ++-- .../zh_TW/{ => arch}/arm64/tagged-pointers.txt | 4 ++-- Documentation/translations/zh_TW/index.rst | 2 +- Documentation/virt/kvm/api.rst | 2 +- MAINTAINERS | 2 +- 49 files changed, 66 insertions(+), 66 deletions(-) rename Documentation/{ => arch}/arm64/acpi_object_usage.rst (100%) rename Documentation/{ => arch}/arm64/amu.rst (100%) rename Documentation/{ => arch}/arm64/arm-acpi.rst (99%) rename Documentation/{ => arch}/arm64/asymmetric-32bit.rst (100%) rename Documentation/{ => arch}/arm64/booting.rst (100%) rename Documentation/{ => arch}/arm64/cpu-feature-registers.rst (100%) rename Documentation/{ => arch}/arm64/elf_hwcaps.rst (96%) rename Documentation/{ => arch}/arm64/features.rst (100%) rename Documentation/{ => arch}/arm64/hugetlbpage.rst (100%) rename Documentation/{ => arch}/arm64/index.rst (100%) rename Documentation/{ => arch}/arm64/kasan-offsets.sh (100%) rename Documentation/{ => arch}/arm64/legacy_instructions.rst (100%) rename Documentation/{ => arch}/arm64/memory-tagging-extension.rst (99%) rename Documentation/{ => arch}/arm64/memory.rst (100%) rename Documentation/{ => arch}/arm64/perf.rst (100%) rename Documentation/{ => arch}/arm64/pointer-authentication.rst (100%) rename Documentation/{ => arch}/arm64/silicon-errata.rst (100%) rename Documentation/{ => arch}/arm64/sme.rst (99%) rename Documentation/{ => arch}/arm64/sve.rst (99%) rename Documentation/{ => arch}/arm64/tagged-address-abi.rst (99%) rename Documentation/{ => arch}/arm64/tagged-pointers.rst (98%) rename Documentation/translations/zh_CN/{ => arch}/arm64/amu.rst (97%) rename Documentation/translations/zh_CN/{ => arch}/arm64/booting.txt (98%) rename Documentation/translations/zh_CN/{ => arch}/arm64/elf_hwcaps.rst (94%) rename Documentation/translations/zh_CN/{ => arch}/arm64/hugetlbpage.rst (91%) rename Documentation/translations/zh_CN/{ => arch}/arm64/index.rst (63%) rename Documentation/translations/zh_CN/{ => arch}/arm64/legacy_instructions.txt (95%) rename Documentation/translations/zh_CN/{ => arch}/arm64/memory.txt (97%) rename Documentation/translations/zh_CN/{ => arch}/arm64/perf.rst (96%) rename Documentation/translations/zh_CN/{ => arch}/arm64/silicon-errata.txt (97%) rename Documentation/translations/zh_CN/{ => arch}/arm64/tagged-pointers.txt (94%) rename Documentation/translations/zh_TW/{ => arch}/arm64/amu.rst (97%) rename Documentation/translations/zh_TW/{ => arch}/arm64/booting.txt (98%) rename Documentation/translations/zh_TW/{ => arch}/arm64/elf_hwcaps.rst (94%) rename Documentation/translations/zh_TW/{ => arch}/arm64/hugetlbpage.rst (91%) rename Documentation/translations/zh_TW/{ => arch}/arm64/index.rst (71%) rename Documentation/translations/zh_TW/{ => arch}/arm64/legacy_instructions.txt (96%) rename Documentation/translations/zh_TW/{ => arch}/arm64/memory.txt (97%) rename Documentation/translations/zh_TW/{ => arch}/arm64/perf.rst (96%) rename Documentation/translations/zh_TW/{ => arch}/arm64/silicon-errata.txt (97%) rename Documentation/translations/zh_TW/{ => arch}/arm64/tagged-pointers.txt (95%) diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index f54867cadb0f..ecd585ca2d50 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -670,7 +670,7 @@ Description: Preferred MTE tag checking mode "async" Prefer asynchronous mode ================ ============================================== - See also: Documentation/arm64/memory-tagging-extension.rst + See also: Documentation/arch/arm64/memory-tagging-extension.rst What: /sys/devices/system/cpu/nohz_full Date: Apr 2015 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 9e5bab29685f..893b5a133041 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -304,7 +304,7 @@ EL0 is indicated by /sys/devices/system/cpu/aarch32_el0 and hot-unplug operations may be restricted. - See Documentation/arm64/asymmetric-32bit.rst for more + See Documentation/arch/arm64/asymmetric-32bit.rst for more information. amd_iommu= [HW,X86-64] diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst index d85d90f5d000..3800fab1619b 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -949,7 +949,7 @@ user space can read performance monitor counter registers directly. The default value is 0 (access disabled). -See Documentation/arm64/perf.rst for more information. +See Documentation/arch/arm64/perf.rst for more information. pid_max diff --git a/Documentation/arm64/acpi_object_usage.rst b/Documentation/arch/arm64/acpi_object_usage.rst similarity index 100% rename from Documentation/arm64/acpi_object_usage.rst rename to Documentation/arch/arm64/acpi_object_usage.rst diff --git a/Documentation/arm64/amu.rst b/Documentation/arch/arm64/amu.rst similarity index 100% rename from Documentation/arm64/amu.rst rename to Documentation/arch/arm64/amu.rst diff --git a/Documentation/arm64/arm-acpi.rst b/Documentation/arch/arm64/arm-acpi.rst similarity index 99% rename from Documentation/arm64/arm-acpi.rst rename to Documentation/arch/arm64/arm-acpi.rst index 47ecb9930dde..1636352756bb 100644 --- a/Documentation/arm64/arm-acpi.rst +++ b/Documentation/arch/arm64/arm-acpi.rst @@ -485,7 +485,7 @@ ACPI_OS_NAME ACPI Objects ------------ Detailed expectations for ACPI tables and object are listed in the file -Documentation/arm64/acpi_object_usage.rst. +Documentation/arch/arm64/acpi_object_usage.rst. References diff --git a/Documentation/arm64/asymmetric-32bit.rst b/Documentation/arch/arm64/asymmetric-32bit.rst similarity index 100% rename from Documentation/arm64/asymmetric-32bit.rst rename to Documentation/arch/arm64/asymmetric-32bit.rst diff --git a/Documentation/arm64/booting.rst b/Documentation/arch/arm64/booting.rst similarity index 100% rename from Documentation/arm64/booting.rst rename to Documentation/arch/arm64/booting.rst diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst similarity index 100% rename from Documentation/arm64/cpu-feature-registers.rst rename to Documentation/arch/arm64/cpu-feature-registers.rst diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst similarity index 96% rename from Documentation/arm64/elf_hwcaps.rst rename to Documentation/arch/arm64/elf_hwcaps.rst index 83e57e4d38e2..58a86d532228 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -102,7 +102,7 @@ HWCAP_ASIMDHP HWCAP_CPUID EL0 access to certain ID registers is available, to the extent - described by Documentation/arm64/cpu-feature-registers.rst. + described by Documentation/arch/arm64/cpu-feature-registers.rst. These ID registers may imply the availability of features. @@ -163,12 +163,12 @@ HWCAP_SB HWCAP_PACA Functionality implied by ID_AA64ISAR1_EL1.APA == 0b0001 or ID_AA64ISAR1_EL1.API == 0b0001, as described by - Documentation/arm64/pointer-authentication.rst. + Documentation/arch/arm64/pointer-authentication.rst. HWCAP_PACG Functionality implied by ID_AA64ISAR1_EL1.GPA == 0b0001 or ID_AA64ISAR1_EL1.GPI == 0b0001, as described by - Documentation/arm64/pointer-authentication.rst. + Documentation/arch/arm64/pointer-authentication.rst. HWCAP2_DCPODP Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010. @@ -226,7 +226,7 @@ HWCAP2_BTI HWCAP2_MTE Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described - by Documentation/arm64/memory-tagging-extension.rst. + by Documentation/arch/arm64/memory-tagging-extension.rst. HWCAP2_ECV Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. @@ -239,11 +239,11 @@ HWCAP2_RPRES HWCAP2_MTE3 Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described - by Documentation/arm64/memory-tagging-extension.rst. + by Documentation/arch/arm64/memory-tagging-extension.rst. HWCAP2_SME Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described - by Documentation/arm64/sme.rst. + by Documentation/arch/arm64/sme.rst. HWCAP2_SME_I16I64 Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111. diff --git a/Documentation/arm64/features.rst b/Documentation/arch/arm64/features.rst similarity index 100% rename from Documentation/arm64/features.rst rename to Documentation/arch/arm64/features.rst diff --git a/Documentation/arm64/hugetlbpage.rst b/Documentation/arch/arm64/hugetlbpage.rst similarity index 100% rename from Documentation/arm64/hugetlbpage.rst rename to Documentation/arch/arm64/hugetlbpage.rst diff --git a/Documentation/arm64/index.rst b/Documentation/arch/arm64/index.rst similarity index 100% rename from Documentation/arm64/index.rst rename to Documentation/arch/arm64/index.rst diff --git a/Documentation/arm64/kasan-offsets.sh b/Documentation/arch/arm64/kasan-offsets.sh similarity index 100% rename from Documentation/arm64/kasan-offsets.sh rename to Documentation/arch/arm64/kasan-offsets.sh diff --git a/Documentation/arm64/legacy_instructions.rst b/Documentation/arch/arm64/legacy_instructions.rst similarity index 100% rename from Documentation/arm64/legacy_instructions.rst rename to Documentation/arch/arm64/legacy_instructions.rst diff --git a/Documentation/arm64/memory-tagging-extension.rst b/Documentation/arch/arm64/memory-tagging-extension.rst similarity index 99% rename from Documentation/arm64/memory-tagging-extension.rst rename to Documentation/arch/arm64/memory-tagging-extension.rst index dbae47bba25e..679725030731 100644 --- a/Documentation/arm64/memory-tagging-extension.rst +++ b/Documentation/arch/arm64/memory-tagging-extension.rst @@ -221,7 +221,7 @@ programs should not retry in case of a non-zero system call return. ``NT_ARM_TAGGED_ADDR_CTRL`` allow ``ptrace()`` access to the tagged address ABI control and MTE configuration of a process as per the ``prctl()`` options described in -Documentation/arm64/tagged-address-abi.rst and above. The corresponding +Documentation/arch/arm64/tagged-address-abi.rst and above. The corresponding ``regset`` is 1 element of 8 bytes (``sizeof(long))``). Core dump support diff --git a/Documentation/arm64/memory.rst b/Documentation/arch/arm64/memory.rst similarity index 100% rename from Documentation/arm64/memory.rst rename to Documentation/arch/arm64/memory.rst diff --git a/Documentation/arm64/perf.rst b/Documentation/arch/arm64/perf.rst similarity index 100% rename from Documentation/arm64/perf.rst rename to Documentation/arch/arm64/perf.rst diff --git a/Documentation/arm64/pointer-authentication.rst b/Documentation/arch/arm64/pointer-authentication.rst similarity index 100% rename from Documentation/arm64/pointer-authentication.rst rename to Documentation/arch/arm64/pointer-authentication.rst diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst similarity index 100% rename from Documentation/arm64/silicon-errata.rst rename to Documentation/arch/arm64/silicon-errata.rst diff --git a/Documentation/arm64/sme.rst b/Documentation/arch/arm64/sme.rst similarity index 99% rename from Documentation/arm64/sme.rst rename to Documentation/arch/arm64/sme.rst index 1c43ea12eb4f..ba529a1dc606 100644 --- a/Documentation/arm64/sme.rst +++ b/Documentation/arch/arm64/sme.rst @@ -465,4 +465,4 @@ References [2] arch/arm64/include/uapi/asm/ptrace.h AArch64 Linux ptrace ABI definitions -[3] Documentation/arm64/cpu-feature-registers.rst +[3] Documentation/arch/arm64/cpu-feature-registers.rst diff --git a/Documentation/arm64/sve.rst b/Documentation/arch/arm64/sve.rst similarity index 99% rename from Documentation/arm64/sve.rst rename to Documentation/arch/arm64/sve.rst index 1b90a30382ac..0d9a426e9f85 100644 --- a/Documentation/arm64/sve.rst +++ b/Documentation/arch/arm64/sve.rst @@ -606,7 +606,7 @@ References [2] arch/arm64/include/uapi/asm/ptrace.h AArch64 Linux ptrace ABI definitions -[3] Documentation/arm64/cpu-feature-registers.rst +[3] Documentation/arch/arm64/cpu-feature-registers.rst [4] ARM IHI0055C http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf diff --git a/Documentation/arm64/tagged-address-abi.rst b/Documentation/arch/arm64/tagged-address-abi.rst similarity index 99% rename from Documentation/arm64/tagged-address-abi.rst rename to Documentation/arch/arm64/tagged-address-abi.rst index 540a1d4fc6c9..fe24a3f158c5 100644 --- a/Documentation/arm64/tagged-address-abi.rst +++ b/Documentation/arch/arm64/tagged-address-abi.rst @@ -107,7 +107,7 @@ following behaviours are guaranteed: A definition of the meaning of tagged pointers on AArch64 can be found -in Documentation/arm64/tagged-pointers.rst. +in Documentation/arch/arm64/tagged-pointers.rst. 3. AArch64 Tagged Address ABI Exceptions ----------------------------------------- diff --git a/Documentation/arm64/tagged-pointers.rst b/Documentation/arch/arm64/tagged-pointers.rst similarity index 98% rename from Documentation/arm64/tagged-pointers.rst rename to Documentation/arch/arm64/tagged-pointers.rst index 19d284b70384..81b6c2a770dd 100644 --- a/Documentation/arm64/tagged-pointers.rst +++ b/Documentation/arch/arm64/tagged-pointers.rst @@ -22,7 +22,7 @@ Passing tagged addresses to the kernel All interpretation of userspace memory addresses by the kernel assumes an address tag of 0x00, unless the application enables the AArch64 Tagged Address ABI explicitly -(Documentation/arm64/tagged-address-abi.rst). +(Documentation/arch/arm64/tagged-address-abi.rst). This includes, but is not limited to, addresses found in: diff --git a/Documentation/arch/index.rst b/Documentation/arch/index.rst index 80ee31016584..41cd957d53ea 100644 --- a/Documentation/arch/index.rst +++ b/Documentation/arch/index.rst @@ -11,7 +11,7 @@ implementation. arc/index ../arm/index - ../arm64/index + arm64/index ia64/index ../loongarch/index m68k/index diff --git a/Documentation/translations/zh_CN/arm64/amu.rst b/Documentation/translations/zh_CN/arch/arm64/amu.rst similarity index 97% rename from Documentation/translations/zh_CN/arm64/amu.rst rename to Documentation/translations/zh_CN/arch/arm64/amu.rst index ab7180f91394..f8e09fd21ef5 100644 --- a/Documentation/translations/zh_CN/arm64/amu.rst +++ b/Documentation/translations/zh_CN/arch/arm64/amu.rst @@ -1,6 +1,6 @@ -.. include:: ../disclaimer-zh_CN.rst +.. include:: ../../disclaimer-zh_CN.rst -:Original: :ref:`Documentation/arm64/amu.rst ` +:Original: :ref:`Documentation/arch/arm64/amu.rst ` Translator: Bailu Lin diff --git a/Documentation/translations/zh_CN/arm64/booting.txt b/Documentation/translations/zh_CN/arch/arm64/booting.txt similarity index 98% rename from Documentation/translations/zh_CN/arm64/booting.txt rename to Documentation/translations/zh_CN/arch/arm64/booting.txt index 5b0164132c71..630eb32a8854 100644 --- a/Documentation/translations/zh_CN/arm64/booting.txt +++ b/Documentation/translations/zh_CN/arch/arm64/booting.txt @@ -1,4 +1,4 @@ -Chinese translated version of Documentation/arm64/booting.rst +Chinese translated version of Documentation/arch/arm64/booting.rst If you have any comment or update to the content, please contact the original document maintainer directly. However, if you have a problem @@ -10,7 +10,7 @@ M: Will Deacon zh_CN: Fu Wei C: 55f058e7574c3615dea4615573a19bdb258696c6 --------------------------------------------------------------------- -Documentation/arm64/booting.rst 的中文翻译 +Documentation/arch/arm64/booting.rst 的中文翻译 如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 diff --git a/Documentation/translations/zh_CN/arm64/elf_hwcaps.rst b/Documentation/translations/zh_CN/arch/arm64/elf_hwcaps.rst similarity index 94% rename from Documentation/translations/zh_CN/arm64/elf_hwcaps.rst rename to Documentation/translations/zh_CN/arch/arm64/elf_hwcaps.rst index 9aa4637eac97..f60ac1580d3e 100644 --- a/Documentation/translations/zh_CN/arm64/elf_hwcaps.rst +++ b/Documentation/translations/zh_CN/arch/arm64/elf_hwcaps.rst @@ -1,6 +1,6 @@ -.. include:: ../disclaimer-zh_CN.rst +.. include:: ../../disclaimer-zh_CN.rst -:Original: :ref:`Documentation/arm64/elf_hwcaps.rst ` +:Original: :ref:`Documentation/arch/arm64/elf_hwcaps.rst ` Translator: Bailu Lin @@ -92,7 +92,7 @@ HWCAP_ASIMDHP ID_AA64PFR0_EL1.AdvSIMD == 0b0001 表示有此功能。 HWCAP_CPUID - 根据 Documentation/arm64/cpu-feature-registers.rst 描述，EL0 可以访问 + 根据 Documentation/arch/arm64/cpu-feature-registers.rst 描述，EL0 可以访问 某些 ID 寄存器。 这些 ID 寄存器可能表示功能的可用性。 @@ -152,12 +152,12 @@ HWCAP_SB ID_AA64ISAR1_EL1.SB == 0b0001 表示有此功能。 HWCAP_PACA - 如 Documentation/arm64/pointer-authentication.rst 所描述， + 如 Documentation/arch/arm64/pointer-authentication.rst 所描述， ID_AA64ISAR1_EL1.APA == 0b0001 或 ID_AA64ISAR1_EL1.API == 0b0001 表示有此功能。 HWCAP_PACG - 如 Documentation/arm64/pointer-authentication.rst 所描述， + 如 Documentation/arch/arm64/pointer-authentication.rst 所描述， ID_AA64ISAR1_EL1.GPA == 0b0001 或 ID_AA64ISAR1_EL1.GPI == 0b0001 表示有此功能。 diff --git a/Documentation/translations/zh_CN/arm64/hugetlbpage.rst b/Documentation/translations/zh_CN/arch/arm64/hugetlbpage.rst similarity index 91% rename from Documentation/translations/zh_CN/arm64/hugetlbpage.rst rename to Documentation/translations/zh_CN/arch/arm64/hugetlbpage.rst index 13304d269d0b..8079eadde29a 100644 --- a/Documentation/translations/zh_CN/arm64/hugetlbpage.rst +++ b/Documentation/translations/zh_CN/arch/arm64/hugetlbpage.rst @@ -1,6 +1,6 @@ -.. include:: ../disclaimer-zh_CN.rst +.. include:: ../../disclaimer-zh_CN.rst -:Original: :ref:`Documentation/arm64/hugetlbpage.rst ` +:Original: :ref:`Documentation/arch/arm64/hugetlbpage.rst ` Translator: Bailu Lin diff --git a/Documentation/translations/zh_CN/arm64/index.rst b/Documentation/translations/zh_CN/arch/arm64/index.rst similarity index 63% rename from Documentation/translations/zh_CN/arm64/index.rst rename to Documentation/translations/zh_CN/arch/arm64/index.rst index 57dc5de5ccc5..e12b9f6e5d6c 100644 --- a/Documentation/translations/zh_CN/arm64/index.rst +++ b/Documentation/translations/zh_CN/arch/arm64/index.rst @@ -1,6 +1,6 @@ -.. include:: ../disclaimer-zh_CN.rst +.. include:: ../../disclaimer-zh_CN.rst -:Original: :ref:`Documentation/arm64/index.rst ` +:Original: :ref:`Documentation/arch/arm64/index.rst ` :Translator: Bailu Lin .. _cn_arm64_index: diff --git a/Documentation/translations/zh_CN/arm64/legacy_instructions.txt b/Documentation/translations/zh_CN/arch/arm64/legacy_instructions.txt similarity index 95% rename from Documentation/translations/zh_CN/arm64/legacy_instructions.txt rename to Documentation/translations/zh_CN/arch/arm64/legacy_instructions.txt index e295cf75f606..e469fccbe356 100644 --- a/Documentation/translations/zh_CN/arm64/legacy_instructions.txt +++ b/Documentation/translations/zh_CN/arch/arm64/legacy_instructions.txt @@ -1,4 +1,4 @@ -Chinese translated version of Documentation/arm64/legacy_instructions.rst +Chinese translated version of Documentation/arch/arm64/legacy_instructions.rst If you have any comment or update to the content, please contact the original document maintainer directly. However, if you have a problem @@ -10,7 +10,7 @@ Maintainer: Punit Agrawal Suzuki K. Poulose Chinese maintainer: Fu Wei --------------------------------------------------------------------- -Documentation/arm64/legacy_instructions.rst 的中文翻译 +Documentation/arch/arm64/legacy_instructions.rst 的中文翻译 如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 diff --git a/Documentation/translations/zh_CN/arm64/memory.txt b/Documentation/translations/zh_CN/arch/arm64/memory.txt similarity index 97% rename from Documentation/translations/zh_CN/arm64/memory.txt rename to Documentation/translations/zh_CN/arch/arm64/memory.txt index be20f8228b91..c6962e9cb9f8 100644 --- a/Documentation/translations/zh_CN/arm64/memory.txt +++ b/Documentation/translations/zh_CN/arch/arm64/memory.txt @@ -1,4 +1,4 @@ -Chinese translated version of Documentation/arm64/memory.rst +Chinese translated version of Documentation/arch/arm64/memory.rst If you have any comment or update to the content, please contact the original document maintainer directly. However, if you have a problem @@ -9,7 +9,7 @@ or if there is a problem with the translation. Maintainer: Catalin Marinas Chinese maintainer: Fu Wei --------------------------------------------------------------------- -Documentation/arm64/memory.rst 的中文翻译 +Documentation/arch/arm64/memory.rst 的中文翻译 如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 diff --git a/Documentation/translations/zh_CN/arm64/perf.rst b/Documentation/translations/zh_CN/arch/arm64/perf.rst similarity index 96% rename from Documentation/translations/zh_CN/arm64/perf.rst rename to Documentation/translations/zh_CN/arch/arm64/perf.rst index 9bf21d73f4d1..6be72704e659 100644 --- a/Documentation/translations/zh_CN/arm64/perf.rst +++ b/Documentation/translations/zh_CN/arch/arm64/perf.rst @@ -1,8 +1,8 @@ .. SPDX-License-Identifier: GPL-2.0 -.. include:: ../disclaimer-zh_CN.rst +.. include:: ../../disclaimer-zh_CN.rst -:Original: :ref:`Documentation/arm64/perf.rst ` +:Original: :ref:`Documentation/arch/arm64/perf.rst ` Translator: Bailu Lin diff --git a/Documentation/translations/zh_CN/arm64/silicon-errata.txt b/Documentation/translations/zh_CN/arch/arm64/silicon-errata.txt similarity index 97% rename from Documentation/translations/zh_CN/arm64/silicon-errata.txt rename to Documentation/translations/zh_CN/arch/arm64/silicon-errata.txt index 440c59ac7dce..f4767ffdd61d 100644 --- a/Documentation/translations/zh_CN/arm64/silicon-errata.txt +++ b/Documentation/translations/zh_CN/arch/arm64/silicon-errata.txt @@ -1,4 +1,4 @@ -Chinese translated version of Documentation/arm64/silicon-errata.rst +Chinese translated version of Documentation/arch/arm64/silicon-errata.rst If you have any comment or update to the content, please contact the original document maintainer directly. However, if you have a problem @@ -10,7 +10,7 @@ M: Will Deacon zh_CN: Fu Wei C: 1926e54f115725a9248d0c4c65c22acaf94de4c4 --------------------------------------------------------------------- -Documentation/arm64/silicon-errata.rst 的中文翻译 +Documentation/arch/arm64/silicon-errata.rst 的中文翻译 如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 diff --git a/Documentation/translations/zh_CN/arm64/tagged-pointers.txt b/Documentation/translations/zh_CN/arch/arm64/tagged-pointers.txt similarity index 94% rename from Documentation/translations/zh_CN/arm64/tagged-pointers.txt rename to Documentation/translations/zh_CN/arch/arm64/tagged-pointers.txt index 77ac3548a16d..27577c3c5e3f 100644 --- a/Documentation/translations/zh_CN/arm64/tagged-pointers.txt +++ b/Documentation/translations/zh_CN/arch/arm64/tagged-pointers.txt @@ -1,4 +1,4 @@ -Chinese translated version of Documentation/arm64/tagged-pointers.rst +Chinese translated version of Documentation/arch/arm64/tagged-pointers.rst If you have any comment or update to the content, please contact the original document maintainer directly. However, if you have a problem @@ -9,7 +9,7 @@ or if there is a problem with the translation. Maintainer: Will Deacon Chinese maintainer: Fu Wei --------------------------------------------------------------------- -Documentation/arm64/tagged-pointers.rst 的中文翻译 +Documentation/arch/arm64/tagged-pointers.rst 的中文翻译 如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 diff --git a/Documentation/translations/zh_CN/arch/index.rst b/Documentation/translations/zh_CN/arch/index.rst index 908ea131bb1c..6fa0cb671009 100644 --- a/Documentation/translations/zh_CN/arch/index.rst +++ b/Documentation/translations/zh_CN/arch/index.rst @@ -9,7 +9,7 @@ :maxdepth: 2 ../mips/index - ../arm64/index + arm64/index ../riscv/index openrisc/index parisc/index diff --git a/Documentation/translations/zh_TW/arm64/amu.rst b/Documentation/translations/zh_TW/arch/arm64/amu.rst similarity index 97% rename from Documentation/translations/zh_TW/arm64/amu.rst rename to Documentation/translations/zh_TW/arch/arm64/amu.rst index ffdc466e0f62..f947a6c7369f 100644 --- a/Documentation/translations/zh_TW/arm64/amu.rst +++ b/Documentation/translations/zh_TW/arch/arm64/amu.rst @@ -1,8 +1,8 @@ .. SPDX-License-Identifier: GPL-2.0 -.. include:: ../disclaimer-zh_TW.rst +.. include:: ../../disclaimer-zh_TW.rst -:Original: :ref:`Documentation/arm64/amu.rst ` +:Original: :ref:`Documentation/arch/arm64/amu.rst ` Translator: Bailu Lin Hu Haowen diff --git a/Documentation/translations/zh_TW/arm64/booting.txt b/Documentation/translations/zh_TW/arch/arm64/booting.txt similarity index 98% rename from Documentation/translations/zh_TW/arm64/booting.txt rename to Documentation/translations/zh_TW/arch/arm64/booting.txt index b9439dd54012..24817b8b70cd 100644 --- a/Documentation/translations/zh_TW/arm64/booting.txt +++ b/Documentation/translations/zh_TW/arch/arm64/booting.txt @@ -1,6 +1,6 @@ SPDX-License-Identifier: GPL-2.0 -Chinese translated version of Documentation/arm64/booting.rst +Chinese translated version of Documentation/arch/arm64/booting.rst If you have any comment or update to the content, please contact the original document maintainer directly. However, if you have a problem @@ -13,7 +13,7 @@ zh_CN: Fu Wei zh_TW: Hu Haowen C: 55f058e7574c3615dea4615573a19bdb258696c6 --------------------------------------------------------------------- -Documentation/arm64/booting.rst 的中文翻譯 +Documentation/arch/arm64/booting.rst 的中文翻譯 如果想評論或更新本文的內容，請直接聯繫原文檔的維護者。如果你使用英文 交流有困難的話，也可以向中文版維護者求助。如果本翻譯更新不及時或者翻 diff --git a/Documentation/translations/zh_TW/arm64/elf_hwcaps.rst b/Documentation/translations/zh_TW/arch/arm64/elf_hwcaps.rst similarity index 94% rename from Documentation/translations/zh_TW/arm64/elf_hwcaps.rst rename to Documentation/translations/zh_TW/arch/arm64/elf_hwcaps.rst index 3eb1c623ce31..fca3c6ff7b93 100644 --- a/Documentation/translations/zh_TW/arm64/elf_hwcaps.rst +++ b/Documentation/translations/zh_TW/arch/arm64/elf_hwcaps.rst @@ -1,8 +1,8 @@ .. SPDX-License-Identifier: GPL-2.0 -.. include:: ../disclaimer-zh_TW.rst +.. include:: ../../disclaimer-zh_TW.rst -:Original: :ref:`Documentation/arm64/elf_hwcaps.rst ` +:Original: :ref:`Documentation/arch/arm64/elf_hwcaps.rst ` Translator: Bailu Lin Hu Haowen @@ -95,7 +95,7 @@ HWCAP_ASIMDHP ID_AA64PFR0_EL1.AdvSIMD == 0b0001 表示有此功能。 HWCAP_CPUID - 根據 Documentation/arm64/cpu-feature-registers.rst 描述，EL0 可以訪問 + 根據 Documentation/arch/arm64/cpu-feature-registers.rst 描述，EL0 可以訪問 某些 ID 寄存器。 這些 ID 寄存器可能表示功能的可用性。 @@ -155,12 +155,12 @@ HWCAP_SB ID_AA64ISAR1_EL1.SB == 0b0001 表示有此功能。 HWCAP_PACA - 如 Documentation/arm64/pointer-authentication.rst 所描述， + 如 Documentation/arch/arm64/pointer-authentication.rst 所描述， ID_AA64ISAR1_EL1.APA == 0b0001 或 ID_AA64ISAR1_EL1.API == 0b0001 表示有此功能。 HWCAP_PACG - 如 Documentation/arm64/pointer-authentication.rst 所描述， + 如 Documentation/arch/arm64/pointer-authentication.rst 所描述， ID_AA64ISAR1_EL1.GPA == 0b0001 或 ID_AA64ISAR1_EL1.GPI == 0b0001 表示有此功能。 diff --git a/Documentation/translations/zh_TW/arm64/hugetlbpage.rst b/Documentation/translations/zh_TW/arch/arm64/hugetlbpage.rst similarity index 91% rename from Documentation/translations/zh_TW/arm64/hugetlbpage.rst rename to Documentation/translations/zh_TW/arch/arm64/hugetlbpage.rst index 846b500dae97..10feb329dfb8 100644 --- a/Documentation/translations/zh_TW/arm64/hugetlbpage.rst +++ b/Documentation/translations/zh_TW/arch/arm64/hugetlbpage.rst @@ -1,8 +1,8 @@ .. SPDX-License-Identifier: GPL-2.0 -.. include:: ../disclaimer-zh_TW.rst +.. include:: ../../disclaimer-zh_TW.rst -:Original: :ref:`Documentation/arm64/hugetlbpage.rst ` +:Original: :ref:`Documentation/arch/arm64/hugetlbpage.rst ` Translator: Bailu Lin Hu Haowen diff --git a/Documentation/translations/zh_TW/arm64/index.rst b/Documentation/translations/zh_TW/arch/arm64/index.rst similarity index 71% rename from Documentation/translations/zh_TW/arm64/index.rst rename to Documentation/translations/zh_TW/arch/arm64/index.rst index 2322783f3881..68befee14b99 100644 --- a/Documentation/translations/zh_TW/arm64/index.rst +++ b/Documentation/translations/zh_TW/arch/arm64/index.rst @@ -1,8 +1,8 @@ .. SPDX-License-Identifier: GPL-2.0 -.. include:: ../disclaimer-zh_TW.rst +.. include:: ../../disclaimer-zh_TW.rst -:Original: :ref:`Documentation/arm64/index.rst ` +:Original: :ref:`Documentation/arch/arm64/index.rst ` :Translator: Bailu Lin Hu Haowen diff --git a/Documentation/translations/zh_TW/arm64/legacy_instructions.txt b/Documentation/translations/zh_TW/arch/arm64/legacy_instructions.txt similarity index 96% rename from Documentation/translations/zh_TW/arm64/legacy_instructions.txt rename to Documentation/translations/zh_TW/arch/arm64/legacy_instructions.txt index 6d4454f77b9e..3c915df9836c 100644 --- a/Documentation/translations/zh_TW/arm64/legacy_instructions.txt +++ b/Documentation/translations/zh_TW/arch/arm64/legacy_instructions.txt @@ -1,6 +1,6 @@ SPDX-License-Identifier: GPL-2.0 -Chinese translated version of Documentation/arm64/legacy_instructions.rst +Chinese translated version of Documentation/arch/arm64/legacy_instructions.rst If you have any comment or update to the content, please contact the original document maintainer directly. However, if you have a problem @@ -13,7 +13,7 @@ Maintainer: Punit Agrawal Chinese maintainer: Fu Wei Traditional Chinese maintainer: Hu Haowen --------------------------------------------------------------------- -Documentation/arm64/legacy_instructions.rst 的中文翻譯 +Documentation/arch/arm64/legacy_instructions.rst 的中文翻譯 如果想評論或更新本文的內容，請直接聯繫原文檔的維護者。如果你使用英文 交流有困難的話，也可以向中文版維護者求助。如果本翻譯更新不及時或者翻 diff --git a/Documentation/translations/zh_TW/arm64/memory.txt b/Documentation/translations/zh_TW/arch/arm64/memory.txt similarity index 97% rename from Documentation/translations/zh_TW/arm64/memory.txt rename to Documentation/translations/zh_TW/arch/arm64/memory.txt index 99c2b78b5674..2437380a26d8 100644 --- a/Documentation/translations/zh_TW/arm64/memory.txt +++ b/Documentation/translations/zh_TW/arch/arm64/memory.txt @@ -1,6 +1,6 @@ SPDX-License-Identifier: GPL-2.0 -Chinese translated version of Documentation/arm64/memory.rst +Chinese translated version of Documentation/arch/arm64/memory.rst If you have any comment or update to the content, please contact the original document maintainer directly. However, if you have a problem @@ -12,7 +12,7 @@ Maintainer: Catalin Marinas Chinese maintainer: Fu Wei Traditional Chinese maintainer: Hu Haowen --------------------------------------------------------------------- -Documentation/arm64/memory.rst 的中文翻譯 +Documentation/arch/arm64/memory.rst 的中文翻譯 如果想評論或更新本文的內容，請直接聯繫原文檔的維護者。如果你使用英文 交流有困難的話，也可以向中文版維護者求助。如果本翻譯更新不及時或者翻 diff --git a/Documentation/translations/zh_TW/arm64/perf.rst b/Documentation/translations/zh_TW/arch/arm64/perf.rst similarity index 96% rename from Documentation/translations/zh_TW/arm64/perf.rst rename to Documentation/translations/zh_TW/arch/arm64/perf.rst index f1ffd55dfe50..3b39997a52eb 100644 --- a/Documentation/translations/zh_TW/arm64/perf.rst +++ b/Documentation/translations/zh_TW/arch/arm64/perf.rst @@ -1,8 +1,8 @@ .. SPDX-License-Identifier: GPL-2.0 -.. include:: ../disclaimer-zh_TW.rst +.. include:: ../../disclaimer-zh_TW.rst -:Original: :ref:`Documentation/arm64/perf.rst ` +:Original: :ref:`Documentation/arch/arm64/perf.rst ` Translator: Bailu Lin Hu Haowen diff --git a/Documentation/translations/zh_TW/arm64/silicon-errata.txt b/Documentation/translations/zh_TW/arch/arm64/silicon-errata.txt similarity index 97% rename from Documentation/translations/zh_TW/arm64/silicon-errata.txt rename to Documentation/translations/zh_TW/arch/arm64/silicon-errata.txt index bf2077197504..66c3a3506458 100644 --- a/Documentation/translations/zh_TW/arm64/silicon-errata.txt +++ b/Documentation/translations/zh_TW/arch/arm64/silicon-errata.txt @@ -1,6 +1,6 @@ SPDX-License-Identifier: GPL-2.0 -Chinese translated version of Documentation/arm64/silicon-errata.rst +Chinese translated version of Documentation/arch/arm64/silicon-errata.rst If you have any comment or update to the content, please contact the original document maintainer directly. However, if you have a problem @@ -13,7 +13,7 @@ zh_CN: Fu Wei zh_TW: Hu Haowen C: 1926e54f115725a9248d0c4c65c22acaf94de4c4 --------------------------------------------------------------------- -Documentation/arm64/silicon-errata.rst 的中文翻譯 +Documentation/arch/arm64/silicon-errata.rst 的中文翻譯 如果想評論或更新本文的內容，請直接聯繫原文檔的維護者。如果你使用英文 交流有困難的話，也可以向中文版維護者求助。如果本翻譯更新不及時或者翻 diff --git a/Documentation/translations/zh_TW/arm64/tagged-pointers.txt b/Documentation/translations/zh_TW/arch/arm64/tagged-pointers.txt similarity index 95% rename from Documentation/translations/zh_TW/arm64/tagged-pointers.txt rename to Documentation/translations/zh_TW/arch/arm64/tagged-pointers.txt index 87f88628401a..b7f683f20ed1 100644 --- a/Documentation/translations/zh_TW/arm64/tagged-pointers.txt +++ b/Documentation/translations/zh_TW/arch/arm64/tagged-pointers.txt @@ -1,6 +1,6 @@ SPDX-License-Identifier: GPL-2.0 -Chinese translated version of Documentation/arm64/tagged-pointers.rst +Chinese translated version of Documentation/arch/arm64/tagged-pointers.rst If you have any comment or update to the content, please contact the original document maintainer directly. However, if you have a problem @@ -12,7 +12,7 @@ Maintainer: Will Deacon Chinese maintainer: Fu Wei Traditional Chinese maintainer: Hu Haowen --------------------------------------------------------------------- -Documentation/arm64/tagged-pointers.rst 的中文翻譯 +Documentation/arch/arm64/tagged-pointers.rst 的中文翻譯 如果想評論或更新本文的內容，請直接聯繫原文檔的維護者。如果你使用英文 交流有困難的話，也可以向中文版維護者求助。如果本翻譯更新不及時或者翻 diff --git a/Documentation/translations/zh_TW/index.rst b/Documentation/translations/zh_TW/index.rst index e97d7d578751..e7c83868e780 100644 --- a/Documentation/translations/zh_TW/index.rst +++ b/Documentation/translations/zh_TW/index.rst @@ -150,7 +150,7 @@ TODOList: .. toctree:: :maxdepth: 2 - arm64/index + arch/arm64/index TODOList: diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index add067793b90..96c4475539c2 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -2613,7 +2613,7 @@ follows:: this vcpu, and determines which register slices are visible through this ioctl interface. -(See Documentation/arm64/sve.rst for an explanation of the "vq" +(See Documentation/arch/arm64/sve.rst for an explanation of the "vq" nomenclature.) KVM_REG_ARM64_SVE_VLS is only accessible after KVM_ARM_VCPU_INIT. diff --git a/MAINTAINERS b/MAINTAINERS index f794002a192e..09d5b6b58ebb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3062,7 +3062,7 @@ M: Will Deacon L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git -F: Documentation/arm64/ +F: Documentation/arch/arm64/ F: arch/arm64/ F: tools/testing/selftests/arm64/ X: arch/arm64/boot/dts/ From patchwork Tue Jun 13 09:46:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Corbet X-Patchwork-Id: 107230 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp425045vqr; Tue, 13 Jun 2023 03:01:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ74AVVrivcstcNSdZhifkuGEzUH0Zcnm7cRu3zE1OQptSrC9TV5q4AI7DPKbUCoeaCPmNO2 X-Received: by 2002:aa7:d712:0:b0:518:7959:e10 with SMTP id t18-20020aa7d712000000b0051879590e10mr788138edq.22.1686650506177; Tue, 13 Jun 2023 03:01:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686650506; cv=none; d=google.com; s=arc-20160816; b=WnPN3lTi0/M8ViXEgu498ui6aR21NyPEARLkMi8RvjupCAo8MG6O0HQ36ZwGegHJnn EQOwOfG6GvnLr0tPoKjE326ZYDRugCR5w2WNGiz4lIEuF/ghKcfswT7kb7zlRako2Ods H5+b4OxjeMTMQXNBvTBU0OYUtMyjnbUK7lara2NHTavxFLWprJp59WL+YPo5p7hD9Gl0 kxaOvlA/DluSx3jsknDc9d55gbQ7oaOcjZpT1ZjRsL+BHEKio8TDCHku0Utz8ex1J9Pe cA7TjFO2oIfm0aKcc3lKSTorjddE7HERj0t9TSmNpSnUhtEfuy/IP11UyaUieSdZnN+v 5Zgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=3D+PguzS4TXh42c031J2y3Uw3/ednR923UHurOmvS98=; b=gMseCAaAfw3OmGXQ9ke+Fe3hKVcT2MvAj8DFq/hIKB1WCq8Zl295bKslITSsMDzv5Y hjzXgt/qaV9x2GzoaVxUjBj7+v+kjyS4R7p3ixaLycYD5D/C6NXQm57ZpYgbZuzbFqG0 WJrTquut1SDl70hGxoSJhVgOUXH2tOnmZVnnXUnZBBbxq7KcxyfsK7TCoW2Gf1FN7TKk WLmbcPw9FidUvH72bjtNEKPF5oimeqAkLUCDj2139bI68wKYgdWuwlxrYyLkL9M36jTU /8LUFe7MpmFIlP2wfN4N2FdsnXQfDx446sUAIRVsBaol3coptegj13X0TL4wkz8T8zaZ i70A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lwn.net header.s=20201203 header.b=qZK1PnYZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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(mdns.lwn.net [45.79.72.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ms.lwn.net (Postfix) with ESMTPSA id 95F6F77D; Tue, 13 Jun 2023 09:46:26 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 ms.lwn.net 95F6F77D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lwn.net; s=20201203; t=1686649589; bh=3D+PguzS4TXh42c031J2y3Uw3/ednR923UHurOmvS98=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qZK1PnYZqJpWnDb1BSqQeus2JOzvGlw0lv0mFoOldcSwZ2HlRxG2iVmKzOv7B8rJO Frfx5gDenDIsj4z499uG9oZBqNKntl9huHJpAG5UE3jY32YW25adiDJ3Utx77Tudp7 KG9jSVWctMFERne2ze86WUfNPep0OwOdbpsNJwact6FCyweg+d98yyuLLD5csR4q5m GOpcDJOLU8W3sdmjcsuO9XaGsYhxTp7qanblBFINo55O3VxTybgFVtqKZBnOv+7Zgs 86GnXk8mLmPNZlqlePoUQasPnbTwc7RoCEHDLqjjYIyH4OOWF9ypifi0jcjKMFcgCQ Ik+GvOcEj35dg== From: Jonathan Corbet To: linux-doc@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonathan Corbet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org Subject: [PATCH 2/5] dt-bindings: fix dangling Documentation/arm64 reference Date: Tue, 13 Jun 2023 03:46:03 -0600 Message-Id: <20230613094606.334687-3-corbet@lwn.net> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613094606.334687-1-corbet@lwn.net> References: <20230613094606.334687-1-corbet@lwn.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768581240894435072?= X-GMAIL-MSGID: =?utf-8?q?1768581240894435072?= The arm64 documentation has move under Documentation/arch/ fix a reference to match. Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: devicetree@vger.kernel.org Signed-off-by: Jonathan Corbet Acked-by: Rob Herring Acked-by: Catalin Marinas --- Documentation/devicetree/bindings/cpu/idle-states.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/cpu/idle-states.yaml b/Documentation/devicetree/bindings/cpu/idle-states.yaml index b8cc826c9501..b3a5356f9916 100644 --- a/Documentation/devicetree/bindings/cpu/idle-states.yaml +++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml @@ -259,7 +259,7 @@ description: |+ http://infocenter.arm.com/help/index.jsp [5] ARM Linux Kernel documentation - Booting AArch64 Linux - Documentation/arm64/booting.rst + Documentation/arch/arm64/booting.rst [6] RISC-V Linux Kernel documentation - CPUs bindings Documentation/devicetree/bindings/riscv/cpus.yaml From patchwork Tue Jun 13 09:46:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Corbet X-Patchwork-Id: 107232 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp425971vqr; Tue, 13 Jun 2023 03:03:03 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6rGL+F7jhrOFF2TyezdoPDcHS0kYPGrRxZRSjZ+r3f+j93XkFC/JTEzt9ZXA/1iqe5nxLS X-Received: by 2002:a05:6a20:7350:b0:10d:5430:c8d6 with SMTP id v16-20020a056a20735000b0010d5430c8d6mr15037771pzc.0.1686650583617; Tue, 13 Jun 2023 03:03:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686650583; cv=none; d=google.com; s=arc-20160816; b=TiIYft+E5yzbsVdDlHwUJf6ca/z8mh0BpDI6wBFk2z1mAeEnxKpsEZD6J+RUwLWvA0 H4xjGvJeAh9Bywn5QExQnpCsfUJLkUR4HvqJatmwECidJnWwi3VK8xQykGJ37xS4K4ww 9XYT/MJp+nD+1pBoyDNuZ210MJpjqciVcjTdhsnwt8g61J69C8rAOEZHUzB+olQPJbhj 58qkUC0wMAcoLs67ZJ2Adyh9uliBpJ+QLr90yayVgdZcz6u7HCQpqDSEy2WaKVUzqj8y lGSm+7o8LHOEDqO49aPAGowvNe957v3T0TD206loT/0ZuoKEWpMlCJ56HeNFYE4wuopg pJ9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=SIo3Mnk6Ywbt2c5vULeGDpc0VLDRElbeGEbpt5REm0M=; b=T+dCpMuy2QeWAxY7DjVrweR+V/GxNvBARpOTGXFB2xly3HFzTizBe/wpnePUTdRVkq j13pN73xSfUg/T0rQHimHLTc8/Pkh/ZzPsY1zv7Cm/bfS1NnunEp2umb8M0QdEmX6sV/ 681tu+QaAr3msTU406h1kQktWU6s/LFIKBP7bEamLiIprp3pKJHsfTX0WKM4Hdns368F zibkOyTRoP+fihUu1WbB7Iw9zfDEY3A3tb3PCzrG/0C/+Kv96IkeN7NcutVtOqhd/rPJ 49K5gP17DGKML8KkZBtuBkoD6isg0Jn4T0+qodzVLOt2batHW7uNiHlYmb1NfwNvgPD6 1ZOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lwn.net header.s=20201203 header.b=MYSICFID; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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(mdns.lwn.net [45.79.72.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ms.lwn.net (Postfix) with ESMTPSA id 1FD9A6A2; Tue, 13 Jun 2023 09:46:29 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 ms.lwn.net 1FD9A6A2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lwn.net; s=20201203; t=1686649592; bh=SIo3Mnk6Ywbt2c5vULeGDpc0VLDRElbeGEbpt5REm0M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MYSICFIDkLND6EiVNDVOqwDb0Ai5y17oxI8ZflQBZdQ7r15NwpBGXY2l0KLRPsiIF /FBCbEZYkD9GJTWlV8XrqufGS8LS0IH75DQ5zmHRv9/2ET3Ak1AqQBpy22sxDT19m+ NlpXLApGJNpN7U0MpQ6/xNpWDyECTx9SrLFFuNhY7tREQAigINbXA8ixpMjuguYfVB fxWZzAJMKVJCZ5v2ZbK3SfH+1+8g0XtxJi0BCojf3bM+/9HlQHfnghsyV/2BSKDAIr spPzBGPVjTut9fVPa6/dIdjX6e4EWhkq/3dV7slwft/kz/MR3mhXx0KlV9plCTF0pf K3tct3DON0nLw== From: Jonathan Corbet To: linux-doc@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonathan Corbet , Catalin Marinas , Will Deacon , Ard Biesheuvel , linux-efi@vger.kernel.org Subject: [PATCH 3/5] arm64: Fix dangling references to Documentation/arm64 Date: Tue, 13 Jun 2023 03:46:04 -0600 Message-Id: <20230613094606.334687-4-corbet@lwn.net> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613094606.334687-1-corbet@lwn.net> References: <20230613094606.334687-1-corbet@lwn.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768581322527216221?= X-GMAIL-MSGID: =?utf-8?q?1768581322527216221?= The arm64 documentation has moved under Documentation/arch/; fix up references in the arm64 subtree to match. Cc: Catalin Marinas Cc: Will Deacon Cc: Ard Biesheuvel Cc: linux-efi@vger.kernel.org Signed-off-by: Jonathan Corbet Acked-by: Catalin Marinas --- arch/arm64/Kconfig | 4 ++-- arch/arm64/include/asm/efi.h | 2 +- arch/arm64/include/asm/image.h | 2 +- arch/arm64/include/uapi/asm/sigcontext.h | 2 +- arch/arm64/kernel/kexec_image.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 343e1e1cae10..1746ac824b91 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1585,7 +1585,7 @@ config ARM64_TAGGED_ADDR_ABI When this option is enabled, user applications can opt in to a relaxed ABI via prctl() allowing tagged addresses to be passed to system calls as pointer arguments. For details, see - Documentation/arm64/tagged-address-abi.rst. + Documentation/arch/arm64/tagged-address-abi.rst. menuconfig COMPAT bool "Kernel support for 32-bit EL0" @@ -2047,7 +2047,7 @@ config ARM64_MTE explicitly opt in. The mechanism for the userspace is described in: - Documentation/arm64/memory-tagging-extension.rst. + Documentation/arch/arm64/memory-tagging-extension.rst. endmenu # "ARMv8.5 architectural features" diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index f86b157a5da3..ca3f72476c29 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -88,7 +88,7 @@ efi_status_t __efi_rt_asm_wrapper(void *, const char *, ...); * guaranteed to cover the kernel Image. * * Since the EFI stub is part of the kernel Image, we can relax the - * usual requirements in Documentation/arm64/booting.rst, which still + * usual requirements in Documentation/arch/arm64/booting.rst, which still * apply to other bootloaders, and are required for some kernel * configurations. */ diff --git a/arch/arm64/include/asm/image.h b/arch/arm64/include/asm/image.h index c2b13213c720..c09cf942dc92 100644 --- a/arch/arm64/include/asm/image.h +++ b/arch/arm64/include/asm/image.h @@ -27,7 +27,7 @@ /* * struct arm64_image_header - arm64 kernel image header - * See Documentation/arm64/booting.rst for details + * See Documentation/arch/arm64/booting.rst for details * * @code0: Executable code, or * @mz_header alternatively used for part of MZ header diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h index 656a10ea6c67..f23c1dc3f002 100644 --- a/arch/arm64/include/uapi/asm/sigcontext.h +++ b/arch/arm64/include/uapi/asm/sigcontext.h @@ -177,7 +177,7 @@ struct zt_context { * vector length beyond its initial architectural limit of 2048 bits * (16 quadwords). * - * See linux/Documentation/arm64/sve.rst for a description of the VL/VQ + * See linux/Documentation/arch/arm64/sve.rst for a description of the VL/VQ * terminology. */ #define SVE_VQ_BYTES __SVE_VQ_BYTES /* bytes per quadword */ diff --git a/arch/arm64/kernel/kexec_image.c b/arch/arm64/kernel/kexec_image.c index 5ed6a585f21f..636be6715155 100644 --- a/arch/arm64/kernel/kexec_image.c +++ b/arch/arm64/kernel/kexec_image.c @@ -48,7 +48,7 @@ static void *image_load(struct kimage *image, /* * We require a kernel with an unambiguous Image header. Per - * Documentation/arm64/booting.rst, this is the case when image_size + * Documentation/arch/arm64/booting.rst, this is the case when image_size * is non-zero (practically speaking, since v3.17). */ h = (struct arm64_image_header *)kernel; From patchwork Tue Jun 13 09:46:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Corbet X-Patchwork-Id: 107223 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp423345vqr; Tue, 13 Jun 2023 02:59:18 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6nbLo7Pe81DHv9OBKF3IYRafk97WRcGl+mBOYLeil9wBsDGlD1WTlQxpeTvmqbOFc7ZlZg X-Received: by 2002:a92:d290:0:b0:340:5a22:d16a with SMTP id p16-20020a92d290000000b003405a22d16amr2446463ilp.26.1686650358473; Tue, 13 Jun 2023 02:59:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686650358; cv=none; d=google.com; s=arc-20160816; b=V2icpMAys31bcfPyzuJzlIrfWklByUhl51lCGltrQ9ZRh//5dMEjH9cKrHWgOce1FA VchGmsmM9PP9q6PJowPMITPjfp7ba5rqs5rf6r9DrcQ6GV4Z7OhZVTCm5PZkDbHbyuaB 7W+kYHSYVyJGeBjmIX3X2O6+ZyzFxsr2e5uyxIF0JNtzMVDyy7Ox8vMOLudyvWjMr2pT 0L+pSgePWhF2KJttyV5NY/uarAUUYUaeeVmteUY9z9ImICEXkpVVpKA2+ec+48dxzHvR 0tuobIuoWtpW5vMrFgQm5ZyyjRQd96sPuyda6sm/OljGH5ALsUamGico/QPuLjA4sWvV LxWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=Qo56z2IvRa1HAZxuU6eMDg1Xfv7BI9bYCGhGj0/XqOw=; b=nR2+fRoMJYnJ9G0Gq3bNpjyacDxRRxiSYMhNvpVlbKhBZv9do2qimO7pNpfSQqH0o0 d5Vo6eNam2JKHHurSyRvbULPleVQiHrQVQfKK5m92RO33lKoZqRjLAsBV6drMkoBY78W em5gklIW88nzx/liDpks3cErS+ktNeqZHoTgbq3CAnqFeVJz0+IDYHadgja+JI9A0ROJ B3mFnG4YFY7+3PL5qTMSn2gFgDvj83M/zHGY6eO67YcolHiliaFYLWt4zl0qhRE32Qkk uIzzXXyHiw3y3OrlZkfoctvNYZybNuY+hMUXgYstTtFiYpVdnunxSmrD2+/5zCNuu2sS dp/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lwn.net header.s=20201203 header.b=HrFfniOx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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(mdns.lwn.net [45.79.72.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ms.lwn.net (Postfix) with ESMTPSA id 4BC2B7F9; Tue, 13 Jun 2023 09:46:33 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 ms.lwn.net 4BC2B7F9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lwn.net; s=20201203; t=1686649595; bh=Qo56z2IvRa1HAZxuU6eMDg1Xfv7BI9bYCGhGj0/XqOw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HrFfniOxN0lBlCMP4QkQ10hFTpkRtQrGkV8gySbd60OM/ZLQpGreJPgNE9dc0Vn5K vGAG1hPmQF041iw8dCOJ6KJwV/siHs2e/A4rcuF15GeyzckbCrQWkEmlvwcMnI9K6+ S1he/jR97oGDDA8l/IHFf8lq4bNN3XllIhXnsLADD/shOc66q+N+roOBYfl/6UoHN0 b59h6QSkN4E3xIkeAex1eFbiQ+S5DWKXL8vmylD8HomUBfk3JzEKpllXFp1NuDl0y9 DMxPmg9J4Nge1TmjIZKb6CM+jFiFgnwUT1JIKbq60+OC4HtGWIaXPQvU7aiL/TPu4G PbRtXJYZb5rPg== From: Jonathan Corbet To: linux-doc@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonathan Corbet , Andrew Morton , linux-mm@kvack.org Subject: [PATCH 4/5] mm: Fix a dangling Documentation/arm64 reference Date: Tue, 13 Jun 2023 03:46:05 -0600 Message-Id: <20230613094606.334687-5-corbet@lwn.net> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613094606.334687-1-corbet@lwn.net> References: <20230613094606.334687-1-corbet@lwn.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768581086236550593?= X-GMAIL-MSGID: =?utf-8?q?1768581086236550593?= The arm64 documentation has moved under Documentation/arch/. Fix up a reference in mm/mremap.c to match. Cc: Andrew Morton Cc: linux-mm@kvack.org Signed-off-by: Jonathan Corbet Acked-by: Mike Rapoport (IBM) Acked-by: Catalin Marinas --- mm/mremap.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/mm/mremap.c b/mm/mremap.c index b11ce6c92099..3185724d8b13 100644 --- a/mm/mremap.c +++ b/mm/mremap.c @@ -914,7 +914,8 @@ SYSCALL_DEFINE5(mremap, unsigned long, addr, unsigned long, old_len, * mapping address intact. A non-zero tag will cause the subsequent * range checks to reject the address as invalid. * - * See Documentation/arm64/tagged-address-abi.rst for more information. + * See Documentation/arch/arm64/tagged-address-abi.rst for more + * information. */ addr = untagged_addr(addr); From patchwork Tue Jun 13 09:46:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Corbet X-Patchwork-Id: 107229 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp425033vqr; Tue, 13 Jun 2023 03:01:45 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6v7XXxsLnuBDnADjOnTNYLRVTpOWqRg3MpQSSROVCDj3F5Wq/bz7lbscmBjf0dYHL/w9ra X-Received: by 2002:a05:6870:1986:b0:19a:1571:f9dc with SMTP id v6-20020a056870198600b0019a1571f9dcmr8501464oam.49.1686650505176; Tue, 13 Jun 2023 03:01:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686650505; cv=none; d=google.com; s=arc-20160816; b=RXNXn92jJmE0E7NorjYAQh/+9XnTDvwjloAN2yQthfXS0M2H4/zT9yILVvpS9Xdkgr PPg0xR9mPq+KrQy7LrLABPgJxnkQDTCm+ZNvOvWR0pOopWFrtaAl9WnEpkGUHBgH2J/O XvWdiwkFrQec8ntYc6V5tE4oVUq5n4hnsTE1N0YVeiPRaDfcFXP2okaKwtyk3hZuIpbi YCGU4GHHyhS8dzyVaB3TH8pgE2mliGHekmmT1OFu4zkT4gbyLDFVBZVA2QtU/9Oac4/N MlzqyLl2K8w/c7pWWSQg/ULwSf/hrLCfiCoKqt4OPkzvnUf46kM596aOseXLGaLuO5vB l/bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=Ws0sgPK8ew7x5vxl+TuTJyXb8SBuL/KQ6lfSG/O9Xu8=; b=mXF8JpxpOpSDPi8Se7onQJbeL2oF/599dUkW5/Z6HgluWIqUqoOD9FLN0l2HQ4eJAD Z9VK2DogiFKdG4ckLd+VwZ7y10Qtt/8iVEZ9WWEqdcJSg9sxMJAKWxlhCRkZuuDcJbKi 5b/11LGB0jhpuEYc2+0lYajheFlBLaIilCwN+69zxOHBcsZgWm7CgVP2OcKfwBgmG/h+ 3P3mgRWVqAKZ4CebxIZe3ZORDlNUV7GG1JoJtZvzS1RjLiukgV84UA/1XUmAUaHG8sFi Jn1rWS4XzEbnt1RThpARUieuzBz80Ixj4knQ+wxO4vqapTUMoGSV0cF5LnMNLscrHrmD K+IQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lwn.net header.s=20201203 header.b=rFS60iFo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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(mdns.lwn.net [45.79.72.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ms.lwn.net (Postfix) with ESMTPSA id 3B1FA7DE; Tue, 13 Jun 2023 09:46:35 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 ms.lwn.net 3B1FA7DE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lwn.net; s=20201203; t=1686649600; bh=Ws0sgPK8ew7x5vxl+TuTJyXb8SBuL/KQ6lfSG/O9Xu8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rFS60iFolb45Rs8MlzAbX9/IuNIHcSz+Kh3iCrSfaqXJXiHRzsDJjwhJAGdCK2fp/ 4tRCQQsJsJtnxTcol2K+zkySYho9KntiXdqkYfR2ZPVebcQTRVgCPP7MFKZN52p9cf 0V9j0i2vmxH4u1OXTtuVk7c4taBYVMw15HJQA6XKCuJdmFOYyuOF/IIypZV6c5iHwY CofdjXO1zlP230wQ5GZyHzIpVxjd32GM0Z2FSsz9+ORhaG7EsQG2UtCS9nUlHs62u6 KQs18KP840i93BAh1rlsDQL+7TmC6X3irvglULosWSeq8IQL+jWx17ZI9nJhoGcUld AJbXeYPk1aKpA== From: Jonathan Corbet To: linux-doc@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa Subject: [PATCH 5/5] perf arm-spe: Fix a dangling Documentation/arm64 reference Date: Tue, 13 Jun 2023 03:46:06 -0600 Message-Id: <20230613094606.334687-6-corbet@lwn.net> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613094606.334687-1-corbet@lwn.net> References: <20230613094606.334687-1-corbet@lwn.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768581239889495686?= X-GMAIL-MSGID: =?utf-8?q?1768581239889495686?= The arm64 documentation has moved under Documentation/arch/. Fix up a dangling reference to match. Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Mark Rutland Cc: Alexander Shishkin Cc: Jiri Olsa Signed-off-by: Jonathan Corbet Acked-by: Arnaldo Carvalho de Melo Acked-by: Catalin Marinas --- tools/perf/util/arm-spe-decoder/arm-spe-decoder.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c index f3918f290df5..ba807071d3c1 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c @@ -51,7 +51,7 @@ static u64 arm_spe_calc_ip(int index, u64 payload) * (bits [63:56]) is assigned as top-byte tag; so we only can * retrieve address value from bits [55:0]. * - * According to Documentation/arm64/memory.rst, if detects the + * According to Documentation/arch/arm64/memory.rst, if detects the * specific pattern in bits [55:52] of payload which falls in * the kernel space, should fixup the top byte and this allows * perf tool to parse DSO symbol for data address correctly.