From patchwork Tue Jun 13 07:04:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 107125 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp362357vqr; Tue, 13 Jun 2023 00:31:28 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ49GZKggvOZtVzT/+e/P9IYSajHs0kMHhjwTSRHufl1CPauoBPCDdPIZcdcguyplfQNK8We X-Received: by 2002:a17:902:e84a:b0:1ae:6a3:d058 with SMTP id t10-20020a170902e84a00b001ae06a3d058mr10116508plg.36.1686641488000; Tue, 13 Jun 2023 00:31:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686641487; cv=none; d=google.com; s=arc-20160816; b=Vcdx5Kp/NU4LUtKb54dVx3HHbpokZhnPmPolEIavnHblPQrDcuBn1J68bFa6hP6iwq gaB1Gng08se6L+Bjnfh554AmIlXUDz3bh5hsrT8VitqQihrF6cmRKNbtlG1y5L+xAz/0 HH9m2WZCbUQzw+RM62W2RQNtyGFLXFLYqLR0IRnqAoK8++aISUiWNA5XrkEcojWc7umK RHB7JBrIRdvcSkIzVUUmJkQDDXM60Zp64nDSMQlS3b53JntIeaLpLbT0eaALQT6Uj2FN dprQYnhT2oLhscYn7LTJujMjfK03zg1y09x5PE4At+juDWCmouwqhlzjzsedSnlcYkbu FxaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0QIo7FNWZ1UIM4tqZ9LSf2/VoGXwoKNu0Yk+WwCE7J4=; b=weIIqfSUBhwvPKL6LcFe7C5E83HFtShAd9LX++HTsw0QPe9wfow9Bevi25O5bahwpd FXuOdSQBZBEyuZPxxV8zSg/dYEuv5EaKEhuJt6mQKrE7SdpcH02h0+F1ADgrRtrtwggy sW6Xs5dSaQGEkK+vyOjgVTgchFc1eptAGMs7Ea+5HYcqJrvhNMGeZgZ109IrlntiXI9l MFk1I7eddjh2Rd/am+f4jLJGusx+O1FxZfYFN4bw2jzDGD/jimYlrBnxw5RssoleZU3q SboC44uavuN/Wadj3j5uWCgei1jQTNfIzIuYlY1/wJv9vxR6sB/3UJ0fP5XqAjBmRfp1 swWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=CQBRJGAu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a10-20020a170902ee8a00b001b0191881efsi8382167pld.37.2023.06.13.00.31.15; Tue, 13 Jun 2023 00:31:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=CQBRJGAu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239750AbjFMHFV (ORCPT + 99 others); Tue, 13 Jun 2023 03:05:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239738AbjFMHFQ (ORCPT ); Tue, 13 Jun 2023 03:05:16 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9534173C; Tue, 13 Jun 2023 00:05:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686639914; x=1718175914; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fRjFS0tyWhibQ8jFtctjzfuGuQJU7LCgPahmmxu6a7A=; b=CQBRJGAu0JvhJFfEp4sebDhUB06zfGs/3ynbNiJXsK+hCEVcIY/zJ6yn wWvWXQQu58Zl0WdRiE6t+BD0E3SRAOWM9Wu2LeTGLIWtNIQxLDBCbRrvF 8A76godPW5pr6OKfyllZ2CuBDLJ2Pv08yxETg0NeK9miYRiJjzJdsdurd 8g8AgWQZOG9i5SWKSV7rM+W63qYmXMgMtJeTRvJzBHAlNo4dLI4O4+mt5 JCRrEyaMRN/PwLnWPlShcfxOTRfEgS94npHMqqAN13VLz3sfHsFl1XzWd xRJpv0YY6/D4thXIKfycorIODtZaCsEzG6IC57R50LfaVX4iA5m6Rns5A A==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="218182139" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:05:12 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:05:11 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:02 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , CC: , , , , , , , Manikandan Subject: [PATCH 1/9] dt-bindings: mfd: Add bindings for SAM9X7 LCD controller Date: Tue, 13 Jun 2023 12:34:18 +0530 Message-ID: <20230613070426.467389-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768571785243429551?= X-GMAIL-MSGID: =?utf-8?q?1768571785243429551?= Add new compatible string for the XLCD controller on SAM9X7 SoC. Signed-off-by: Manikandan Muralidharan Acked-by: Conor Dooley --- Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt index 5f8880cc757e..7c77b6bf4adb 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt @@ -8,6 +8,7 @@ Required properties: "atmel,sama5d3-hlcdc" "atmel,sama5d4-hlcdc" "microchip,sam9x60-hlcdc" + "microchip,sam9x7-xlcdc" - reg: base address and size of the HLCDC device registers. - clock-names: the name of the 3 clocks requested by the HLCDC device. Should contain "periph_clk", "sys_clk" and "slow_clk". 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Signed-off-by: Manikandan Muralidharan --- drivers/mfd/atmel-hlcdc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd/atmel-hlcdc.c index 3c2414ba4b01..8755c91ce854 100644 --- a/drivers/mfd/atmel-hlcdc.c +++ b/drivers/mfd/atmel-hlcdc.c @@ -141,6 +141,7 @@ static const struct of_device_id atmel_hlcdc_match[] = { { .compatible = "atmel,sama5d3-hlcdc" }, { .compatible = "atmel,sama5d4-hlcdc" }, { .compatible = "microchip,sam9x60-hlcdc" }, + { .compatible = "microchip,sam9x7-xlcdc" }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, atmel_hlcdc_match); From patchwork Tue Jun 13 07:04:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 107117 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp357428vqr; Tue, 13 Jun 2023 00:18:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4x19hsr618qg5AZ8fJAuUCGG3vvxc0asxEkRHrTvP3L4Us+d0S6n/3bJK0NLn624srDBcL X-Received: by 2002:a17:906:7947:b0:974:e767:e1db with SMTP id l7-20020a170906794700b00974e767e1dbmr12525768ejo.46.1686640700883; Tue, 13 Jun 2023 00:18:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686640700; cv=none; d=google.com; s=arc-20160816; b=s37nckuCLRB/LLMgfl1nv9EPKZ+N7rrlGRGqRVLD/QrBamY4ZshqnNZlKkiPIX54ZJ wXJAssVl8Et/dD0h0C4Lgo4vZt5eR9PWo3531vVXF3ZXT9HgfTfOX7cehRMO9h5iW19G 2MjOtoYJKK5xtRNQPPQodJeQ3WTuQ/7+oNAsC5aaizVWi2OQF5oY+QAV1S3zMsjAIyeV AJvsdmwds4t7aJUPXDHJyAeEHXWGO/9VtkLdPTPdXLvXg96U3U+vUhs1P+6QStRb5U9M RCnOSh2v6h7nSHrTnp98JyAIwcmL91F3xpZmpphLvIrliZZVY6YtmmFmvgiKrF1zhVnT EMTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JRWwxC2xvquConYUsUskl8FgJUY+7MaZ1UUs7R38bm8=; b=nrwMl8mYLV8Erb5V3r0Y1ikYh9MHXGHC2f0Mre5HvhslJ0jB9eIh4McXAOnET0wTo+ JomjYEv9aggWBN5lOGie9xUB/V248Z4OKps3S+Bz/DkHLWtEiqLc1DZGGprC7InysKoC G5b5+9KLt/YtIwcffa0UuOTjN3aFCFes7Tx1SDGR87TBVzgDzuNc4f8TVbAd54kQz8zS TJz0q0QY2mfYkyFbtAEXHykOc+iv1O0dshb8u+oFp16s9WuwCdl044IjqbOhoQzthu6w lqRJ7zejj+VXv5l6cPPb4/8J80/+hqxxK+aqsOdFQsqMP4U7KgKTt6TSFz11J0OYH5VE wp7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=lauxSJOB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Tue, 13 Jun 2023 00:05:29 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:20 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , CC: , , , , , , , Manikandan Subject: [PATCH 3/9] drm: atmel-hlcdc: add LCD controller layer definition for SAM9X7 Date: Tue, 13 Jun 2023 12:34:20 +0530 Message-ID: <20230613070426.467389-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768570959084458167?= X-GMAIL-MSGID: =?utf-8?q?1768570959084458167?= Add the LCD controller layer definition and descriptor structure for SAM9X7 for the following layers, - Base Layer - Overlay1 Layer - Overlay2 Layer - High End Overlay Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 96 ++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index fa0f9a93d50d..d7ad828e9e8c 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -462,6 +462,98 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sam9x60 = { .layers = atmel_hlcdc_sam9x60_layers, }; +static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x7_layers[] = { + { + .name = "base", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x60, + .id = 0, + .type = ATMEL_HLCDC_BASE_LAYER, + .cfgs_offset = 0x1c, + .layout = { + .xstride = { 2 }, + .default_color = 3, + .general_config = 4, + .disc_pos = 5, + .disc_size = 6, + }, + .clut_offset = 0x700, + }, + { + .name = "overlay1", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x160, + .id = 1, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset = 0x1c, + .layout = { + .pos = 2, + .size = 3, + .xstride = { 4 }, + .pstride = { 5 }, + .default_color = 6, + .chroma_key = 7, + .chroma_key_mask = 8, + .general_config = 9, + }, + .clut_offset = 0xb00, + }, + { + .name = "overlay2", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x260, + .id = 2, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset = 0x1c, + .layout = { + .pos = 2, + .size = 3, + .xstride = { 4 }, + .pstride = { 5 }, + .default_color = 6, + .chroma_key = 7, + .chroma_key_mask = 8, + .general_config = 9, + }, + .clut_offset = 0xf00, + }, + { + .name = "high-end-overlay", + .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats, + .regs_offset = 0x360, + .id = 3, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset = 0x30, + .layout = { + .pos = 2, + .size = 3, + .memsize = 4, + .xstride = { 5, 7 }, + .pstride = { 6, 8 }, + .default_color = 9, + .chroma_key = 10, + .chroma_key_mask = 11, + .general_config = 12, + .csc = 16, + .scaler_config = 23, + }, + .clut_offset = 0x1300, + }, +}; + +static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x7 = { + .min_width = 0, + .min_height = 0, + .max_width = 2048, + .max_height = 2048, + .max_spw = 0xff, + .max_vpw = 0xff, + .max_hpw = 0x3ff, + .fixed_clksrc = true, + .nlayers = ARRAY_SIZE(atmel_xlcdc_sam9x7_layers), + .layers = atmel_xlcdc_sam9x7_layers, +}; + static const struct of_device_id atmel_hlcdc_of_match[] = { { .compatible = "atmel,at91sam9n12-hlcdc", @@ -487,6 +579,10 @@ static const struct of_device_id atmel_hlcdc_of_match[] = { .compatible = "microchip,sam9x60-hlcdc", .data = &atmel_hlcdc_dc_sam9x60, }, + { + .compatible = "microchip,sam9x7-xlcdc", + .data = &atmel_xlcdc_dc_sam9x7, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match); From patchwork Tue Jun 13 07:04:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 107120 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp361575vqr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id az9-20020a056a02004900b0054f947f3d27si2668727pgb.338.2023.06.13.00.29.34; Tue, 13 Jun 2023 00:29:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=tL0abFG6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240339AbjFMHFx (ORCPT + 99 others); Tue, 13 Jun 2023 03:05:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235106AbjFMHFm (ORCPT ); Tue, 13 Jun 2023 03:05:42 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6CF91995; Tue, 13 Jun 2023 00:05:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686639939; x=1718175939; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/CEVsHh3cXtXVIDLUkkyiXlWx5YACPw7oC/4tgbf35c=; b=tL0abFG6utt+46YnADkmRLMD5dLJCLP8ToAc31E9Mv0bStwY2SlllypM ZUw13KgGB9kpYUhByws1krr8I938gx20lc+LryXRlE9x6UIqxmo+MZPRZ UIQFhRRb81lVGMDQsblXdXyuSvPqOZEtl4F+pRAnRCmObH/L2Xfx4SoqN asBbasAB2M9BJeOyHuECbfMnER5YfaPgAXLubCf8Vxpy22/MN2DBkgVZl 6nZhzKxn7Y4ZeFgTSmzT/BSOL6MI9CLmtNtasMTLLmmKFRAhOeCvnHvrE PRWWrVdow4CHSWiSscJPeJO6gITDGKQHHcIF8H+tJFrPveSaHtAgfWMHj w==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="217553976" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:05:38 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:05:38 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:29 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , CC: , , , , , , , Manikandan , Durai Manickam KR Subject: [PATCH 4/9] drm: atmel-hlcdc: Define SAM9X7 XLCDC specific registers Date: Tue, 13 Jun 2023 12:34:21 +0530 Message-ID: <20230613070426.467389-5-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,UPPERCASE_50_75, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768571678133531216?= X-GMAIL-MSGID: =?utf-8?q?1768571678133531216?= From: Durai Manickam KR The register address of the XLCDC IP used in SAM9X7 are different from the previous HLCDC.Defining those address space with valid macros. Signed-off-by: Durai Manickam KR [manikandan.m@microchip.com: Remove unused macro definitions] Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 108 +++++++++++++++++++ include/linux/mfd/atmel-hlcdc.h | 10 ++ 2 files changed, 118 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index 5b5c774e0edf..aed1742b3665 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -15,6 +15,7 @@ #include +/* LCD controller common registers */ #define ATMEL_HLCDC_LAYER_CHER 0x0 #define ATMEL_HLCDC_LAYER_CHDR 0x4 #define ATMEL_HLCDC_LAYER_CHSR 0x8 @@ -128,6 +129,113 @@ #define ATMEL_HLCDC_MAX_LAYERS 6 +/* XLCDC controller specific registers */ +#define ATMEL_XLCDC_LAYER_ENR 0x10 +#define ATMEL_XLCDC_LAYER_EN BIT(0) + +#define ATMEL_XLCDC_LAYER_IER 0x0 +#define ATMEL_XLCDC_LAYER_IDR 0x4 +#define ATMEL_XLCDC_LAYER_IMR 0x8 +#define ATMEL_XLCDC_LAYER_ISR 0xc +#define ATMEL_XLCDC_LAYER_DONE_IRQ(p) BIT(0 + (8 * (p))) +#define ATMEL_XLCDC_LAYER_ERROR_IRQ(p) BIT(1 + (8 * (p))) +#define ATMEL_XLCDC_LAYER_OVR_IRQ(p) BIT(2 + (8 * (p))) + +#define ATMEL_XLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x4) + 0x18) + +#define ATMEL_XLCDC_LAYER_DMA_CFG 0 +#define ATMEL_XLCDC_LAYER_DMA_BLEN_MASK GENMASK(6, 4) +#define ATMEL_XLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4) +#define ATMEL_XLCDC_LAYER_DMA_BLEN_INCR32 (4 << 4) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_MASK GENMASK(10, 8) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_SINGLE (0 << 8) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR4 (1 << 8) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR8 (2 << 8) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR16 (3 << 8) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR32 (4 << 8) + +#define ATMEL_XLCDC_GAM BIT(2) + +#define ATMEL_XLCDC_LAYER_POS(x, y) ((x) | ((y) << 16)) +#define ATMEL_XLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16)) + +#define ATMEL_XLCDC_LAYER_DMA BIT(0) +#define ATMEL_XLCDC_LAYER_REP BIT(1) +#define ATMEL_XLCDC_LAYER_CRKEY BIT(2) +#define ATMEL_XLCDC_LAYER_DSTKEY BIT(3) +#define ATMEL_XLCDC_LAYER_DISCEN BIT(4) +#define ATMEL_XLCDC_LAYER_VIDPRI BIT(5) +#define ATMEL_XLCDC_LAYER_SFACTC_MASK GENMASK(8, 6) +#define ATMEL_XLCDC_LAYER_SFACTC_ONE (0 << 6) +#define ATMEL_XLCDC_LAYER_SFACTC_ZERO (1 << 6) +#define ATMEL_XLCDC_LAYER_SFACTC_A0 (2 << 6) +#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AD (3 << 6) +#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS (4 << 6) +#define ATMEL_XLCDC_LAYER_SFACTC_M_A0_MULT_AD (5 << 6) +#define ATMEL_XLCDC_LAYER_SFACTA_MASK GENMASK(10, 9) +#define ATMEL_XLCDC_LAYER_SFACTA_ZERO (0 << 9) +#define ATMEL_XLCDC_LAYER_SFACTA_ONE (1 << 9) +#define ATMEL_XLCDC_LAYER_SFACTA_A0 (2 << 9) +#define ATMEL_XLCDC_LAYER_SFACTA_A1 (3 << 9) +#define ATMEL_XLCDC_LAYER_DFACTC_MASK GENMASK(13, 11) +#define ATMEL_XLCDC_LAYER_DFACTC_ZERO (0 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_ONE (1 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_A0 (2 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_A1 (3 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_A0_MULT_AD (4 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AD (5 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS (6 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0 (7 << 11) +#define ATMEL_XLCDC_LAYER_DFACTA_MASK GENMASK(15, 14) +#define ATMEL_XLCDC_LAYER_DFACTA_ZERO (0 << 14) +#define ATMEL_XLCDC_LAYER_DFACTA_ONE (1 << 14) +#define ATMEL_XLCDC_LAYER_DFACTA_M_A0_MULT_AS (2 << 14) +#define ATMEL_XLCDC_LAYER_DFACTA_A1 (3 << 14) +#define ATMEL_XLCDC_LAYER_A0_SHIFT 16 +#define ATMEL_XLCDC_LAYER_A0_MASK \ + GENMASK(23, ATMEL_XLCDC_LAYER_A0_SHIFT) +#define ATMEL_XLCDC_LAYER_A0(x) \ + ((x) << ATMEL_XLCDC_LAYER_A0_SHIFT) +#define ATMEL_XLCDC_LAYER_A1_SHIFT 24 +#define ATMEL_XLCDC_LAYER_A1_MASK \ + GENMASK(31, ATMEL_XLCDC_LAYER_A1_SHIFT) +#define ATMEL_XLCDC_LAYER_A1(x) \ + ((x) << ATMEL_XLCDC_LAYER_A1_SHIFT) + +#define ATMEL_XLCDC_LAYER_DISC_POS(x, y) ((x) | ((y) << 16)) +#define ATMEL_XLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16)) + +#define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE BIT(0) +#define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE BIT(1) +#define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE BIT(4) +#define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE BIT(5) + +#define ATMEL_XLCDC_LAYER_VXSYCFG_ZERO (0 << 0) +#define ATMEL_XLCDC_LAYER_VXSYCFG_ONE (1 << 0) +#define ATMEL_XLCDC_LAYER_VXSYCFG_TWO (2 << 0) +#define ATMEL_XLCDC_LAYER_VXSYCFG_THREE (3 << 0) +#define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE BIT(4) +#define ATMEL_XLCDC_LAYER_VXSYBICU_ENABLE BIT(5) +#define ATMEL_XLCDC_LAYER_VXSCCFG_ZERO (0 << 16) +#define ATMEL_XLCDC_LAYER_VXSCCFG_ONE (1 << 16) +#define ATMEL_XLCDC_LAYER_VXSCCFG_TWO (2 << 16) +#define ATMEL_XLCDC_LAYER_VXSCCFG_THREE (3 << 16) +#define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE BIT(20) +#define ATMEL_XLCDC_LAYER_VXSCBICU_ENABLE BIT(21) + +#define ATMEL_XLCDC_LAYER_HXSYCFG_ZERO (0 << 0) +#define ATMEL_XLCDC_LAYER_HXSYCFG_ONE (1 << 0) +#define ATMEL_XLCDC_LAYER_HXSYCFG_TWO (2 << 0) +#define ATMEL_XLCDC_LAYER_HXSYCFG_THREE (3 << 0) +#define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE BIT(4) +#define ATMEL_XLCDC_LAYER_HXSYBICU_ENABLE BIT(5) +#define ATMEL_XLCDC_LAYER_HXSCCFG_ZERO (0 << 16) +#define ATMEL_XLCDC_LAYER_HXSCCFG_ONE (1 << 16) +#define ATMEL_XLCDC_LAYER_HXSCCFG_TWO (2 << 16) +#define ATMEL_XLCDC_LAYER_HXSCCFG_THREE (3 << 16) +#define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE BIT(20) +#define ATMEL_XLCDC_LAYER_HXSCBICU_ENABLE BIT(21) + /** * Atmel HLCDC Layer registers layout structure * diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcdc.h index a186119a49b5..80d675a03b39 100644 --- a/include/linux/mfd/atmel-hlcdc.h +++ b/include/linux/mfd/atmel-hlcdc.h @@ -22,6 +22,8 @@ #define ATMEL_HLCDC_DITHER BIT(6) #define ATMEL_HLCDC_DISPDLY BIT(7) #define ATMEL_HLCDC_MODE_MASK GENMASK(9, 8) +#define ATMEL_XLCDC_MODE_MASK GENMASK(10, 8) +#define ATMEL_XLCDC_DPI BIT(11) #define ATMEL_HLCDC_PP BIT(10) #define ATMEL_HLCDC_VSPSU BIT(12) #define ATMEL_HLCDC_VSPHO BIT(13) @@ -34,6 +36,12 @@ #define ATMEL_HLCDC_IDR 0x30 #define ATMEL_HLCDC_IMR 0x34 #define ATMEL_HLCDC_ISR 0x38 +#define ATMEL_XLCDC_ATTRE 0x3c + +#define ATMEL_XLCDC_BASE_UPDATE BIT(0) +#define ATMEL_XLCDC_OVR1_UPDATE BIT(1) +#define ATMEL_XLCDC_OVR3_UPDATE BIT(2) +#define ATMEL_XLCDC_HEO_UPDATE BIT(3) #define ATMEL_HLCDC_CLKPOL BIT(0) #define ATMEL_HLCDC_CLKSEL BIT(2) @@ -48,6 +56,8 @@ #define ATMEL_HLCDC_DISP BIT(2) #define ATMEL_HLCDC_PWM BIT(3) #define ATMEL_HLCDC_SIP BIT(4) +#define ATMEL_XLCDC_SD BIT(5) +#define ATMEL_XLCDC_CM BIT(6) #define ATMEL_HLCDC_SOF BIT(0) #define ATMEL_HLCDC_SYNCDIS BIT(1) From patchwork Tue Jun 13 07:04:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 107118 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp357735vqr; Tue, 13 Jun 2023 00:19:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7XoLcT8VIXjEqA9+2YiLfi68QedxFYTMtEJRgwxU6x9yv1vWviid8kc+EzDUvJSqjDym6z X-Received: by 2002:a17:907:3607:b0:8b1:7de3:cfaa with SMTP id bk7-20020a170907360700b008b17de3cfaamr11354272ejc.3.1686640751976; Tue, 13 Jun 2023 00:19:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686640751; cv=none; d=google.com; s=arc-20160816; b=J+tzjM8/oBbwnVEHAvmMeB9MPyV5TScFjTZSNNfP6kM4kwyQhkaAgFOsICRmlv+UeW rJyHWFzf1DzxuI6/h7dNvcwsY/AKceKRQXOapMmZWj4716SITigHisBAYwN7Asr46nix VNAHxQghdAvSrHWc+txhtU7zEDyVFYMhx0KD2oZoj93LHp8JUATy7HZ1GboGynF5OEc3 omjPCx++U7vFIdf7la7izAYlf4/+sFeAPKQhWPk7W7ehMH1JNBPYbVZxLssO+eXEat7O vC2U5c8S4RgvMbkYdqJ7B3qvfQ00KnXSXK1wZ/CTaRNxsh4l0bMyrl+ghuyrUBJPI2F6 E8nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=osaOVUDCTeq1PWKBuFR+jboA7G6BpwGBXM2L/0MdBi8=; b=XvbhTxn9AdPLiGYhyjE+o6ApQSEDBxEeiEi3cErhg9iGc9EfuUnm2LX9t5gO02R8+L +2JnzYsxrk9htYCV6tShtFT6VKHhKs64Zpego5Buspw1CSADwhGlkkKJFQkiy2tduYBn FjAI3Ij6iVoB0C7+N7R4FFG1K53LX70fXIMZn526YAMsjbkjA6krOmWSJX5NlCH1+wNF nReeJ6TNxvhGR4whQJDEZ3SJs4RwP7SrZS/FABjlKxkViy0P2ioZbf9NmbnuQNu511an sMvVJSGRMsVpcUhemorfw+TZhxfgyt0nwQwz7hnECRgk6gHk7uc6Qh9Xu28OxuFZ38R4 /coQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=pOOOyITO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ot13-20020a170906cccd00b00977e50c2f96si6574535ejb.558.2023.06.13.00.18.47; Tue, 13 Jun 2023 00:19:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=pOOOyITO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240442AbjFMHGC (ORCPT + 99 others); Tue, 13 Jun 2023 03:06:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238110AbjFMHFu (ORCPT ); Tue, 13 Jun 2023 03:05:50 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6779410F7; Tue, 13 Jun 2023 00:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686639949; x=1718175949; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z7sh0i6Gl2/LRPzmrS845oLG7MhlbMwUzMTImsVh/hI=; b=pOOOyITOP1Wtaat6scwATLEe7NwZIWFjfRwM+MMUnoi98/veJMevFg0i WaKV0DdwgAgcGCBZlffYU5sDjVv90sgqGko4dg9qabGstxz50kJbq7STy Esb81TBwEbC9eczpBgjsPH09j0T+iWoBtVFhsMHNWYqU/TdFYtwSRib5h 5ltAcalXNbmvUPQyConoo+Su56AtIe4L/1Xm8km2BoFAwhN9NdjENJ5EP X8672+7mRpWTjz51xIK0s/p5PW9zveM+kDZ8nc11uLcOZ3zqNuh6pW7Iy TWWXwpiX7g1OJo6U91twwsBY+pgmUNjfRYatcdkDKCKrPrd6pXZLp7sRJ Q==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="229806838" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:05:47 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:05:46 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:38 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , CC: , , , , , , , Manikandan , Durai Manickam KR Subject: [PATCH 5/9] drm: atmel-hlcdc: add compatible string check for XLCDC and HLCDC Date: Tue, 13 Jun 2023 12:34:22 +0530 Message-ID: <20230613070426.467389-6-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768571012790665469?= X-GMAIL-MSGID: =?utf-8?q?1768571012790665469?= From: Durai Manickam KR Add compatible string check to differentiate XLCDC and HLCDC code within the atmel-hlcdc driver files. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 7 +++++++ drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index d7ad828e9e8c..fbbd2592efc7 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -761,6 +761,13 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev) if (!dc) return -ENOMEM; + /* SAM9X7 supports XLCDC */ + if (!strcmp(match->compatible, "microchip,sam9x7-xlcdc")) + dc->is_xlcdc = true; + else + /* Other SoC's that supports HLCDC IP */ + dc->is_xlcdc = false; + dc->desc = match->data; dc->hlcdc = dev_get_drvdata(dev->dev->parent); dev->dev_private = dc; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index aed1742b3665..804e4d476f2b 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -451,6 +451,7 @@ struct atmel_hlcdc_dc { u32 imr; struct drm_atomic_state *state; } suspend; + bool is_xlcdc; }; extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats; From patchwork Tue Jun 13 07:04:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 107121 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp361946vqr; Tue, 13 Jun 2023 00:30:41 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4+LgKP3o9jDpSY65RPSxyXFX0chUOSXsJmxhMBfWWo/3v1OLLw9B5F6K6NVxPDtn4/H2gV X-Received: by 2002:a05:6358:f0e:b0:12b:ed05:18bb with SMTP id b14-20020a0563580f0e00b0012bed0518bbmr3302414rwj.27.1686641440981; Tue, 13 Jun 2023 00:30:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686641440; cv=none; d=google.com; s=arc-20160816; b=aNy8CjLjwrIaC1SAof+9O8IRaT35Y9E57n06rz1w3yA97jy1UrQsWDe6bZU4Y0ZKLj 1AlvEZDS5B+gerlzELO3FMTTMRn9TySZX5osSfPO9Gpp5ApxkDQ1+AVTg7VH/tkpNyXR /bgcUci4oyok9ee/vNAEvuC0xFlraNbh0vKB1DNPKTJdPA0ZURS3cNkXfmrtL5OP3rGV vD1vY+7cIjDbQfXoqO4/GXICOrd1VyK+5V48rkpv3X6XxxqvKAor1XfXVWCzEiEEfy+1 whiExLkwLj9LabtCgaCFZGyMaW6mMPKSLRRhVlchj2t8+Wv4HQwVg8BpOau8r/canxnS ioew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BvzXRq3f/K2MBbL4ZylYXk6bw+ymL0ne8Ws6jqdwKSg=; b=ufDeltf9ycVfImCBUIDt0ugjxpx0Qi/VZ3zqMQftH3N6IXrWGQoe+B9N4OT20pnzf6 Q84Xwt7VbDDb/qplPX2y2ZD7UMUNgfpQqZY+VUfyQd2cBGNe/+b1HO9oUm3zMbTOEMfT y+QH0eW/ak+S3zS+4e1DQ4Yia65tuq3xJ6q6R5lAeiKXJbcp9aTdfBaRApXl1VpSuJLR XqK3Qb7tQjHX3FEl0wzgLoYqHfHhakuWOodtYbxHIertqgYoR0xLQCmpD7biQlS2JNQE EofkuS7lk82Akv508uDzVZh4jbxiaKCmbRp+E3zln0yqT9r9+b2a4zn/Il9k3Cj36KJK BwJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=qm0p7qM1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m189-20020a6326c6000000b00542aab0e4fdsi8128539pgm.129.2023.06.13.00.30.27; Tue, 13 Jun 2023 00:30:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=qm0p7qM1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240405AbjFMHHT (ORCPT + 99 others); Tue, 13 Jun 2023 03:07:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240398AbjFMHGz (ORCPT ); Tue, 13 Jun 2023 03:06:55 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2819C1FFB; Tue, 13 Jun 2023 00:06:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686639975; x=1718175975; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EXoJDlE0rvVHtvzhro8MbvcrVWmqxytqo57znv5RaEU=; b=qm0p7qM1AFJ+i55uLCzWk8mXVzZU7fvQDv6x7flTJK/BEeBKW+lTf3Dr kX6rLuRK/VLKDTNXrQDms3JxFjIW6c+AdemsBlSZ4x0kZptL+m73L5zu+ QvkEv7VrQoC/+K7i50EGN2xZ8Ly8lUaw2TB2gpMJXy2S6/kl9D35trdT5 CtbJaJsv2ONyEaXLgeYcMnzndXqdctMA38W4uihQhbaSywwNJlBlQlpa0 M0B4wB8KCu2Ho/bPu5gK54Aal6IGCRYIkiP/9hh+V8RpbHu7c6KSDTvRK eKLUENrl9xVwX+qX7B272uAkizKSGbeVRFd7z010zXtmD9MEnbQkzmAUz A==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="229806880" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:06:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:05:56 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:47 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , CC: , , , , , , , Manikandan , Durai Manickam KR Subject: [PATCH 6/9] drm: atmel_hlcdc: Add support for XLCDC in atmel LCD driver Date: Tue, 13 Jun 2023 12:34:23 +0530 Message-ID: <20230613070426.467389-7-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768571735775327337?= X-GMAIL-MSGID: =?utf-8?q?1768571735775327337?= - XLCDC in SAM9X7 has different sets of registers and additional configuration bits when compared to previous HLCDC IP. Read/write operation on the controller registers is now separated using the XLCDC status flag. - HEO scaling, window resampling, Alpha blending, YUV-to-RGB conversion in XLCDC is derived and handled using additional configuration bits and registers. - Writing one to the Enable fields of each layer in LCD_ATTRE is required to reflect the values set in Configuration, FBA, Enable registers of each layer Signed-off-by: Manikandan Muralidharan [Hari.PrasathGE@microchip.com: update the attribute field for each layer] Signed-off-by: Hari Prasath Gujulan Elango [durai.manickamkr@microchip.com: implement status flag to seprate register update] Signed-off-by: Durai Manickam KR --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 28 +- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 297 ++++++++++++++---- 2 files changed, 256 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 58184cd6ab0b..7c9cf7c0c75d 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -139,10 +139,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); cfg = state->output_mode << 8; - if (adj->flags & DRM_MODE_FLAG_NVSYNC) + if (!crtc->dc->is_xlcdc && (adj->flags & DRM_MODE_FLAG_NVSYNC)) cfg |= ATMEL_HLCDC_VSPOL; - if (adj->flags & DRM_MODE_FLAG_NHSYNC) + if (!crtc->dc->is_xlcdc && (adj->flags & DRM_MODE_FLAG_NHSYNC)) cfg |= ATMEL_HLCDC_HSPOL; regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5), @@ -177,6 +177,18 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, pm_runtime_get_sync(dev->dev); + if (crtc->dc->is_xlcdc) { + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_CM); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + (status & ATMEL_XLCDC_CM)) + cpu_relax(); + + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_SD); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + !(status & ATMEL_XLCDC_SD)) + cpu_relax(); + } + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP); while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && (status & ATMEL_HLCDC_DISP)) @@ -231,6 +243,18 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, !(status & ATMEL_HLCDC_DISP)) cpu_relax(); + if (crtc->dc->is_xlcdc) { + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_CM); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + !(status & ATMEL_XLCDC_CM)) + cpu_relax(); + + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_SD); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + (status & ATMEL_XLCDC_SD)) + cpu_relax(); + } + pm_runtime_put_sync(dev->dev); } diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index daa508504f47..fe33476818c4 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -330,11 +330,59 @@ static void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, yfactor)); } +static void atmel_xlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_state *state) +{ + const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; + u32 xfactor, yfactor; + + if (!desc->layout.scaler_config) + return; + + if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) { + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.scaler_config, 0); + return; + } + + /* xfactor = round[(2^20 * XMEMSIZE)/XSIZE)] */ + xfactor = (1048576 * state->src_w) / state->crtc_w; + + /* yfactor = round[(2^20 * YMEMSIZE)/YSIZE)] */ + yfactor = (1048576 * state->src_h) / state->crtc_h; + + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, + ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE | + ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE | + ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE | + ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE); + + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 1, + yfactor); + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 3, + xfactor); + + /* As per YCbCr window resampling configuration */ + if (state->base.fb->format->format == DRM_FORMAT_YUV420) { + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, + yfactor / 2); + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4, + xfactor / 2); + } else { + /* As per ARGB window resampling configuration */ + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, + yfactor); + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4, + xfactor); + } +} + static void atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, struct atmel_hlcdc_plane_state *state) { const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; if (desc->layout.size) atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size, @@ -352,7 +400,10 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, ATMEL_HLCDC_LAYER_POS(state->crtc_x, state->crtc_y)); - atmel_hlcdc_plane_setup_scaler(plane, state); + if (!(dc->is_xlcdc)) + atmel_hlcdc_plane_setup_scaler(plane, state); + else + atmel_xlcdc_plane_setup_scaler(plane, state); } static void @@ -362,33 +413,58 @@ atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, unsigned int cfg = ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id; const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; const struct drm_format_info *format = state->base.fb->format; - + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; /* * Rotation optimization is not working on RGB888 (rotation is still * working but without any optimization). */ - if (format->format == DRM_FORMAT_RGB888) + if ((!(dc->is_xlcdc)) && format->format == DRM_FORMAT_RGB888) cfg |= ATMEL_HLCDC_LAYER_DMA_ROTDIS; - atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG, - cfg); + if (!(dc->is_xlcdc)) { + atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG, + cfg); - cfg = ATMEL_HLCDC_LAYER_DMA | ATMEL_HLCDC_LAYER_REP; + cfg = ATMEL_HLCDC_LAYER_DMA | ATMEL_HLCDC_LAYER_REP; + } else { + atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_XLCDC_LAYER_DMA_CFG, + cfg); + + cfg = ATMEL_XLCDC_LAYER_DMA | ATMEL_XLCDC_LAYER_REP; + } if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) { - cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL | - ATMEL_HLCDC_LAYER_ITER; + if (!(dc->is_xlcdc)) { + cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL | + ATMEL_HLCDC_LAYER_ITER; + + if (format->has_alpha) + cfg |= ATMEL_HLCDC_LAYER_LAEN; + else + cfg |= ATMEL_HLCDC_LAYER_GAEN | + ATMEL_HLCDC_LAYER_GA(state->base.alpha); + } else { + /* + * Alpha Blending bits specific to SAM9X7 SoC + */ + cfg |= ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS | + ATMEL_XLCDC_LAYER_SFACTA_ONE | + ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS | + ATMEL_XLCDC_LAYER_DFACTA_ONE; + if (format->has_alpha) + cfg |= ATMEL_XLCDC_LAYER_A0(0xff); + else + cfg |= ATMEL_XLCDC_LAYER_A0(state->base.alpha); + } + } - if (format->has_alpha) - cfg |= ATMEL_HLCDC_LAYER_LAEN; + if (state->disc_h && state->disc_w) { + if (!(dc->is_xlcdc)) + cfg |= ATMEL_HLCDC_LAYER_DISCEN; else - cfg |= ATMEL_HLCDC_LAYER_GAEN | - ATMEL_HLCDC_LAYER_GA(state->base.alpha); + cfg |= ATMEL_XLCDC_LAYER_DISCEN; } - if (state->disc_h && state->disc_w) - cfg |= ATMEL_HLCDC_LAYER_DISCEN; - atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config, cfg); } @@ -441,33 +517,42 @@ static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane, struct atmel_hlcdc_plane_state *state) { const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; struct drm_framebuffer *fb = state->base.fb; u32 sr; int i; - sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); + if (!(dc->is_xlcdc)) + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); + else + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ENR); for (i = 0; i < state->nplanes; i++) { struct drm_gem_dma_object *gem = drm_fb_dma_get_gem_obj(fb, i); state->dscrs[i]->addr = gem->dma_addr + state->offsets[i]; - atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_HEAD(i), - state->dscrs[i]->self); - - if (!(sr & ATMEL_HLCDC_LAYER_EN)) { - atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_ADDR(i), - state->dscrs[i]->addr); + if (!(dc->is_xlcdc)) { atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_CTRL(i), - state->dscrs[i]->ctrl); + ATMEL_HLCDC_LAYER_PLANE_HEAD(i), + state->dscrs[i]->self); + + if (!(sr & ATMEL_HLCDC_LAYER_EN)) { + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_PLANE_ADDR(i), + state->dscrs[i]->addr); + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_PLANE_CTRL(i), + state->dscrs[i]->ctrl); + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_PLANE_NEXT(i), + state->dscrs[i]->self); + } + } else { atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_NEXT(i), - state->dscrs[i]->self); + ATMEL_XLCDC_LAYER_PLANE_ADDR(i), + state->dscrs[i]->addr); } - if (desc->layout.xstride[i]) atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.xstride[i], @@ -716,19 +801,31 @@ static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, struct drm_atomic_state *state) { struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); - + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; /* Disable interrupts */ - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR, - 0xffffffff); + if (!(dc->is_xlcdc)) + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR, + 0xffffffff); + else + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IDR, + 0xffffffff); /* Disable the layer */ - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHDR, - ATMEL_HLCDC_LAYER_RST | - ATMEL_HLCDC_LAYER_A2Q | - ATMEL_HLCDC_LAYER_UPDATE); + if (!(dc->is_xlcdc)) + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_CHDR, + ATMEL_HLCDC_LAYER_RST | + ATMEL_HLCDC_LAYER_A2Q | + ATMEL_HLCDC_LAYER_UPDATE); + else + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_XLCDC_LAYER_ENR, 0); /* Clear all pending interrupts */ - atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); + if (!(dc->is_xlcdc)) + atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); + else + atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR); } static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, @@ -739,6 +836,7 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); struct atmel_hlcdc_plane_state *hstate = drm_plane_state_to_atmel_hlcdc_plane_state(new_s); + struct atmel_hlcdc_dc *dc = p->dev->dev_private; u32 sr; if (!new_s->crtc || !new_s->fb) @@ -756,23 +854,46 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, atmel_hlcdc_plane_update_buffers(plane, hstate); atmel_hlcdc_plane_update_disc_area(plane, hstate); - /* Enable the overrun interrupts. */ - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, - ATMEL_HLCDC_LAYER_OVR_IRQ(0) | - ATMEL_HLCDC_LAYER_OVR_IRQ(1) | - ATMEL_HLCDC_LAYER_OVR_IRQ(2)); - - /* Apply the new config at the next SOF event. */ - sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, - ATMEL_HLCDC_LAYER_UPDATE | - (sr & ATMEL_HLCDC_LAYER_EN ? - ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN)); + if (!(dc->is_xlcdc)) { + /* Enable the overrun interrupts. */ + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, + ATMEL_HLCDC_LAYER_OVR_IRQ(0) | + ATMEL_HLCDC_LAYER_OVR_IRQ(1) | + ATMEL_HLCDC_LAYER_OVR_IRQ(2)); + + /* Apply the new config at the next SOF event. */ + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, + ATMEL_HLCDC_LAYER_UPDATE | + (sr & ATMEL_HLCDC_LAYER_EN ? + ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN)); + } else { + /* Enable the overrun interrupts. */ + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IER, + ATMEL_XLCDC_LAYER_OVR_IRQ(0) | + ATMEL_XLCDC_LAYER_OVR_IRQ(1) | + ATMEL_XLCDC_LAYER_OVR_IRQ(2)); + + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_ENR, + ATMEL_XLCDC_LAYER_EN); + } + + /* + * Updating XLCDC_xxxCFGx, XLCDC_xxxFBA and XLCDC_xxxEN, + * (where xxx indicates each layer) requires writing one to the + * Update Attribute field for each layer in LCDC_ATTRE register for SAM9X7. + */ + if (dc->is_xlcdc) { + regmap_write(dc->hlcdc->regmap, ATMEL_XLCDC_ATTRE, ATMEL_XLCDC_BASE_UPDATE | + ATMEL_XLCDC_OVR1_UPDATE | ATMEL_XLCDC_OVR3_UPDATE | + ATMEL_XLCDC_HEO_UPDATE); + } } static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) { const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER || desc->type == ATMEL_HLCDC_CURSOR_LAYER) { @@ -796,20 +917,50 @@ static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) return ret; } - if (desc->layout.csc) { + if (!(dc->is_xlcdc)) { + if (desc->layout.csc) { + /* + * TODO: decare a "yuv-to-rgb-conv-factors" property to let + * userspace modify these factors (using a BLOB property ?). + */ + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc, + 0x4c900091); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 1, + 0x7a5f5090); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 2, + 0x40040890); + } + } else { /* - * TODO: decare a "yuv-to-rgb-conv-factors" property to let - * userspace modify these factors (using a BLOB property ?). + * yuv-to-rgb-conv-factors are now defined from LCDC_HEOCFG16 to + * LCDC_HEOCFG21 registers in SAM9X7. */ - atmel_hlcdc_layer_write_cfg(&plane->layer, - desc->layout.csc, - 0x4c900091); - atmel_hlcdc_layer_write_cfg(&plane->layer, - desc->layout.csc + 1, - 0x7a5f5090); - atmel_hlcdc_layer_write_cfg(&plane->layer, - desc->layout.csc + 2, - 0x40040890); + if (desc->layout.csc) { + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc, + 0x00000488); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 1, + 0x00000648); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 2, + 0x1EA00480); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 3, + 0x00001D28); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 4, + 0x08100480); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 5, + 0x00000000); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 6, + 0x00000007); + } } return 0; @@ -819,19 +970,31 @@ void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) { const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; u32 isr; + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; - isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); + if (!(dc->is_xlcdc)) + isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); + else + isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR); /* * There's not much we can do in case of overrun except informing * the user. However, we are in interrupt context here, hence the * use of dev_dbg(). */ - if (isr & - (ATMEL_HLCDC_LAYER_OVR_IRQ(0) | ATMEL_HLCDC_LAYER_OVR_IRQ(1) | - ATMEL_HLCDC_LAYER_OVR_IRQ(2))) - dev_dbg(plane->base.dev->dev, "overrun on plane %s\n", - desc->name); + if (!(dc->is_xlcdc)) { + if (isr & + (ATMEL_HLCDC_LAYER_OVR_IRQ(0) | ATMEL_HLCDC_LAYER_OVR_IRQ(1) | + ATMEL_HLCDC_LAYER_OVR_IRQ(2))) + dev_dbg(plane->base.dev->dev, "overrun on plane %s\n", + desc->name); + } else { + if (isr & + (ATMEL_XLCDC_LAYER_OVR_IRQ(0) | ATMEL_XLCDC_LAYER_OVR_IRQ(1) | + ATMEL_XLCDC_LAYER_OVR_IRQ(2))) + dev_dbg(plane->base.dev->dev, "overrun on plane %s\n", + desc->name); + } } static const struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = { From patchwork Tue Jun 13 07:04:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 107124 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp362272vqr; Tue, 13 Jun 2023 00:31:18 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4GVSk2finKsTV/QVbKpxFIGgKcBRN1wwk6tN0me8TyAYFHAxnyH3oQF7bu7/xEhxIDY+n/ X-Received: by 2002:a17:90a:b38c:b0:25c:1a9b:db97 with SMTP id e12-20020a17090ab38c00b0025c1a9bdb97mr314576pjr.10.1686641478446; Tue, 13 Jun 2023 00:31:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686641478; cv=none; d=google.com; s=arc-20160816; b=UFnypADnehO/sNREc8/fCEYYIKWzU3gVubtmx2o0R6jqzcoBlBtYEv3qO5qd7WKnCi 00x2pREuwdYPbe2pQeE2Ek+lhJIkRLSMc0Z8hzGUO6V/g7Vd3WrRjPROEEWOXt8Q4hHk UMURljF2LWRJJdm2ITfT7fKaRiq5EwTF536tcVcArbOEQqJ+kto6LNkzQ+byFMVB+2Y0 8bBnwWxeL7WFAYlVtEGEitexj6FZB9ec5xsbBLII7Hep4yXBslXl9fo2eSfYSfQQXJh8 hQaP2jVka6j3PbsdU+GNPIjr5tpnAbf3CapwqTstp6mx4cIAwl4SPjgDFkhCeBHQGGVt Lbww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LUU9IQ6gjEYvbs5YNydrFaTb7VxTwnZUXtmPXk8jgkA=; b=l0PdnaA6Q3svuOt+qqU9AI+9KXIIXKpcCOvCczL1K2arlMJ0P+RCA7tTZf9SLZkKf8 rjfL9ojOvk62ly3qetqI4R50zeV9xluJYMnwKCAdGYz6p/7GmgjNc7o0+qnf7vnZ+Y4i qrx3OGNdy+fbgJIqxIQ+YZzFUoPA2E+bQHhf4k6gD41a87uV/lP4JKsO56IpSLixFMlL PKXh/45WHHPjBWiYQtehCh7udZoHj1VAZ6dx8DgAN5Rfsulq8R41uiokZ6VbwK2OhK7t 7YQ3m0tt/4kriS8hNBkdr8PXEkIXdMejiRGSvMSvaKwa8wKw+D7s8UdNF3P/QPLKeZzG TXTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=W56NGDFz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id pc13-20020a17090b3b8d00b00250a2c9a793si8688849pjb.152.2023.06.13.00.31.06; Tue, 13 Jun 2023 00:31:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=W56NGDFz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235139AbjFMHHO (ORCPT + 99 others); Tue, 13 Jun 2023 03:07:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239925AbjFMHGw (ORCPT ); Tue, 13 Jun 2023 03:06:52 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B74E1FEF; Tue, 13 Jun 2023 00:06:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686639974; x=1718175974; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T7Y/2YDTllTUUHSl2rDvQC/p9LxvbkgfdDNcPx1ZDwk=; b=W56NGDFzdQUEk2V7l+W7EBL6Z095Z1fzJXCzsojLZONmVpAAOkcrFsEv eDG0kelD+86BUgflzPxqDxAzG71tAULB35u2KrNn7Jz4YNWTPfVNCVT9d 61gwNYGRyD2yoSQxDVKJNUjlM2IjzwhFB8oBuHD6Z9vXkUlG3nmfBm34D 8yVLUnhOtyW/wPLLvIIFQQVvI2lHTaw+W4dIxFNAX3VuuriP8OvN8cvD+ sZHJaoOTOHdBE0dnBJ3efncdBzwTRpU6uESyB6mz05XazwtgcY84pTD4E UB7LTy4G6KrBnDnnVSQZGnHvP05oyYZBrz6f0ihZuMU0s0wpWnc6i/lts Q==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="217554081" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:06:11 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:06:06 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:57 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , CC: , , , , , , , Manikandan , Durai Manickam KR Subject: [PATCH 7/9] drm: atmel-hlcdc: add DPI mode support for XLCDC Date: Tue, 13 Jun 2023 12:34:24 +0530 Message-ID: <20230613070426.467389-8-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768571774712126882?= X-GMAIL-MSGID: =?utf-8?q?1768571774712126882?= Add support for Display Pixel Interface (DPI) Compatible Mode support in atmel-hlcdc driver for XLCDC IP along with legacy pixel mapping.DPI mode BIT is configured in LCDC_CFG5 register. Signed-off-by: Manikandan Muralidharan [durai.manickamkr@microchip.com: update DPI mode bit using is_xlcdc flag] Signed-off-by: Durai Manickam KR --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 7c9cf7c0c75d..abdece982507 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -30,10 +30,12 @@ * * @base: base CRTC state * @output_mode: RGBXXX output mode + * @dpi: output DPI mode */ struct atmel_hlcdc_crtc_state { struct drm_crtc_state base; unsigned int output_mode; + bool dpi; }; static inline struct atmel_hlcdc_crtc_state * @@ -138,6 +140,8 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); cfg = state->output_mode << 8; + if (crtc->dc->is_xlcdc) + cfg |= state->dpi << 11; if (!crtc->dc->is_xlcdc && (adj->flags & DRM_MODE_FLAG_NVSYNC)) cfg |= ATMEL_HLCDC_VSPOL; @@ -150,7 +154,9 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE | ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY | ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO | - ATMEL_HLCDC_GUARDTIME_MASK | ATMEL_HLCDC_MODE_MASK, + ATMEL_HLCDC_GUARDTIME_MASK | + (crtc->dc->is_xlcdc ? ATMEL_XLCDC_MODE_MASK | + ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK), cfg); clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); @@ -344,7 +350,15 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) hstate = drm_crtc_state_to_atmel_hlcdc_crtc_state(state); hstate->output_mode = fls(output_fmts) - 1; - + if (crtc->dc->is_xlcdc) { + /* check if MIPI DPI bit needs to be set */ + if (fls(output_fmts) > 3) { + hstate->output_mode -= 4; + hstate->dpi = true; + } else { + hstate->dpi = false; + } + } return 0; } @@ -448,7 +462,7 @@ static struct drm_crtc_state * atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc) { struct atmel_hlcdc_crtc_state *state, *cur; - + struct atmel_hlcdc_crtc *c = drm_crtc_to_atmel_hlcdc_crtc(crtc); if (WARN_ON(!crtc->state)) return NULL; @@ -459,6 +473,8 @@ atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc) cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state); state->output_mode = cur->output_mode; + if (c->dc->is_xlcdc) + state->dpi = cur->dpi; return &state->base; } From patchwork Tue Jun 13 07:04:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 107119 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp360858vqr; Tue, 13 Jun 2023 00:27:36 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4mRq5fwZ7p/VjgYEBuKaU1QtVXXlJdR/gvpZIhU76b5SRUllFDwJ3dG8uNNyh+Yjjv2mBW X-Received: by 2002:a05:6a20:428b:b0:111:ee3b:59b1 with SMTP id o11-20020a056a20428b00b00111ee3b59b1mr12457540pzj.2.1686641256667; Tue, 13 Jun 2023 00:27:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686641256; cv=none; d=google.com; s=arc-20160816; b=0Udf5elaNdAK6w4h2JCH2FywhQWP+Honb7IZDBzLmc3RE0INl5C+sFd7UYzFxmkZgV Ft2ElHwxNQYIZwzl8gYJRQg3MV4/yCo5k4DcQzW/Bl6VtcTNWbcbpdiDNauaKEqHNQin 6JRCwaw51zvE+O5b6JBZFGV+Em3pdvlQapdb+RO2TR8IGA7NoTeTVSjg+zeoIz1O/1Dj dbGwcWz5wzaOjYDQk/uXgeEygFwEu83NPWYdkuR6UKB3SlZfi0gaodiPLmnOGN3vndn+ 9eLHm4Rzsvus/NrDVwIM6b+vwC+VeaUpdhyprpD8QshRTx8dT+qMPe7EO7zylfc7ZggA Ocyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Fvz2dYJMeiiQeGebM1sec+xiafj4LkbWST3rnsWkMIU=; b=rjvgOZCYQu5cqWlMUHbtN+DCFCpV+CRkvefHsN7brJD+cDQdnRWi0KjXMfS/Hh6jxR AhxMaNOxknrHl9j+fiw/EvG/Iqb79ayzcACSscaZVRq3c2atNFOUl5WStm2t01oOYF66 4br54/juFkIEmdvXaunVQb9kLoLArXURRuejIUdQ5wbw35RQ/xZIeKQZPrDAngzqSsED ksZ8duCazlXxjzoHVJbd6H03JKXR9LZRACAtftSOKV7pd+DemyWzmTv0rbcamuBYeB01 j2Dyi6NLGpuQ4B8nO/yL1GGcLve5nH/W6sJc3z/PoU22H64UW6DFHiDuD6hubDURknMy gGtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=vdUibDuR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j18-20020a633c12000000b0053045e0307esi8012421pga.451.2023.06.13.00.27.24; Tue, 13 Jun 2023 00:27:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=vdUibDuR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240434AbjFMHHZ (ORCPT + 99 others); Tue, 13 Jun 2023 03:07:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240424AbjFMHG6 (ORCPT ); Tue, 13 Jun 2023 03:06:58 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29B081985; Tue, 13 Jun 2023 00:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686639979; x=1718175979; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NtZ1w67xZL59awaoTi+PT78oJSyEe138AbnOfIJ/pYE=; b=vdUibDuRWk/PHROamlm0fMa5/mERNIgi3kwTbT47CimZDXEGHH6MQOZh pDKMNbdoazSZ+HFCZVtkqm3wqYecOCRehK+Ulx8HwGmkJp4/QLtu52J9R VuLHD72HUiGMB0J8i3kXohiHJyBUiDwwMMRDxZ/xBFXo9y3y+peSM2xpt BS1TfkznVw2hraTLqnobqGH1kBWopNC53UzXp78vVqmlI7HjAnHqfB0E5 efATYzI730SZXOD9DqOicXxTS+mDr1H5jwrKUcbtz0QkqBpOIiMjWmPmZ PqL7dmdb2Yfmug573YJOZ76Im2e+LkyCjJHtZKQUQkE6FBslSzIuezsJv g==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="229806934" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:06:16 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:06:14 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:06:06 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , CC: , , , , , , , Manikandan Subject: [PATCH 8/9] drm: atmel-hlcdc: add vertical and horizontal scaling support for XLCDC Date: Tue, 13 Jun 2023 12:34:25 +0530 Message-ID: <20230613070426.467389-9-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768571542294270782?= X-GMAIL-MSGID: =?utf-8?q?1768571542294270782?= update the LCDC_HEOCFG30 and LCDC_HEOCFG31 registers of XLCDC IP which supports vertical and horizontal scaling with Bilinear and Bicubic co-efficients taps for Chroma and Luma componenets of the Pixel. Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 2 ++ drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 4 ++++ .../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 18 ++++++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index fbbd2592efc7..8fcaa4023155 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -536,6 +536,8 @@ static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x7_layers[] = { .general_config = 12, .csc = 16, .scaler_config = 23, + .vxs_config = 30, + .hxs_config = 31, }, .clut_offset = 0x1300, }, diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index 804e4d476f2b..9aedfd0f6039 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -264,6 +264,8 @@ * @disc_pos: discard area position register * @disc_size: discard area size register * @csc: color space conversion register + * @vxs_config: vertical scalar filter taps control register + * @hxs_config: horizontal scalar filter taps control register */ struct atmel_hlcdc_layer_cfg_layout { int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES]; @@ -283,6 +285,8 @@ struct atmel_hlcdc_layer_cfg_layout { int disc_pos; int disc_size; int csc; + int vxs_config; + int hxs_config; }; /** diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index fe33476818c4..613382baa553 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -961,6 +961,24 @@ static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) desc->layout.csc + 6, 0x00000007); } + if (desc->layout.vxs_config && desc->layout.hxs_config) { + /* + * Updating vxs.config and hxs.config fixes the + * Green Color Issue in SAM9X7 EGT Video Player App + */ + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.vxs_config, + ATMEL_XLCDC_LAYER_VXSYCFG_ONE | + ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE | + ATMEL_XLCDC_LAYER_VXSCCFG_ONE | + ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.hxs_config, + ATMEL_XLCDC_LAYER_HXSYCFG_ONE | + ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE | + ATMEL_XLCDC_LAYER_HXSCCFG_ONE | + ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE); + } } return 0; From patchwork Tue Jun 13 07:04:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 107122 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp362007vqr; Tue, 13 Jun 2023 00:30:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7051lr8XFFsHLweNe7pmWy3qPapnYwgdmP6mEyV/lOZiEBz4+Rjh0Fgt6Pqgppuh0ygOgf X-Received: by 2002:a05:6359:b82:b0:127:f2e0:9c2c with SMTP id gf2-20020a0563590b8200b00127f2e09c2cmr5608782rwb.0.1686641447149; Tue, 13 Jun 2023 00:30:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686641447; cv=none; d=google.com; s=arc-20160816; b=I88StXcpHN/YAyEqNlV4wQwdakTbcHxPOR81SkSIWqgmmW08Fi6hKDLQdmIPwy44l9 ao3tvIp9gRL8oBQibDyx8+X/EkEvreDKQ9FIJXIGe843MsC76ehs566KoBkLuXYHilLx p+yaer8fllyitQq+zWG2yQsWlNewJ6g8PBnqjCY7/mFyFdIetXjcQLMph6PCs58L8IB/ p3wPqXNXoPRucLIlZ/DLk487ZlJMso74A/2emkE7hLKwSfsq5T1A+7RcFqmsP8CzYbGN HmCGOGz83U/N1sSvtSXkmuPkYbfDm5BYiJgjDRojod2DeOXZKAFy2ZVwGy9AXqm1Sxrv Q5Cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XW+A/T5Pg1SM/GoreO2Xn/Of9+WN8EU9Ngae/Q4Zamg=; b=SjswXT+2ifW2b+StDVRQOGph2nshXvnuU/dwfQW/yfZ/PVhU8s8/Z+XOdZW4elTXe5 Hb3Ov4PIIhtC3+wxBPRZvPHQc5jVgQOeNwnHiZjf2nkcWL5lRbkRq74XIT/Aqdf0ZaPf KWSxI+dbg9AjAqOO8KTQzZijSiNDfzdTM8EtakXH3lNlNHlwbb77sOktKw7MoHJt9HRR XUqy0jw7qWvK1mvlgfvead8w7oFokSGaMWB9s/njTb8O6mA6dSXxWBYIk3RuSg5PVARz xBw0mfFIagdgwGyV4aiE2T4o1HlEpy+j5jzJKvGwdsOOx6Lo0u+MdMihqjcBwbUvWuvE +fFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=njZ3YTL8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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13 Jun 2023 00:06:24 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:06:23 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:06:15 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , CC: , , , , , , , Manikandan , Durai Manickam KR Subject: [PATCH 9/9] drm: atmel-hlcdc: add support for DSI output formats Date: Tue, 13 Jun 2023 12:34:26 +0530 Message-ID: <20230613070426.467389-10-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768571742050336575?= X-GMAIL-MSGID: =?utf-8?q?1768571742050336575?= Add support for the following DPI mode if the encoder type is DSI as per the XLCDC IP datasheet: - 16BPPCFG1 - 16BPPCFG2 - 16BPPCFG3 - 18BPPCFG1 - 18BPPCFG2 - 24BPP Signed-off-by: Manikandan Muralidharan [durai.manickamkr@microchip.com: update output format using is_xlcdc flag] Signed-off-by: Durai Manickam KR --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 117 +++++++++++++----- 1 file changed, 86 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index abdece982507..dc8361ebf05b 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -265,11 +265,18 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, } -#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) -#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1) -#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2) -#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3) -#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0) +#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) +#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1) +#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2) +#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3) +#define ATMEL_HLCDC_DPI_RGB565C1_OUTPUT BIT(4) +#define ATMEL_HLCDC_DPI_RGB565C2_OUTPUT BIT(5) +#define ATMEL_HLCDC_DPI_RGB565C3_OUTPUT BIT(6) +#define ATMEL_HLCDC_DPI_RGB666C1_OUTPUT BIT(7) +#define ATMEL_HLCDC_DPI_RGB666C2_OUTPUT BIT(8) +#define ATMEL_HLCDC_DPI_RGB888_OUTPUT BIT(9) +#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0) +#define ATMEL_XLCDC_OUTPUT_MODE_MASK GENMASK(9, 0) static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) { @@ -283,37 +290,83 @@ static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) if (!encoder) encoder = connector->encoder; - switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { - case 0: - break; - case MEDIA_BUS_FMT_RGB444_1X12: - return ATMEL_HLCDC_RGB444_OUTPUT; - case MEDIA_BUS_FMT_RGB565_1X16: - return ATMEL_HLCDC_RGB565_OUTPUT; - case MEDIA_BUS_FMT_RGB666_1X18: - return ATMEL_HLCDC_RGB666_OUTPUT; - case MEDIA_BUS_FMT_RGB888_1X24: - return ATMEL_HLCDC_RGB888_OUTPUT; - default: - return -EINVAL; - } - - for (j = 0; j < info->num_bus_formats; j++) { - switch (info->bus_formats[j]) { - case MEDIA_BUS_FMT_RGB444_1X12: - supported_fmts |= ATMEL_HLCDC_RGB444_OUTPUT; + if (encoder->encoder_type == DRM_MODE_ENCODER_DSI) { + /* + * atmel-hlcdc to support DSI formats with DSI video pipeline + * when DRM_MODE_ENCODER_DSI type is set by + * connector driver component. + */ + switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { + case 0: break; case MEDIA_BUS_FMT_RGB565_1X16: - supported_fmts |= ATMEL_HLCDC_RGB565_OUTPUT; - break; + return ATMEL_HLCDC_DPI_RGB565C1_OUTPUT; case MEDIA_BUS_FMT_RGB666_1X18: - supported_fmts |= ATMEL_HLCDC_RGB666_OUTPUT; - break; + return ATMEL_HLCDC_DPI_RGB666C1_OUTPUT; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + return ATMEL_HLCDC_DPI_RGB666C2_OUTPUT; case MEDIA_BUS_FMT_RGB888_1X24: - supported_fmts |= ATMEL_HLCDC_RGB888_OUTPUT; - break; + return ATMEL_HLCDC_DPI_RGB888_OUTPUT; default: + return -EINVAL; + } + + for (j = 0; j < info->num_bus_formats; j++) { + switch (info->bus_formats[j]) { + case MEDIA_BUS_FMT_RGB565_1X16: + supported_fmts |= + ATMEL_HLCDC_DPI_RGB565C1_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + supported_fmts |= + ATMEL_HLCDC_DPI_RGB666C1_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + supported_fmts |= + ATMEL_HLCDC_DPI_RGB666C2_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB888_1X24: + supported_fmts |= + ATMEL_HLCDC_DPI_RGB888_OUTPUT; + break; + default: + break; + } + } + + } else { + switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { + case 0: break; + case MEDIA_BUS_FMT_RGB444_1X12: + return ATMEL_HLCDC_RGB444_OUTPUT; + case MEDIA_BUS_FMT_RGB565_1X16: + return ATMEL_HLCDC_RGB565_OUTPUT; + case MEDIA_BUS_FMT_RGB666_1X18: + return ATMEL_HLCDC_RGB666_OUTPUT; + case MEDIA_BUS_FMT_RGB888_1X24: + return ATMEL_HLCDC_RGB888_OUTPUT; + default: + return -EINVAL; + } + + for (j = 0; j < info->num_bus_formats; j++) { + switch (info->bus_formats[j]) { + case MEDIA_BUS_FMT_RGB444_1X12: + supported_fmts |= ATMEL_HLCDC_RGB444_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB565_1X16: + supported_fmts |= ATMEL_HLCDC_RGB565_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + supported_fmts |= ATMEL_HLCDC_RGB666_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB888_1X24: + supported_fmts |= ATMEL_HLCDC_RGB888_OUTPUT; + break; + default: + break; + } } } @@ -322,7 +375,7 @@ static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) { - unsigned int output_fmts = ATMEL_HLCDC_OUTPUT_MODE_MASK; + unsigned int output_fmts; struct atmel_hlcdc_crtc_state *hstate; struct drm_connector_state *cstate; struct drm_connector *connector; @@ -330,6 +383,8 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) int i; crtc = drm_crtc_to_atmel_hlcdc_crtc(state->crtc); + output_fmts = crtc->dc->is_xlcdc ? ATMEL_XLCDC_OUTPUT_MODE_MASK : + ATMEL_HLCDC_OUTPUT_MODE_MASK; for_each_new_connector_in_state(state->state, connector, cstate, i) { unsigned int supported_fmts = 0;