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[8.43.85.97]) by mx.google.com with ESMTPS id l13-20020aa7c3cd000000b0045c26f0050esi1157540edr.238.2022.10.27.03.57.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 03:57:15 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="Iz/xoOXr"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E4C43382EA3B for ; Thu, 27 Oct 2022 10:57:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E4C43382EA3B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666868233; bh=T4CB7A1vlO3kFX46Z0pZAspN5Bs09PapvJ49ax4X6gU=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=Iz/xoOXrGQaA/g1LJk618GbkOcvmBqKZxnKPDOowCwjg84PbN9qe/ku8BLzSkvhlb cTYjD9uUXiRMu2uDg0p9QpVfeEH1zPUJMEVfBidqnXSaPm/bdACtaGwP3BuvcksGCe zSPG6P7DPxCsKc5KnlXkp3RvIyAN0/vjpPYZl3xk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 298DB3857031 for ; Thu, 27 Oct 2022 10:56:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 298DB3857031 X-IronPort-AV: E=McAfee;i="6500,9779,10512"; a="308184910" X-IronPort-AV: E=Sophos;i="5.95,217,1661842800"; d="scan'208";a="308184910" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2022 03:55:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10512"; a="610322576" X-IronPort-AV: E=Sophos;i="5.95,217,1661842800"; d="scan'208";a="610322576" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga006.jf.intel.com with ESMTP; 27 Oct 2022 03:55:54 -0700 Received: from shliclel4051.sh.intel.com (shliclel4051.sh.intel.com [10.239.240.51]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 54E2110056DD; Thu, 27 Oct 2022 18:55:54 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH] [x86] Fix incorrect digit constraint Date: Thu, 27 Oct 2022 18:53:54 +0800 Message-Id: <20221027105354.3151191-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747838026634848133?= X-GMAIL-MSGID: =?utf-8?q?1747838026634848133?= Matching constraints are used in these circumstances. More precisely, the two operands that match must include one input-only operand and one output-only operand. Moreover, the digit must be a smaller number than the number of the operand that uses it in the constraint. In pr107057, the 2 operands in the pattern are both input operands. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR target/107057 * config/i386/sse.md (*vec_interleave_highv2df): Remove constraint 1. (*vec_interleave_lowv2df): Ditto. (vec_concatv2df): Ditto. * config/i386/i386.cc (ix86_vec_interleave_v2df_operator_ok): Disallow MEM_P (op1) && MEM_P (op2). gcc/testsuite/ChangeLog: * gcc.target/i386/pr107057.c: New test. --- gcc/config/i386/i386.cc | 2 +- gcc/config/i386/sse.md | 68 +++++++++++------------- gcc/testsuite/gcc.target/i386/pr107057.c | 19 +++++++ 3 files changed, 50 insertions(+), 39 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr107057.c diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index aeea26ef4be..e3b7bea0d68 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -15652,7 +15652,7 @@ ix86_vec_interleave_v2df_operator_ok (rtx operands[3], bool high) if (MEM_P (operands[0])) return rtx_equal_p (operands[0], operands[1 + high]); if (MEM_P (operands[1]) && MEM_P (operands[2])) - return TARGET_SSE3 && rtx_equal_p (operands[1], operands[2]); + return false; return true; } diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index f4b5506703f..e6fefe39ca2 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12170,29 +12170,28 @@ (define_expand "vec_interleave_highv2df" }) (define_insn "*vec_interleave_highv2df" - [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,v,x,v,m") + [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,x,v,m") (vec_select:V2DF (vec_concat:V4DF - (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,o,o,o,v") - (match_operand:V2DF 2 "nonimmediate_operand" " x,v,1,0,v,0")) + (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,o,o,v") + (match_operand:V2DF 2 "nonimmediate_operand" " x,v,0,v,0")) (parallel [(const_int 1) (const_int 3)])))] "TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 1)" "@ unpckhpd\t{%2, %0|%0, %2} vunpckhpd\t{%2, %1, %0|%0, %1, %2} - %vmovddup\t{%H1, %0|%0, %H1} movlpd\t{%H1, %0|%0, %H1} vmovlpd\t{%H1, %2, %0|%0, %2, %H1} %vmovhpd\t{%1, %0|%q0, %1}" - [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*") - (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov") + [(set_attr "isa" "noavx,avx,noavx,avx,*") + (set_attr "type" "sselog,sselog,ssemov,ssemov,ssemov") (set (attr "prefix_data16") - (if_then_else (eq_attr "alternative" "3,5") + (if_then_else (eq_attr "alternative" "2,4") (const_string "1") (const_string "*"))) - (set_attr "prefix" "orig,maybe_evex,maybe_vex,orig,maybe_evex,maybe_vex") - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")]) + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex") + (set_attr "mode" "V2DF,V2DF,V1DF,V1DF,V1DF")]) (define_expand "avx512f_movddup512" [(set (match_operand:V8DF 0 "register_operand") @@ -12332,29 +12331,28 @@ (define_expand "vec_interleave_lowv2df" }) (define_insn "*vec_interleave_lowv2df" - [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,v,x,v,o") + [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,x,v,o") (vec_select:V2DF (vec_concat:V4DF - (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,m,0,v,0") - (match_operand:V2DF 2 "nonimmediate_operand" " x,v,1,m,m,v")) + (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,0,v,0") + (match_operand:V2DF 2 "nonimmediate_operand" " x,v,m,m,v")) (parallel [(const_int 0) (const_int 2)])))] "TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 0)" "@ unpcklpd\t{%2, %0|%0, %2} vunpcklpd\t{%2, %1, %0|%0, %1, %2} - %vmovddup\t{%1, %0|%0, %q1} movhpd\t{%2, %0|%0, %q2} vmovhpd\t{%2, %1, %0|%0, %1, %q2} %vmovlpd\t{%2, %H0|%H0, %2}" - [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*") - (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov") + [(set_attr "isa" "noavx,avx,noavx,avx,*") + (set_attr "type" "sselog,sselog,ssemov,ssemov,ssemov") (set (attr "prefix_data16") - (if_then_else (eq_attr "alternative" "3,5") + (if_then_else (eq_attr "alternative" "2,4") (const_string "1") (const_string "*"))) - (set_attr "prefix" "orig,maybe_evex,maybe_vex,orig,maybe_evex,maybe_vex") - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")]) + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex") + (set_attr "mode" "V2DF,V2DF,V1DF,V1DF,V1DF")]) (define_split [(set (match_operand:V2DF 0 "memory_operand") @@ -13560,56 +13558,50 @@ (define_insn "vec_dupv2df" (set_attr "mode" "V2DF,DF,DF")]) (define_insn "vec_concatv2df" - [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x, v,x,x") + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,x, v,x,x") (vec_concat:V2DF - (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,vm,0,0") - (match_operand:DF 2 "nonimm_or_0_operand" " x,x,v,1,1,m,m, C,x,m")))] - "TARGET_SSE - && (!(MEM_P (operands[1]) && MEM_P (operands[2])) - || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))" + (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,0,x,vm,0,0") + (match_operand:DF 2 "nonimm_or_0_operand" " x,x,v,m,m, C,x,m")))] + "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ unpcklpd\t{%2, %0|%0, %2} vunpcklpd\t{%2, %1, %0|%0, %1, %2} vunpcklpd\t{%2, %1, %0|%0, %1, %2} - %vmovddup\t{%1, %0|%0, %1} - vmovddup\t{%1, %0|%0, %1} movhpd\t{%2, %0|%0, %2} vmovhpd\t{%2, %1, %0|%0, %1, %2} %vmovq\t{%1, %0|%0, %1} movlhps\t{%2, %0|%0, %2} movhps\t{%2, %0|%0, %2}" [(set (attr "isa") - (cond [(eq_attr "alternative" "0,5") + (cond [(eq_attr "alternative" "0,3") (const_string "sse2_noavx") - (eq_attr "alternative" "1,6") + (eq_attr "alternative" "1,4") (const_string "avx") - (eq_attr "alternative" "2,4") + (eq_attr "alternative" "2") (const_string "avx512vl") - (eq_attr "alternative" "3") - (const_string "sse3") - (eq_attr "alternative" "7") + (eq_attr "alternative" "5") (const_string "sse2") ] (const_string "noavx"))) (set (attr "type") (if_then_else - (eq_attr "alternative" "0,1,2,3,4") + (eq_attr "alternative" "0,1,2") (const_string "sselog") (const_string "ssemov"))) (set (attr "prefix_data16") - (if_then_else (eq_attr "alternative" "5") + (if_then_else (eq_attr "alternative" "3") (const_string "1") (const_string "*"))) (set (attr "prefix") - (cond [(eq_attr "alternative" "1,6") + (cond [(eq_attr "alternative" "1,4") (const_string "vex") - (eq_attr "alternative" "2,4") + (eq_attr "alternative" "2") (const_string "evex") - (eq_attr "alternative" "3,7") + (eq_attr "alternative" "5") (const_string "maybe_vex") ] (const_string "orig"))) - (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")]) + (set_attr "mode" "V2DF,V2DF,V2DF,V1DF,V1DF,DF,V4SF,V2SF")]) ;; vmovq clears also the higher bits. (define_insn "vec_set_0" diff --git a/gcc/testsuite/gcc.target/i386/pr107057.c b/gcc/testsuite/gcc.target/i386/pr107057.c new file mode 100644 index 00000000000..40b49ac21ec --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr107057.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx -mcmodel=large -O3" } */ + +typedef double v2df __attribute__ ((vector_size (16))); +v2df f (double a, double b) +{ + v2df v; + double *c = (double *)&v; + *c = a; + *(c+1) = b; + return v; +} +void g () +{ + v2df x = f (1.0, 1.0); + v2df y = f (2.0, 2.0); + for (;*(double *)&x<=8; x+=y) + g (); +}