From patchwork Thu Jun 8 16:37:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 105047 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp407406vqr; Thu, 8 Jun 2023 09:45:29 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6I3bjcgUsklMjnSiNtOx5XfZURTzhrYPUgx/r9tn2X3mEulA5+9OVBH7U1slbSpIsHYdoG X-Received: by 2002:a05:6a00:982:b0:65c:2ea:2c5e with SMTP id u2-20020a056a00098200b0065c02ea2c5emr7364481pfg.29.1686242729170; Thu, 08 Jun 2023 09:45:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686242729; cv=none; d=google.com; s=arc-20160816; b=x0QxsJGwlF+6tBH+VXxJQHm8dK9JLSkI+4RZyXTNWkBdXuPX/ChwOHy9Xt6uREuEhy pY1LYpcHJQBJVn55AL0cwppzxm2HY2hunQJyR9Cs6noEPQUE9bDAD69BbL6YI8WDcsZC vRrEi96kV7Y94QlaYfmATAXuoTj0EQFndCJQn8zmy5vyCp9aiSIVmg4ODvFUygNM4g07 nm6G7zGe+hallMAEzPpLuZ0hmVWM1APawkNFH2AMhQlgldTD+/fo71pfNzrCRJv/iqya xEW1iYkgc/T3LcX/xyunhdUF1TCzxjBJPVrbkJh0YVt28V0u/NL0fffRt+/qwxDlYigV r1hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fto8hspIWYbudCmEl2g6ecL/UhlQpTiwRoj5dazNq+E=; b=jxz8da0z6xOe5Y0YXomNSkQpNq6Wudp37KJsHWziBq7sdZ63walQKHo/Owmf6wI0A2 45ArfBN6zVdOk41Ik8rMcVHEvbwGWBpg6zaqeONTZCzYRYx7EaVSffcD+kIauxbmK9HL GJtCAE11LOAdPFhKjHIix6yuhmUoTcf3/Nh6EI5/8NEvNF5zOMub7m2gxpC3Zum4XAUv Pm65xSKdsTapRN5IvV9atml5KvUuYD89Irdlzj+6FH+UGfKQ1CZukltl7Uju8LMvCBWG 7LeS6k6YIN8DsW1B+efCrvRxluRjTWk6kPLpbgYqhD88W1dP92SK5eXQOnUtStDgZjWV VM6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=yjZCdYec; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h125-20020a625383000000b0065290aa261dsi1086593pfb.22.2023.06.08.09.45.16; Thu, 08 Jun 2023 09:45:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=yjZCdYec; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235799AbjFHQjF (ORCPT + 99 others); Thu, 8 Jun 2023 12:39:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234916AbjFHQjA (ORCPT ); Thu, 8 Jun 2023 12:39:00 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CE1D30FA; Thu, 8 Jun 2023 09:38:34 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 358GbbNS115695; Thu, 8 Jun 2023 11:37:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1686242257; bh=fto8hspIWYbudCmEl2g6ecL/UhlQpTiwRoj5dazNq+E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yjZCdYecCqlAfAByHrEBHPQ46JbIDet0HySG5g4tlTO8ToNCtOrdBEP8Lh9YsF8eQ rlI5HTv/e0wwJbPunaMQrHN6oM8k6Li0HzGF1jXHKletw92au7WdAOTEQBstJ2KP2z cT7ATZeBN3QAVhtFA97yk8QZvzRD0TTXtdeEDd1g= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 358Gbbkn111920 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Jun 2023 11:37:37 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 Jun 2023 11:37:37 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 Jun 2023 11:37:37 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 358GbZV7024680; Thu, 8 Jun 2023 11:37:36 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: DRI Development List , Devicetree List , Linux Kernel List , Nishanth Menon , Vignesh Raghavendra , Rahul T R , Devarsh Thakkar , Jayesh Choudhary , Aradhya Bhatia Subject: [PATCH v8 1/2] dt-bindings: display: ti,am65x-dss: Add am625 dss compatible Date: Thu, 8 Jun 2023 22:07:33 +0530 Message-ID: <20230608163734.2578-2-a-bhatia1@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608163734.2578-1-a-bhatia1@ti.com> References: <20230608163734.2578-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768153656224268757?= X-GMAIL-MSGID: =?utf-8?q?1768153656224268757?= The DSS controller on TI's AM625 SoC is an update from that on TI's AM65X SoC. The former has an additional OLDI TX on its first video port that helps output cloned video or WUXGA (1920x1200@60fps) resolution video output over a dual-link mode to reduce the required OLDI clock output. The second video port is same from AM65x DSS and it outputs DPI video data. It can support 2K resolutions @ 60fps, independently. Add the new controller's compatible and update descriptions. Signed-off-by: Aradhya Bhatia Acked-by: Krzysztof Kozlowski Reviewed-by: Tomi Valkeinen --- Notes: Changes from v7: * Drop the 3rd port property and update descriptions. * Drop the Reviewed-by tags of Krzysztof Kozlowski and Rahul T R because of the changes. .../bindings/display/ti/ti,am65x-dss.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index b6b402f16161..ae09cd3cbce1 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -12,14 +12,18 @@ maintainers: - Tomi Valkeinen description: | - The AM65x TI Keystone Display SubSystem with two output ports and - two video planes. The first video port supports OLDI and the second - supports DPI format. The fist plane is full video plane with all - features and the second is a "lite plane" without scaling support. + The AM625 and AM65x TI Keystone Display SubSystem with two output + ports and two video planes. In AM65x DSS, the first video port + supports 1 OLDI TX and in AM625 DSS, the first video port output is + internally routed to 2 OLDI TXes. The second video port supports DPI + format. The first plane is full video plane with all features and the + second is a "lite plane" without scaling support. properties: compatible: - const: ti,am65x-dss + enum: + - ti,am625-dss + - ti,am65x-dss reg: description: @@ -80,7 +84,9 @@ properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: - The DSS OLDI output port node form video port 1 + For AM65x DSS, the OLDI output port node from video port 1. + For AM625 DSS, the internal DPI output port node from video + port 1. port@1: $ref: /schemas/graph.yaml#/properties/port From patchwork Thu Jun 8 16:37:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 105054 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp411834vqr; Thu, 8 Jun 2023 09:53:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4Czs72pPjRjQskkhS4Ny5N+H7fuBRwW7GxP5WO4YlECNiIWUqrwfukKXucbT6y0Erl8T5F X-Received: by 2002:a05:6a21:1191:b0:10f:f8e2:183c with SMTP id oj17-20020a056a21119100b0010ff8e2183cmr4496394pzb.51.1686243218208; Thu, 08 Jun 2023 09:53:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686243218; cv=none; d=google.com; s=arc-20160816; b=UMX+sXMH5Qbny97Al3auTM4Spgat8vTbt9pP4D8t3rC7uhSHJpy8+XhEaIi/Wo7qm9 D2s1kIgtAd+SYHH8Q9mDt49u0B4/u+mCFV3xsf63ZmGvt2zKsLoTicrya+lGs7P7m6v9 HXSN8ZYzblitcH+Dhn1TdDbdLDUTi49DFLC27/pj/S3deq3HACCbZ719NZkaYzAmHq5Y sZe6SUjmhzPXWfUSPTj/5gAFZn1czhIDpDiROjES69TJngXQgqovjgrxYYDu9YGJ8UPS Ay3E1KRIGj5qZ7UB/ERAvPAPu6mynGJ5JkEk4T07GxR65Ag5zXPguJN9DVDCGvjSekxR ITjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=63yTje9gSZ+jL3DeHEsDLsQhdq8Nwny9LUmnTnUGE+M=; b=M3eZelvasHGKhhlQi35f6DzTBnOoUxB1puQ3rqNhvFNrrwyI7aDIpiWnhAxxbHglCC gKNpI+nMswiF86VV+jxn02OjquIQlYXO6OqQlUp6RA+xBgycy0SbsJDW5AXoAQjORxwX GNSxSpd7pHFiB0/cQcNaOru4GlaBNe5D8Y8IFMUaGIzhrlZGcE/lE8B9T+QvUnxHFCHI VENiYMhdtKSfpENKryDwkSOjZqejnr9wvMfYTSHL1EL44yhJwuLyVz5f2khVXY+DCWA5 KzoeuUptqjleOpufDRz2UAKd4FADFn9VA4GYLBJT6UACYm7uGm9Nfzq1nJkgXYtN9ddx MhCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mMb7qYCP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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The AM625 DSS supports 2 video planes connecting to 2 video ports. The first plane is a full plane supporting all the features, while the 2nd plane is a "lite" plane without scaling support. The first video port in AM625 DSS internally provides DPI output to 2 OLDI transmitters. Each OLDI TX outputs 4 differential lanes of video output and 1 of clock output. The second video port outputs DPI data directly out of the SoC. It has 24 data lines and can support a maximum of RGB888 output bus format. Signed-off-by: Aradhya Bhatia Reviewed-by: Tomi Valkeinen --- Notes: Changes from v7: * Drop all changes made after v3. - Drop output bus type support. All outputs from DSS will be the video port outptus. * Make the first video port type as INTERNAL from OLDI. drivers/gpu/drm/tidss/tidss_dispc.c | 57 ++++++++++++++++++++++++++++- drivers/gpu/drm/tidss/tidss_dispc.h | 2 + drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index dca077411f77..484da1aa27bb 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -275,6 +275,55 @@ const struct dispc_features dispc_j721e_feats = { .vid_order = { 1, 3, 0, 2 }, }; +const struct dispc_features dispc_am625_feats = { + .max_pclk_khz = { + [DISPC_VP_DPI] = 165000, + [DISPC_VP_INTERNAL] = 170000, + }, + + .scaling = { + .in_width_max_5tap_rgb = 1280, + .in_width_max_3tap_rgb = 2560, + .in_width_max_5tap_yuv = 2560, + .in_width_max_3tap_yuv = 4096, + .upscale_limit = 16, + .downscale_limit_5tap = 4, + .downscale_limit_3tap = 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max = 32, + }, + + .subrev = DISPC_AM625, + + .common = "common", + .common_regs = tidss_am65x_common_regs, + + .num_vps = 2, + .vp_name = { "vp1", "vp2" }, + .ovr_name = { "ovr1", "ovr2" }, + .vpclk_name = { "vp1", "vp2" }, + .vp_bus_type = { DISPC_VP_INTERNAL, DISPC_VP_DPI }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size = 256, + .gamma_type = TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes = 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name = { "vid", "vidl1" }, + .vid_lite = { false, true, }, + .vid_order = { 1, 0 }, +}; + static const u16 *dispc_common_regmap; struct dss_vp_data { @@ -776,6 +825,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) switch (dispc->feat->subrev) { case DISPC_K2G: return dispc_k2g_read_and_clear_irqstatus(dispc); + case DISPC_AM625: case DISPC_AM65X: case DISPC_J721E: return dispc_k3_read_and_clear_irqstatus(dispc); @@ -791,6 +841,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) case DISPC_K2G: dispc_k2g_set_irqenable(dispc, mask); break; + case DISPC_AM625: case DISPC_AM65X: case DISPC_J721E: dispc_k3_set_irqenable(dispc, mask); @@ -1281,6 +1332,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); break; + case DISPC_AM625: case DISPC_AM65X: dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); @@ -2199,6 +2251,7 @@ static void dispc_plane_init(struct dispc_device *dispc) case DISPC_K2G: dispc_k2g_plane_init(dispc); break; + case DISPC_AM625: case DISPC_AM65X: case DISPC_J721E: dispc_k3_plane_init(dispc); @@ -2305,6 +2358,7 @@ static void dispc_vp_write_gamma_table(struct dispc_device *dispc, case DISPC_K2G: dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); break; + case DISPC_AM625: case DISPC_AM65X: dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); break; @@ -2579,7 +2633,8 @@ int dispc_runtime_resume(struct dispc_device *dispc) REG_GET(dispc, DSS_SYSSTATUS, 2, 2), REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); - if (dispc->feat->subrev == DISPC_AM65X) + if (dispc->feat->subrev == DISPC_AM625 || + dispc->feat->subrev == DISPC_AM65X) dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", REG_GET(dispc, DSS_SYSSTATUS, 5, 5), REG_GET(dispc, DSS_SYSSTATUS, 6, 6), diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index 946ed769caaf..33ac5ad7a423 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -59,6 +59,7 @@ enum dispc_vp_bus_type { enum dispc_dss_subrevision { DISPC_K2G, + DISPC_AM625, DISPC_AM65X, DISPC_J721E, }; @@ -86,6 +87,7 @@ struct dispc_features { }; extern const struct dispc_features dispc_k2g_feats; +extern const struct dispc_features dispc_am625_feats; extern const struct dispc_features dispc_am65x_feats; extern const struct dispc_features dispc_j721e_feats; diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c index 3f5f27fb6ebc..0a6f19314662 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -232,6 +232,7 @@ static void tidss_shutdown(struct platform_device *pdev) static const struct of_device_id tidss_of_table[] = { { .compatible = "ti,k2g-dss", .data = &dispc_k2g_feats, }, + { .compatible = "ti,am625-dss", .data = &dispc_am625_feats, }, { .compatible = "ti,am65x-dss", .data = &dispc_am65x_feats, }, { .compatible = "ti,j721e-dss", .data = &dispc_j721e_feats, }, { }