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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r8-20020aa79628000000b00660b5630927si62306pfg.133.2023.06.07.19.21.33; Wed, 07 Jun 2023 19:21:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233256AbjFHCQc (ORCPT + 99 others); Wed, 7 Jun 2023 22:16:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232670AbjFHCQa (ORCPT ); Wed, 7 Jun 2023 22:16:30 -0400 Received: from mail.aspeedtech.com (mail.aspeedtech.com [211.20.114.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C964926A3; Wed, 7 Jun 2023 19:16:28 -0700 (PDT) Received: from BillyTsai-pc.aspeed.com (192.168.1.221) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Jun 2023 10:16:21 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , , , , , Subject: [v6 1/4] dt-bindings: pwm: Add ASPEED PWM Control documentation Date: Thu, 8 Jun 2023 10:18:36 +0800 Message-ID: <20230608021839.12769-2-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230608021839.12769-1-billy_tsai@aspeedtech.com> References: <20230608021839.12769-1-billy_tsai@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.1.221] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768099317241068639?= X-GMAIL-MSGID: =?utf-8?q?1768099317241068639?= Document the compatible for aspeed,ast2600-pwm device. Signed-off-by: Billy Tsai --- .../bindings/pwm/aspeed,ast2600-pwm.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml b/Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml new file mode 100644 index 000000000000..a9e040263578 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2021 Aspeed, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/aspeed,ast2600-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed Ast2600 PWM controller + +maintainers: + - Billy Tsai + +description: | + The Aspeed PWM controller supports up to 1 PWM outputs. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - aspeed,ast2600-pwm + + "#pwm-cells": + const: 3 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - clocks + - resets + +additionalProperties: false From patchwork Thu Jun 8 02:18:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 104798 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp616915vqr; Wed, 7 Jun 2023 19:20:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5p/RjP980pJyjX2rvfeHwkUhaFCapMaj3nk2n86ZMA/y3Kf87O/eUA2pY/BzCm4CmWbp9j X-Received: by 2002:aca:110f:0:b0:398:2c03:45fc with SMTP id 15-20020aca110f000000b003982c0345fcmr6185564oir.15.1686190842492; Wed, 07 Jun 2023 19:20:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686190842; cv=none; d=google.com; s=arc-20160816; b=TGvUew8DKtnK94RJdY6aAK5iUavuD27KWDeQjhB1nJh7hOJUOVtKFCyVzl6+CsB8Ja Cli5WaBF+d2ph/AxM20MJ4u1VYe5QbzGzcRpS+xfwY7LODNrQPQK/7LGjwuMCqVbYlup UHQl3kzPmH0KdvOVLiC8O8Ddjn+omU0G2qd34yxqRcqDn3XcSzvBeDWMqiZ9XK9S4wpE Pqby/qM3cZD6lJ+gjW55kDP/B7UKzcK7LGxabmn0Ct/hj0PoZGpM3nCOpcDdDUaPg1es +MDuuPW3JEcdPjCuRhRfY/5eii/AvjjCWDeEEFGbPczTKi9IoqGKzNGazH3g39K/L4qZ K4iA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from; bh=XrZF/fJ5607/Mbvv+ay1VNJJmuv3rAKzSFAo0Chw5wY=; b=CLIAxhxeDwNTDzt1p4qbkZlw+0pu3j7vVX+EwT00qKEalFfKzV5A3KGKlj9SQ2bgIJ M/MmVWL6d1rGQD4M+bzJ3zvW32Nfozqynn7ZMQp0CyTfF00WwZkia6P75jsv1DNWnRKO 5+lIDji7+IZT3q6LfUBlDhLs2Yp07j7ND1d49EFP4mej0Ii3CoP5NpLEjZCn2/dB2A+C VJvJ0pDGgsNNIC/Jl2lfvWjasiJ93TD7y2FtWpDJeeGR4SPSNW+pk6jtye7S/6gxH17k em0inEHdh5R2+sOwBMdKid+mZ88c1QEII45LWUfS79wopj+04NVpzRfWVvK/ft1rCUSW RUNg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Billy Tsai --- .../bindings/hwmon/aspeed,ast2600-tach.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml diff --git a/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml b/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml new file mode 100644 index 000000000000..627aa00f2e92 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2021 Aspeed, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/aspeed,ast2600-tach.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed Ast2600 Tach controller + +maintainers: + - Billy Tsai + +description: | + The Aspeed Tach controller can support upto 1 fan input. + +properties: + compatible: + enum: + - aspeed,ast2600-tach + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - clocks + - resets + +additionalProperties: false From patchwork Thu Jun 8 02:18:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 104797 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp616882vqr; Wed, 7 Jun 2023 19:20:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6asVfwXZ1dSqjFm70pYjTLrcnR6fJFcRUIeCeMRTH47RQ8K6jZGrD/JqDXf9AT+RVcgOLI X-Received: by 2002:a92:d5c9:0:b0:33a:b6ca:c4d3 with SMTP id d9-20020a92d5c9000000b0033ab6cac4d3mr9936239ilq.12.1686190838226; Wed, 07 Jun 2023 19:20:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686190838; cv=none; d=google.com; s=arc-20160816; b=lheKhGWbPYjKJFRiFzkyeNAZrCp5vqtpWm62De+ephL6E+Unhg3gfda//mMGi3FUYl ma5K0Kraw4cUx+S+0MwWwMBp+dO9vaSxqaZdJ/Do4udHoVma9JH1PQQbAY9yjdYEHP92 dGEhrNr5xkOA31y4/ZTFGurjaOoY7gXIYPqPI7Sbbf8Sy559YC5snGMJcrST6FMItgqc 59UMO7d4C7079omTcf3WjC+MrIB6EMgtYUujpLH6DONB2lWlcULUNqUkBTDL1PJ+l611 /hLal39KBtCRmBCaGXL6L9gJbG7jSwjm8H1DYJRBp3RnVcEapqQ81Nc+PgeBekjn8CL3 pY0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from; bh=gK2X7M98DSczcPfCqf5wYeuPr0wxmMgk+8LtsJp5nPU=; b=eP5ZTe7ntW8LER7icdqrAQnAJD5Yjp+VUgrX5uFcfUnD2h/EjIrdZbuY2w2+hdtoGJ wzq/UURyctSRnRPjWW8mH4xr4yVJE42zuc5UouocrxmCFmoIHeByaep6x297mpcFpYai L12gS5uaf4lEElmjTYE1ovsBy2NdvKaSnruSCyoElptztZALziY7fGNqMHCf0JY1XiGZ +QpQPO87gunY6sXkgRQNHxiMiwA5vgj1ncNweNNwDs+XpgJkljjovf/M4oimioepifQJ +v/YZic495pv4XXCtylvUmBa64i/XEjNXVJaZiDLDtONhZbrf6P2OsvhcC2KtJUSBbIQ WJdw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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This particular SoC features 16 PWM controllers, with each controller capable of supporting up to 1 PWM output. Signed-off-by: Billy Tsai Reviewed-by: Uwe Kleine-König --- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-aspeed-ast2600.c | 309 +++++++++++++++++++++++++++++++ 3 files changed, 320 insertions(+) create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..54915185d918 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -51,6 +51,16 @@ config PWM_AB8500 To compile this driver as a module, choose M here: the module will be called pwm-ab8500. +config PWM_ASPEED_AST2600 + tristate "Aspeed ast2600 PWM support" + depends on ARCH_ASPEED || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + This driver provides support for Aspeed ast2600 PWM controllers. + + To compile this driver as a module, choose M here: the module + will be called pwm-aspeed-ast2600. + config PWM_ATMEL tristate "Atmel PWM support" depends on ARCH_AT91 || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..5169c34056e6 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_PWM) += core.o obj-$(CONFIG_PWM_SYSFS) += sysfs.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o +obj-$(CONFIG_PWM_ASPEED_AST2600) += pwm-aspeed-ast2600.o obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o diff --git a/drivers/pwm/pwm-aspeed-ast2600.c b/drivers/pwm/pwm-aspeed-ast2600.c new file mode 100644 index 000000000000..ae6eb197e473 --- /dev/null +++ b/drivers/pwm/pwm-aspeed-ast2600.c @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2021 Aspeed Technology Inc. + * + * PWM controller driver for Aspeed ast2600 SoCs. + * This drivers doesn't support earlier version of the IP. + * + * The hardware operates in time quantities of length + * Q := (DIV_L + 1) << DIV_H / input-clk + * The length of a PWM period is (DUTY_CYCLE_PERIOD + 1) * Q. + * The maximal value for DUTY_CYCLE_PERIOD is used here to provide + * a fine grained selection for the duty cycle. + * + * This driver uses DUTY_CYCLE_RISING_POINT = 0, so from the start of a + * period the output is active until DUTY_CYCLE_FALLING_POINT * Q. Note + * that if DUTY_CYCLE_RISING_POINT = DUTY_CYCLE_FALLING_POINT the output is + * always active. + * + * Register usage: + * PIN_ENABLE: When it is unset the pwm controller will emit inactive level to the external. + * Use to determine whether the PWM channel is enabled or disabled + * CLK_ENABLE: When it is unset the pwm controller will assert the duty counter reset and + * emit inactive level to the PIN_ENABLE mux after that the driver can still change the pwm period + * and duty and the value will apply when CLK_ENABLE be set again. + * Use to determine whether duty_cycle bigger than 0. + * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately. + * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two + * values are equal it means the duty cycle = 100%. + * + * The glitch may generate at: + * - Enabled changing when the duty_cycle bigger than 0% and less than 100%. + * - Polarity changing when the duty_cycle bigger than 0% and less than 100%. + * + * Limitations: + * - When changing both duty cycle and period, we cannot prevent in + * software that the output might produce a period with mixed + * settings. + * - Disabling the PWM doesn't complete the current period. + * + * Improvements: + * - When only changing one of duty cycle or period, our pwm controller will not + * generate the glitch, the configure will change at next cycle of pwm. + * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PWM Control Register */ +#define PWM_ASPEED_CTRL (0x00) +#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19) +#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18) +#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17) +#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16) +#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15) +#define PWM_ASPEED_CTRL_INVERSE BIT(14) +#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13) +#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12) +#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8) +#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0) + +/* PWM Duty Cycle Register */ +#define PWM_ASPEED_DUTY_CYCLE (0x04) +#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24) +#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16) +#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8) +#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0) + +/* PWM fixed value */ +#define PWM_ASPEED_FIXED_PERIOD FIELD_MAX(PWM_ASPEED_DUTY_CYCLE_PERIOD) + +struct aspeed_pwm_data { + struct pwm_chip chip; + struct clk *clk; + void __iomem *base; + struct reset_control *reset; + unsigned long clk_source; +}; + +static inline struct aspeed_pwm_data * +aspeed_pwm_chip_to_data(struct pwm_chip *chip) +{ + return container_of(chip, struct aspeed_pwm_data, chip); +} + +static int aspeed_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct device *dev = chip->dev; + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); + bool polarity, pin_en, clk_en; + u32 duty_pt, val; + u64 div_h, div_l, duty_cycle_period, dividend; + + val = readl(priv->base + PWM_ASPEED_CTRL); + polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val); + pin_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val); + clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val); + div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val); + div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val); + val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE); + duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val); + duty_cycle_period = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_PERIOD, val); + + /* + * This multiplication doesn't overflow, the upper bound is + * 1000000000 * 256 * 256 << 15 = 0x1dcd650000000000 + */ + dividend = (u64)NSEC_PER_SEC * (div_l + 1) * (duty_cycle_period + 1) + << div_h; + state->period = DIV_ROUND_UP_ULL(dividend, priv->clk_source); + + if (clk_en && duty_pt) { + dividend = (u64)NSEC_PER_SEC * (div_l + 1) * duty_pt + << div_h; + state->duty_cycle = + DIV_ROUND_UP_ULL(dividend, priv->clk_source); + } else { + state->duty_cycle = clk_en ? state->period : 0; + } + state->polarity = polarity ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; + state->enabled = pin_en; + dev_dbg(dev, "get period: %lldns, duty_cycle: %lldns", state->period, + state->duty_cycle); + return 0; +} + +static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct device *dev = chip->dev; + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); + u32 duty_pt; + u64 div_h, div_l, divisor, expect_period; + bool clk_en; + + expect_period = min(div64_u64(ULLONG_MAX, (u64)priv->clk_source), + state->period); + dev_dbg(dev, "expect period: %lldns, duty_cycle: %lldns", expect_period, + state->duty_cycle); + /* + * Pick the smallest value for div_h so that div_l can be the biggest + * which results in a finer resolution near the target period value. + */ + divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) * + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1); + div_h = order_base_2(DIV64_U64_ROUND_UP(priv->clk_source * expect_period, divisor)); + if (div_h > 0xf) + div_h = 0xf; + + divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h; + div_l = div64_u64(priv->clk_source * expect_period, divisor); + + if (div_l == 0) + return -ERANGE; + + div_l -= 1; + + if (div_l > 255) + div_l = 255; + + dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", + priv->clk_source, div_h, div_l); + /* duty_pt = duty_cycle * (PERIOD + 1) / period */ + duty_pt = div64_u64(state->duty_cycle * priv->clk_source, + (u64)NSEC_PER_SEC * (div_l + 1) << div_h); + dev_dbg(dev, "duty_cycle = %lld, duty_pt = %d\n", state->duty_cycle, + duty_pt); + + /* + * Fixed DUTY_CYCLE_PERIOD to its max value to get a + * fine-grained resolution for duty_cycle at the expense of a + * coarser period resolution. + */ + writel((readl(priv->base + PWM_ASPEED_DUTY_CYCLE) & + ~(PWM_ASPEED_DUTY_CYCLE_PERIOD)) | + FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD, + PWM_ASPEED_FIXED_PERIOD), + priv->base + PWM_ASPEED_DUTY_CYCLE); + + if (duty_pt == 0) { + /* emit inactive level and assert the duty counter reset */ + clk_en = 0; + } else { + clk_en = 1; + if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1)) + duty_pt = 0; + writel((readl(priv->base + PWM_ASPEED_DUTY_CYCLE) & + ~(PWM_ASPEED_DUTY_CYCLE_RISING_POINT | + PWM_ASPEED_DUTY_CYCLE_FALLING_POINT)) | + FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, + duty_pt), + priv->base + PWM_ASPEED_DUTY_CYCLE); + } + + writel((readl(priv->base + PWM_ASPEED_CTRL) & + ~(PWM_ASPEED_CTRL_CLK_DIV_H | PWM_ASPEED_CTRL_CLK_DIV_L | + PWM_ASPEED_CTRL_PIN_ENABLE | PWM_ASPEED_CTRL_CLK_ENABLE | + PWM_ASPEED_CTRL_INVERSE)) | + FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) | + FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) | + FIELD_PREP(PWM_ASPEED_CTRL_PIN_ENABLE, state->enabled) | + FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en) | + FIELD_PREP(PWM_ASPEED_CTRL_INVERSE, state->polarity), + priv->base + PWM_ASPEED_CTRL); + + return 0; +} + +static const struct pwm_ops aspeed_pwm_ops = { + .apply = aspeed_pwm_apply, + .get_state = aspeed_pwm_get_state, + .owner = THIS_MODULE, +}; + +static void aspeed_pwm_reset_assert(void *data) +{ + struct reset_control *rst = data; + + reset_control_assert(rst); +} + +static void aspeed_pwm_chip_remove(void *data) +{ + struct pwm_chip *chip = data; + + pwmchip_remove(chip); +} + +static int aspeed_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int ret; + struct aspeed_pwm_data *priv; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), + "Couldn't get clock\n"); + priv->clk_source = clk_get_rate(priv->clk); + priv->reset = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(priv->reset)) + return dev_err_probe(dev, PTR_ERR(priv->reset), + "Couldn't get reset control\n"); + + ret = reset_control_deassert(priv->reset); + if (ret) + return dev_err_probe(dev, ret, + "Couldn't deassert reset control\n"); + + ret = devm_add_action_or_reset(dev, aspeed_pwm_reset_assert, + priv->reset); + if (ret) + return ret; + + priv->chip.dev = dev; + priv->chip.ops = &aspeed_pwm_ops; + priv->chip.npwm = 1; + + ret = pwmchip_add(&priv->chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); + ret = devm_add_action_or_reset(dev, aspeed_pwm_chip_remove, + &priv->chip); + if (ret) + return ret; + return 0; +} + +static const struct of_device_id of_pwm_match_table[] = { + { + .compatible = "aspeed,ast2600-pwm", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_pwm_match_table); + +static struct platform_driver aspeed_pwm_driver = { + .probe = aspeed_pwm_probe, + .driver = { + .name = "aspeed-pwm", + .of_match_table = of_pwm_match_table, + }, +}; + +module_platform_driver(aspeed_pwm_driver); + +MODULE_AUTHOR("Billy Tsai "); +MODULE_DESCRIPTION("Aspeed ast2600 PWM device driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Jun 8 02:18:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 104796 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp615855vqr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j5-20020a17090a734500b002564edc1320si291452pjs.51.2023.06.07.19.17.41; Wed, 07 Jun 2023 19:17:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233268AbjFHCQr (ORCPT + 99 others); Wed, 7 Jun 2023 22:16:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233385AbjFHCQl (ORCPT ); Wed, 7 Jun 2023 22:16:41 -0400 Received: from mail.aspeedtech.com (mail.aspeedtech.com [211.20.114.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DC0B26A9; Wed, 7 Jun 2023 19:16:35 -0700 (PDT) Received: from BillyTsai-pc.aspeed.com (192.168.1.221) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Jun 2023 10:16:22 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , , , , , Subject: [v6 4/4] hwmon: Add Aspeed ast2600 TACH support Date: Thu, 8 Jun 2023 10:18:39 +0800 Message-ID: <20230608021839.12769-5-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230608021839.12769-1-billy_tsai@aspeedtech.com> References: <20230608021839.12769-1-billy_tsai@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.1.221] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768099071585892201?= X-GMAIL-MSGID: =?utf-8?q?1768099071585892201?= Add the support of Tachometer which can use to monitor the frequency of the input. In Aspeed AST2600 SoC features 16 TACH controllers, with each controller capable of supporting up to 1 input. Signed-off-by: Billy Tsai --- Documentation/hwmon/index.rst | 1 + Documentation/hwmon/tach-aspeed-ast2600.rst | 25 ++ drivers/hwmon/Kconfig | 10 + drivers/hwmon/Makefile | 1 + drivers/hwmon/tach-aspeed-ast2600.c | 305 ++++++++++++++++++++ 5 files changed, 342 insertions(+) create mode 100644 Documentation/hwmon/tach-aspeed-ast2600.rst create mode 100644 drivers/hwmon/tach-aspeed-ast2600.c diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst index ddff3c5713d7..4c3dd74675ef 100644 --- a/Documentation/hwmon/index.rst +++ b/Documentation/hwmon/index.rst @@ -194,6 +194,7 @@ Hardware Monitoring Kernel Drivers sparx5-temp stpddc60 sy7636a-hwmon + tach-aspeed-ast2600 tc654 tc74 thmc50 diff --git a/Documentation/hwmon/tach-aspeed-ast2600.rst b/Documentation/hwmon/tach-aspeed-ast2600.rst new file mode 100644 index 000000000000..b08c73a4237f --- /dev/null +++ b/Documentation/hwmon/tach-aspeed-ast2600.rst @@ -0,0 +1,25 @@ +Kernel driver tach-aspeed-ast2600 +================================= + +Supported chips: + ASPEED AST2600 + +Authors: + + +Description: +------------ +This driver implements support for ASPEED AST2600 Fan Tacho controller. +The controller supports up to 1 tachometer inputs. + +The driver provides the following sensor accesses in sysfs: + +=============== ======= ====================================================== +fanX_input ro provide current fan rotation value in RPM as reported + by the fan to the device. +fanX_div rw Fan divisor: Supported value are power of 4 (1, 4, 16 + 64, ... 4194304) + The larger divisor, the less rpm accuracy and the less + affected by fan signal glitch. +fanX_pulses rw Fan pulses per resolution. +=============== ======= ====================================================== diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index a5253abb7ea7..5948a63e44e7 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -411,6 +411,16 @@ config SENSORS_ASPEED This driver can also be built as a module. If so, the module will be called aspeed_pwm_tacho. +config SENSORS_TACH_ASPEED_AST2600 + tristate "ASPEED ast2600 Tachometer support" + depends on ARCH_ASPEED || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + This driver provides support for Aspeed ast2600 Tachometer. + + To compile this driver as a module, choose M here: the module + will be called tach-aspeed-ast2600. + config SENSORS_ATXP1 tristate "Attansic ATXP1 VID controller" depends on I2C diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index c5cd7e3a67ff..a3bf5b438e0f 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_SENSORS_ARM_SCMI) += scmi-hwmon.o obj-$(CONFIG_SENSORS_ARM_SCPI) += scpi-hwmon.o obj-$(CONFIG_SENSORS_AS370) += as370-hwmon.o obj-$(CONFIG_SENSORS_ASC7621) += asc7621.o +obj-$(CONFIG_SENSORS_TACH_ASPEED_AST2600) += tach-aspeed-ast2600.o obj-$(CONFIG_SENSORS_ASPEED) += aspeed-pwm-tacho.o obj-$(CONFIG_SENSORS_ATXP1) += atxp1.o obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o diff --git a/drivers/hwmon/tach-aspeed-ast2600.c b/drivers/hwmon/tach-aspeed-ast2600.c new file mode 100644 index 000000000000..8be66ee25a31 --- /dev/null +++ b/drivers/hwmon/tach-aspeed-ast2600.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TACH Control Register */ +#define TACH_ASPEED_CTRL (0x00) +#define TACH_ASPEED_IER BIT(31) +#define TACH_ASPEED_INVERS_LIMIT BIT(30) +#define TACH_ASPEED_LOOPBACK BIT(29) +#define TACH_ASPEED_ENABLE BIT(28) +#define TACH_ASPEED_DEBOUNCE_MASK GENMASK(27, 26) +#define TACH_ASPEED_DEBOUNCE_BIT 26 +#define TACH_ASPEED_IO_EDGE_MASK GENMASK(25, 24) +#define TACH_ASPEED_IO_EDGE_BIT 24 +#define TACH_ASPEED_CLK_DIV_T_MASK GENMASK(23, 20) +#define TACH_ASPEED_CLK_DIV_BIT 20 +#define TACH_ASPEED_THRESHOLD_MASK GENMASK(19, 0) +/* [27:26] */ +#define DEBOUNCE_3_CLK 0x00 +#define DEBOUNCE_2_CLK 0x01 +#define DEBOUNCE_1_CLK 0x02 +#define DEBOUNCE_0_CLK 0x03 +/* [25:24] */ +#define F2F_EDGES 0x00 +#define R2R_EDGES 0x01 +#define BOTH_EDGES 0x02 +/* [23:20] */ +/* divisor = 4 to the nth power, n = register value */ +#define DEFAULT_TACH_DIV 1024 +#define DIV_TO_REG(divisor) (ilog2(divisor) >> 1) + +/* TACH Status Register */ +#define TACH_ASPEED_STS (0x04) + +/*PWM_TACH_STS */ +#define TACH_ASPEED_ISR BIT(31) +#define TACH_ASPEED_PWM_OUT BIT(25) +#define TACH_ASPEED_PWM_OEN BIT(24) +#define TACH_ASPEED_DEB_INPUT BIT(23) +#define TACH_ASPEED_RAW_INPUT BIT(22) +#define TACH_ASPEED_VALUE_UPDATE BIT(21) +#define TACH_ASPEED_FULL_MEASUREMENT BIT(20) +#define TACH_ASPEED_VALUE_MASK GENMASK(19, 0) +/********************************************************** + * Software setting + *********************************************************/ +#define DEFAULT_FAN_PULSE_PR 2 + +struct aspeed_tach_channel_params { + u8 pulse_pr; + u32 divisor; +}; + +struct aspeed_tach_data { + struct device *dev; + void __iomem *base; + struct clk *clk; + struct reset_control *reset; + bool tach_present; + struct aspeed_tach_channel_params tach_channel; + unsigned long clk_source; +}; + +static void aspeed_tach_ch_enable(struct aspeed_tach_data *priv, bool enable) +{ + if (enable) + writel(readl(priv->base + TACH_ASPEED_CTRL) | + (TACH_ASPEED_ENABLE), + priv->base + TACH_ASPEED_CTRL); + else + writel(readl(priv->base + TACH_ASPEED_CTRL) & + ~(TACH_ASPEED_ENABLE), + priv->base + TACH_ASPEED_CTRL); +} + +static u64 aspeed_tach_val_to_rpm(struct aspeed_tach_data *priv, u32 tach_val) +{ + u64 rpm; + u32 tach_div; + + tach_div = tach_val * (priv->tach_channel.divisor) * + (priv->tach_channel.pulse_pr); + + dev_dbg(priv->dev, "clk %ld, tach_val %d , tach_div %d\n", + priv->clk_source, tach_val, tach_div); + + rpm = (u64)priv->clk_source * 60; + do_div(rpm, tach_div); + + return rpm; +} + +static int aspeed_get_fan_tach_ch_rpm(struct aspeed_tach_data *priv) +{ + u32 val; + u64 rpm; + + val = readl(priv->base + TACH_ASPEED_STS); + + if (!(val & TACH_ASPEED_FULL_MEASUREMENT)) + return 0; + rpm = aspeed_tach_val_to_rpm(priv, val & TACH_ASPEED_VALUE_MASK); + + return rpm; +} + +static int aspeed_tach_hwmon_read(struct device *dev, + enum hwmon_sensor_types type, u32 attr, + int channel, long *val) +{ + struct aspeed_tach_data *priv = dev_get_drvdata(dev); + u32 reg_val; + int ret; + + switch (attr) { + case hwmon_fan_input: + ret = aspeed_get_fan_tach_ch_rpm(priv); + if (ret < 0) + return ret; + *val = ret; + break; + case hwmon_fan_div: + reg_val = readl(priv->base + TACH_ASPEED_CTRL); + reg_val = FIELD_GET(TACH_ASPEED_CLK_DIV_T_MASK, reg_val); + *val = BIT(reg_val << 1); + break; + case hwmon_fan_pulses: + *val = priv->tach_channel.pulse_pr; + break; + default: + return -EOPNOTSUPP; + } + return 0; +} + +static int aspeed_tach_hwmon_write(struct device *dev, + enum hwmon_sensor_types type, u32 attr, + int channel, long val) +{ + struct aspeed_tach_data *priv = dev_get_drvdata(dev); + + switch (attr) { + case hwmon_fan_div: + if (!is_power_of_2(val) || (ilog2(val) % 2)) + return -EINVAL; + else if (DIV_TO_REG(val) > 0xb) + return -ERANGE; + priv->tach_channel.divisor = val; + writel((readl(priv->base + TACH_ASPEED_CTRL) & + ~(TACH_ASPEED_CLK_DIV_T_MASK)) | + (DIV_TO_REG(priv->tach_channel.divisor) + << TACH_ASPEED_CLK_DIV_BIT), + priv->base + TACH_ASPEED_CTRL); + break; + case hwmon_fan_pulses: + priv->tach_channel.pulse_pr = val; + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static umode_t aspeed_tach_dev_is_visible(const void *drvdata, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + const struct aspeed_tach_data *priv = drvdata; + + if (!priv->tach_present) + return 0; + switch (attr) { + case hwmon_fan_input: + return 0444; + case hwmon_fan_div: + case hwmon_fan_pulses: + return 0644; + } + return 0; +} + +static const struct hwmon_ops aspeed_tach_ops = { + .is_visible = aspeed_tach_dev_is_visible, + .read = aspeed_tach_hwmon_read, + .write = aspeed_tach_hwmon_write, +}; + +static const struct hwmon_channel_info *aspeed_tach_info[] = { + HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES), + NULL +}; + +static const struct hwmon_chip_info aspeed_tach_chip_info = { + .ops = &aspeed_tach_ops, + .info = aspeed_tach_info, +}; + +static void aspeed_present_fan_tach(struct aspeed_tach_data *priv) +{ + priv->tach_present = true; + priv->tach_channel.divisor = DEFAULT_TACH_DIV; + priv->tach_channel.pulse_pr = DEFAULT_FAN_PULSE_PR; + + writel((readl(priv->base + TACH_ASPEED_CTRL) & + ~(TACH_ASPEED_INVERS_LIMIT | TACH_ASPEED_DEBOUNCE_MASK | + TACH_ASPEED_IO_EDGE_MASK | TACH_ASPEED_CLK_DIV_T_MASK | + TACH_ASPEED_THRESHOLD_MASK)) | + ((DEBOUNCE_3_CLK << TACH_ASPEED_DEBOUNCE_BIT) | + F2F_EDGES | + (DIV_TO_REG(priv->tach_channel.divisor) + << TACH_ASPEED_CLK_DIV_BIT)), + priv->base + TACH_ASPEED_CTRL); + + aspeed_tach_ch_enable(priv, true); +} + +static void aspeed_tach_reset_assert(void *data) +{ + struct reset_control *rst = data; + + reset_control_assert(rst); +} + +static int aspeed_tach_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct aspeed_tach_data *priv; + struct device *hwmon; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + priv->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), + "Couldn't get clock\n"); + + priv->clk_source = clk_get_rate(priv->clk); + priv->reset = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(priv->reset)) + return dev_err_probe(dev, PTR_ERR(priv->reset), + "Couldn't get reset control\n"); + + ret = reset_control_deassert(priv->reset); + if (ret) + return dev_err_probe(dev, ret, + "Couldn't deassert reset control\n"); + + ret = devm_add_action_or_reset(dev, aspeed_tach_reset_assert, + priv->reset); + if (ret) + return ret; + + aspeed_present_fan_tach(priv); + + hwmon = devm_hwmon_device_register_with_info(dev, "aspeed_tach", priv, + &aspeed_tach_chip_info, NULL); + ret = PTR_ERR_OR_ZERO(hwmon); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register hwmon device\n"); + return 0; +} + +static const struct of_device_id of_stach_match_table[] = { + { + .compatible = "aspeed,ast2600-tach", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_stach_match_table); + +static struct platform_driver aspeed_tach_driver = { + .probe = aspeed_tach_probe, + .driver = { + .name = "aspeed_tach", + .of_match_table = of_stach_match_table, + }, +}; + +module_platform_driver(aspeed_tach_driver); + +MODULE_AUTHOR("Billy Tsai "); +MODULE_DESCRIPTION("Aspeed ast2600 TACH device driver"); +MODULE_LICENSE("GPL");