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Signed-off-by: Krishna chaitanya chundru --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index b3c22eb..6fc5440 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -70,6 +70,13 @@ properties: description: GPIO used as WAKE# output signal maxItems: 1 + interconnects: + maxItems: 1 + + interconnect-names: + items: + - const: pcie-mem + resets: maxItems: 1 @@ -97,6 +104,8 @@ required: - interrupts - interrupt-names - reset-gpios + - interconnects + - interconnect-names - resets - reset-names - power-domains From patchwork Wed Jun 7 16:18:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 104611 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp324701vqr; Wed, 7 Jun 2023 09:28:31 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ54NFxrUdgZhITmqxbAq35SDwCtbgroEQwK5ZiiG/CU5zHCa9U+jvmigIDnXHZSbPW0ie0D X-Received: by 2002:a17:90a:cb8f:b0:24e:2e86:5465 with SMTP id a15-20020a17090acb8f00b0024e2e865465mr1914854pju.31.1686155310811; Wed, 07 Jun 2023 09:28:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686155310; cv=none; d=google.com; s=arc-20160816; b=LF66/Fx2DrQ0NDmltCihs8CHAX+3BKeM6w/Gsl/A9lHncQKCzEX74UEBwn5oiRpyik vhWfAKQS4Sb10C/9qjePLYRu+aOo04ejOgpOMZ5g2RXlXD1DmUIZg7pV45qygD+P1hXU WhtKMi4hIsS1cdxr7W4pXLsuAEb9fAJbIFKldcnpWsJKqWajsRGIAME+TDzOK5L5PhvR lcO7N7Hh++By16XPW2bOkNxfWnigJW++rmUADSX3AwPOU8mExwhC3h3NIi6CR7M27V9R HgVqGyZ15Sr4Rv/eXeDOLlayJFWfJvd4UP8b7rmkI8GneucXl1ctjaf/xBgqFxbffwOD PSdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=w3cL8mcfmHWXjhLEt5MfxlT5xCUiRleQGo/dFFFupDw=; b=XQcCDH5KQAv8dbDCMQbemf7qGLcF7cyqFYHmLPVKSJNmvL7L6iWXjGGztgyn8005zX DBQ5HqbXMF+w3QMcIcebvSZ3L+84xYN9CYSict2A1JopMwmwYRX99wOcsh0gJuAhXW6N WvfI9Vnmh8ALXet9/E0l18ibcZ+jGpfJjBHbQzik1nHO7cP3K1TyxkqgbqhLlaGhPVFx bdp6V0WFSzcumQAYFINnKyTBr1k1A5WL0o6dOBZ8+9OWo9LEWdIENniysM9i7xxr2MAq TgK0jRJNJ/Cmf8Az1upkB0Sq2TXBQW6B0RrhYa+6Tn+fuQnN3RXKsVV90MMDguKTR/UF XGyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=f8ctetF7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 342c3d1..e9f8bfe 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -421,6 +421,10 @@ ; interrupt-names = "global", "doorbell"; + + interconnects = <&system_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "pci-mem"; + resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; From patchwork Wed Jun 7 16:18:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 104616 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp327159vqr; Wed, 7 Jun 2023 09:31:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4O9XCsE4M+vVzEZVDfVAEVBEGOL9bkrduK+jaFaGgD/NHNvArVpetVPigoxL0UjF+yv8rW X-Received: by 2002:a17:90a:d3d3:b0:258:c4b5:c6b8 with SMTP id d19-20020a17090ad3d300b00258c4b5c6b8mr2530305pjw.11.1686155511028; Wed, 07 Jun 2023 09:31:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686155511; cv=none; d=google.com; s=arc-20160816; b=kF2dksG2k1IFOmp+WcqkHSjYdi/vWsoR/2FtnfbuKJ24M46fsX/KqAYpSLcYPHbVBz HNggkWqYvnkdU2WNCepxSPf6MMmaZORWicnBNsaicDWHSt/m0DFyRDxqifS5zqU8DpPt Wuk3wlU+wbvxxOffP4E+BBCouYcFaTBYwY4ra9kVLapXsrwlXUonAvhMbh7Ad7NjP++z hHzBJVgaVsT9hZM6ejdU3zDFSlm1lGLM7dAl9ayiHsnyQwUYESvhGhfOl5n4xra04CTv FG5SVXPrGjFHDEWG2at0wRx6mUMhAPThQDiwWdYP5FXnMeE4Z/T0AH0d9xlZYYr764Nv PT6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=VeSbAxWEvoQCsQCbDJ4cOXZRowdK7XhoiI7gBf8qkcg=; b=E0GskwoJVw9h2hOa+w3UFv2omXzi8ZPiR9S6l/M64krLarSYIB1dM9FRgcr/6fluoe CS4uJBp/UHV9wgUzxk6B+dKN/HHDEz6MVzzxBXA010WPEP+7MyWpoCpXIxiBagqbChNd xxdyxXdEkTikwe/07WAzY6tlYYhZYELlFleWkU8WNxvYiUVAKwdcGSA1EOPBgIBTMSzt IRYZU5rOBtFQ4Ze19nDpLC9BIWNRac0638TL0kvez9JmKtkpIgG6HXrwVsUKsX5tMrox tFSkkr+u0Ih0LgCr7PHkv8DlBRbg4hA7oY2iC7kAGuX2mJw4Rb2fBK9ZYf7esPfWzYnr EE0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=blkcMsm5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Wed, 07 Jun 2023 16:18:13 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 357GIAwv029266; Wed, 7 Jun 2023 16:18:10 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3qyxkm3buk-1; Wed, 07 Jun 2023 16:18:10 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 357GI92I029191; Wed, 7 Jun 2023 16:18:10 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 357GI9cJ029203; Wed, 07 Jun 2023 16:18:09 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id E2FCC3935; Wed, 7 Jun 2023 21:48:08 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: quic_vbadigan@quicinc.com, quic_ramkri@quicinc.com, Krishna chaitanya chundru , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org (open list:PCIE ENDPOINT DRIVER FOR QUALCOMM), linux-arm-msm@vger.kernel.org (open list:PCIE ENDPOINT DRIVER FOR QUALCOMM), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 3/3] PCI: qcom-ep: Add ICC bandwidth voting support Date: Wed, 7 Jun 2023 21:48:07 +0530 Message-Id: <1686154687-29356-4-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1686154687-29356-1-git-send-email-quic_krichai@quicinc.com> References: <1686154687-29356-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TxFsakLNEaTdOeXWqubTjoNOdUdID8SN X-Proofpoint-GUID: TxFsakLNEaTdOeXWqubTjoNOdUdID8SN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 impostorscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306070138 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768062201253931068?= X-GMAIL-MSGID: =?utf-8?q?1768062201253931068?= Add support to vote for ICC bandwidth based on the link speed and width. This patch is inspired from pcie-qcom driver to add basic interconnect support. Link:https://patchwork.kernel.org/project/linux-pci/patch/20221102090705.23634-3-johan+linaro@kernel.org/ Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 68 +++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 19b3283..5f9139d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,7 @@ #define PARF_SYS_CTRL 0x00 #define PARF_DB_CTRL 0x10 #define PARF_PM_CTRL 0x20 +#define PARF_PM_STTS 0x24 #define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PARF_MHI_BASE_ADDR_LOWER 0x178 #define PARF_MHI_BASE_ADDR_UPPER 0x17c @@ -128,6 +130,9 @@ /* DBI register fields */ #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0) +#define DBI_LINKCTRLSTATUS 0x80 +#define DBI_LINKCTRLSTATUS_SHIFT 16 + #define XMLH_LINK_UP 0x400 #define CORE_RESET_TIME_US_MIN 1000 #define CORE_RESET_TIME_US_MAX 1005 @@ -178,6 +183,8 @@ struct qcom_pcie_ep { struct phy *phy; struct dentry *debugfs; + struct icc_path *icc; + struct clk_bulk_data *clks; int num_clks; @@ -253,9 +260,51 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) disable_irq(pcie_ep->perst_irq); } +static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) +{ + struct dw_pcie *pci = &pcie_ep->pci; + int speed, width; + u32 val, bw; + int ret; + + if (!pcie_ep->icc) + return; + + val = dw_pcie_readl_dbi(pci, DBI_LINKCTRLSTATUS); + val = val >> DBI_LINKCTRLSTATUS_SHIFT; + + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val); + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val); + + switch (speed) { + case 1: + bw = MBps_to_icc(250); /* BW for GEN1 per lane: 250MBps */ + break; + case 2: + bw = MBps_to_icc(500); /* BW for GEN2 per lane: 500MBps */ + break; + case 3: + bw = MBps_to_icc(985); /* BW for GEN3 per lane: 985MBps */ + break; + default: + WARN_ON_ONCE(1); + fallthrough; + case 4: + bw = MBps_to_icc(1969); /* BW for GEN4 per lane: 985MBps */ + break; + } + + ret = icc_set_bw(pcie_ep->icc, 0, width * bw); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + ret); + } +} + static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) { int ret; + struct dw_pcie *pci = &pcie_ep->pci; ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); if (ret) @@ -277,6 +326,20 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) if (ret) goto err_phy_exit; + /* + * Some Qualcomm platforms require interconnect bandwidth constraints + * to be set before enabling interconnect clocks. + * + * Set an initial average bandwidth corresponding to single-lane Gen 1 + * for the pcie to mem path. + */ + ret = icc_set_bw(pcie_ep->icc, 0, MBps_to_icc(250)); /* BW for GEN1 per lane: 250MBps */ + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + ret); + goto err_phy_exit; + } + return 0; err_phy_exit: @@ -550,6 +613,10 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, if (IS_ERR(pcie_ep->phy)) ret = PTR_ERR(pcie_ep->phy); + pcie_ep->icc = devm_of_icc_get(dev, "pcie-mem"); + if (IS_ERR(pcie_ep->icc)) + ret = PTR_ERR(pcie_ep->icc); + return ret; } @@ -572,6 +639,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received BME event. Link is enabled!\n"); pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; + qcom_pcie_ep_icc_update(pcie_ep); } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);