From patchwork Thu Oct 27 02:39:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 11520 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp603898wru; Wed, 26 Oct 2022 19:49:49 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4eDUx7nvvgQh955q27X/+eJ8nHfZlenHdH7puWjXaP3GGBiNMdf8N/xRI+uxWMSj+TCXpY X-Received: by 2002:a05:6402:2694:b0:45c:a035:34bc with SMTP id w20-20020a056402269400b0045ca03534bcmr42504800edd.158.1666838988936; Wed, 26 Oct 2022 19:49:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666838988; cv=none; d=google.com; s=arc-20160816; b=B7uJw3McSYylixd2WvKVfB3eWs2CycGGWynFaa7qSHv1+kotBB9i99S5zmefOayBQl cU46vqhDYfoS9GfbjTlzjD0LZZCG0W5YfAVy1uNGPv9Ks9CKvRIS/7xLOcPVDBlN4324 3WyWFA+z28mHwqMKZJmgdJU8dwgLd2Hqyw3GevCliMyhGFdNBy175DSCWCn1MHHCOzKR gT1+rMYXt0MbBFjckZzHF69X8jRzQF0h3FDaYeqF/8u/YdCQjkSAqCD8Y/KjG1W99laY HtKqf07QI4DU1f8eE4QeqKUfr+0oSpV2CIIC6V54a27xTxJy2NNr9ejI365pAUkRwlcq r5yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=9edXG9SBCBFkr8z43egDqb7kCES1Ezo7Q/IINFcYamc=; b=GVXFbqWSLJIAfylRDKW5JU6gVtVo2WskC9G43DP3eoAfIWKz5zdk7Z+jJg/6PQ2//l ANlDhge/p7Hl27BOtjP8ICooNP2wa6Rl8LJkHeEf8rgfqWW9Ie/X9GOBCFM3iQa3ZgAG yR374THUwqeszmRTBvLWLY2i5NFOq6RwQxPIfPwpL2JPZ0zLIipqxe1yDGAA2GcykWMB jvAvXI45WPzu9dCr3suaKGq0XbP/7PTAJIq6NjGe5Ei1q4w6/hqnMC448MkrrFKLR+ly jVNyPpqSWu7I1wbOHmIMbEHtFlDN30IFyHExNb2YAB9xZnrT1Q6er5GUUciyxQC9nzQS 053w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e5-20020a170906844500b0078255525a6fsi111801ejy.671.2022.10.26.19.49.00; Wed, 26 Oct 2022 19:49:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233801AbiJ0Cjo (ORCPT + 99 others); Wed, 26 Oct 2022 22:39:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233569AbiJ0Cji (ORCPT ); Wed, 26 Oct 2022 22:39:38 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A5533FD07; Wed, 26 Oct 2022 19:39:33 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B0C18D6E; Wed, 26 Oct 2022 19:39:39 -0700 (PDT) Received: from a077893.blr.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EC1863F792; Wed, 26 Oct 2022 19:39:29 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org Cc: Anshuman Khandual , Suzuki K Poulose , James Morse , Jonathan Corbet , Mark Rutland , linux-doc@vger.kernel.org Subject: [PATCH 1/2] arm64: Add Cortex-715 CPU part definition Date: Thu, 27 Oct 2022 08:09:14 +0530 Message-Id: <20221027023915.1318100-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221027023915.1318100-1-anshuman.khandual@arm.com> References: <20221027023915.1318100-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747807359866258070?= X-GMAIL-MSGID: =?utf-8?q?1747807359866258070?= Add the CPU Partnumbers for the new Arm designs. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: James Morse Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index abc418650fec..4b1ad810436f 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -80,6 +80,7 @@ #define ARM_CPU_PART_CORTEX_X1 0xD44 #define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_CORTEX_A715 0xD4D #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B @@ -142,6 +143,7 @@ #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) +#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) From patchwork Thu Oct 27 02:39:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 11521 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp605107wru; Wed, 26 Oct 2022 19:54:53 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6tlRDWxHKio+j6MY4CjFzd/trhq6ZtBhEAVEkBJS0/g4xeGBGjsZqA58393UDUpxkNPLq9 X-Received: by 2002:aa7:c58a:0:b0:461:fc07:a821 with SMTP id g10-20020aa7c58a000000b00461fc07a821mr13656602edq.19.1666839293134; Wed, 26 Oct 2022 19:54:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666839293; cv=none; d=google.com; s=arc-20160816; b=YdDNcypjkWAKSvRjqmGkGYOc2EzFnOzp7yem28rrTPVrn13ZYEALkQQHa9cX8Paz28 8Qgimaj6NE0EJfEGXV9Cyx4/mq0bUc9oc7fxgXwWvqXqO1rz88uR4RpYrPgKaRGKHe33 DZf5y2oclpr5XjZOglvaNzG/HOymVcqD2Jo5/2SnawReY3VZcaSlkevKsdPBAbCwBFzl m5oh0poKvY8+Pb8m9dTp9OYQ1974cPZUe7eLslOq2fNv0hgxLm9SIWTv26rdtS8ZJlTA 2RLbDy8V5uB5W++iwGOUm0QdIewjZhpX6847eiTlkc5ng/oDncoJrW14sEzN6ttDm7n1 ewaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=m5HwYJbwiBwxkTNb9zNWqGbnmocwKPcEGHPdZl+5Kzc=; b=us9AE7YNbeBiBmTOrga6MK+ev50L/YCI0DJapxio4ZFpRidRekczQGYvDl0+ThQL7R +LXO0KHGl1G5EftUkHJWze8JiwzxU3lipG8DLdnZ3NTQ3xG3E4aBvL7/9JR2RpvCJpxu W2CyvRie5CfIjTP6m9TAYNcKzSSD/sFyJdlRjVIozJNLGM7ikDpDq3tCL0WKMuGt3tAj HYf5pHUwpH9kyEtuZhh7S/7tC4gDyuy9arVUF82nxMMyBuiozB8SfHEZwrK89kqJTtSe guReR1fElbD0iwl1NeCOMiA1F1uTUjZ3f9aeD5v5olFbKwR/z3a0xV+Q87VtkNm40q8w XjpQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g22-20020a1709065d1600b00773b8e3b6a1si176095ejt.805.2022.10.26.19.54.02; Wed, 26 Oct 2022 19:54:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233891AbiJ0Cjs (ORCPT + 99 others); Wed, 26 Oct 2022 22:39:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233668AbiJ0Cjk (ORCPT ); Wed, 26 Oct 2022 22:39:40 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EDE0F1A811; Wed, 26 Oct 2022 19:39:37 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 088D21042; Wed, 26 Oct 2022 19:39:44 -0700 (PDT) Received: from a077893.blr.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0F8D63F792; Wed, 26 Oct 2022 19:39:33 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org Cc: Anshuman Khandual , Suzuki K Poulose , James Morse , Jonathan Corbet , Mark Rutland , linux-doc@vger.kernel.org Subject: [PATCH 2/2] arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption Date: Thu, 27 Oct 2022 08:09:15 +0530 Message-Id: <20221027023915.1318100-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221027023915.1318100-1-anshuman.khandual@arm.com> References: <20221027023915.1318100-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747807678510678634?= X-GMAIL-MSGID: =?utf-8?q?1747807678510678634?= If a Cortex-A715 cpu sees a page mapping permissions change from executable to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers, on the next instruction abort caused by permission fault. Only user-space does executable to non-executable permission transition via mprotect() system call which calls ptep_modify_prot_start() and ptep_modify _prot_commit() helpers, while changing the page mapping. The platform code can override these helpers via __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION. Work around the problem via doing a break-before-make TLB invalidation, for all executable user space mappings, that go through mprotect() system call. This overrides ptep_modify_prot_start() and ptep_modify_prot_commit(), via defining HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION on the platform thus giving an opportunity to intercept user space exec mappings, and do the necessary TLB invalidation. Similar interceptions are also implemented for HugeTLB. Cc: Catalin Marinas Cc: Will Deacon Cc: Jonathan Corbet Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- Documentation/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 16 +++++++++++ arch/arm64/include/asm/hugetlb.h | 9 +++++++ arch/arm64/include/asm/pgtable.h | 24 +++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 7 +++++ arch/arm64/mm/hugetlbpage.c | 37 ++++++++++++++++++++++++++ arch/arm64/tools/cpucaps | 1 + 7 files changed, 96 insertions(+) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 808ade4cc008..ec5f889d7681 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -120,6 +120,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 505c8a1ccbe0..56c3381e9d94 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -964,6 +964,22 @@ config ARM64_ERRATUM_2457168 If unsure, say Y. +config ARM64_ERRATUM_2645198 + bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" + default y + help + This option adds the workaround for ARM Cortex-A715 erratum 2645198. + + If a Cortex-A715 cpu sees a page mapping permissions change from executable + to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the + next instruction abort caused by permission fault. + + Only user-space does executable to non-executable permission transition via + mprotect() system call. Workaround the problem by doing a break-before-make + TLB invalidation, for all changes to executable user space mappings. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h index d20f5da2d76f..6a4a1ab8eb23 100644 --- a/arch/arm64/include/asm/hugetlb.h +++ b/arch/arm64/include/asm/hugetlb.h @@ -49,6 +49,15 @@ extern pte_t huge_ptep_get(pte_t *ptep); void __init arm64_hugetlb_cma_reserve(void); +#define huge_ptep_modify_prot_start huge_ptep_modify_prot_start +extern pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma, + unsigned long addr, pte_t *ptep); + +#define huge_ptep_modify_prot_commit huge_ptep_modify_prot_commit +extern void huge_ptep_modify_prot_commit(struct vm_area_struct *vma, + unsigned long addr, pte_t *ptep, + pte_t old_pte, pte_t new_pte); + #include #endif /* __ASM_HUGETLB_H */ diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 71a1af42f0e8..c4c021277f20 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -1095,7 +1095,31 @@ static inline bool pud_sect_supported(void) return PAGE_SIZE == SZ_4K; } +#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION +static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, + unsigned long addr, + pte_t *ptep) +{ + pte_t pte = ptep_get_and_clear(vma->vm_mm, addr, ptep); + if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198)) { + /* + * Break-before-make (BBM) is required for all user space mappings + * when the permission changes from executable to non-executable + * in cases where cpu is affected with errata #2645198. + */ + if (pte_user_exec(pte) && cpus_have_const_cap(ARM64_WORKAROUND_2645198)) + __flush_tlb_range(vma, addr, addr + PAGE_SIZE, PAGE_SIZE, false, 3); + } + return pte; +} + +static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, + unsigned long addr, + pte_t *ptep, pte_t old_pte, pte_t pte) +{ + __set_pte_at(vma->vm_mm, addr, ptep, pte); +} #endif /* !__ASSEMBLY__ */ #endif /* __ASM_PGTABLE_H */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 89ac00084f38..307faa2b4395 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -661,6 +661,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), }, #endif +#ifdef CONFIG_ARM64_ERRATUM_2645198 + { + .desc = "ARM erratum 2645198", + .capability = ARM64_WORKAROUND_2645198, + ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A715) + }, +#endif #ifdef CONFIG_ARM64_ERRATUM_2077057 { .desc = "ARM erratum 2077057", diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c index 35e9a468d13e..8cdcb3a34c27 100644 --- a/arch/arm64/mm/hugetlbpage.c +++ b/arch/arm64/mm/hugetlbpage.c @@ -559,3 +559,40 @@ bool __init arch_hugetlb_valid_size(unsigned long size) { return __hugetlb_valid_size(size); } + +pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma, + unsigned long addr, pte_t *ptep) +{ + pte_t pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep); + + if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198)) { + /* + * Break-before-make (BBM) is required for all user space mappings + * when the permission changes from executable to non-executable + * in cases where cpu is affected with errata #2645198. + */ + if (pte_user_exec(pte) && cpus_have_const_cap(ARM64_WORKAROUND_2645198)) { + size_t pgsize = page_size(pte_page(pte)); + int level = 3; + + if (pgsize == PUD_SIZE) + level = 1; + else if ((pgsize == PMD_SIZE) || (pgsize == CONT_PMD_SIZE)) + level = 2; + else if (pgsize == CONT_PTE_SIZE) + level = 3; + else + pr_warn("%s: unrecognized huge page size 0x%lx\n", + __func__, pgsize); + __flush_tlb_range(vma, addr, addr + pgsize, pgsize, false, level); + } + } + return pte; +} + +void huge_ptep_modify_prot_commit(struct vm_area_struct *vma, + unsigned long addr, pte_t *ptep, + pte_t old_pte, pte_t pte) +{ + set_huge_pte_at(vma->vm_mm, addr, ptep, pte); +} diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index f1c0347ec31a..2274d836fcfe 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -70,6 +70,7 @@ WORKAROUND_2038923 WORKAROUND_2064142 WORKAROUND_2077057 WORKAROUND_2457168 +WORKAROUND_2645198 WORKAROUND_2658417 WORKAROUND_TRBE_OVERWRITE_FILL_MODE WORKAROUND_TSB_FLUSH_FAILURE