From patchwork Wed Oct 26 20:04:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 11433 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp462635wru; Wed, 26 Oct 2022 13:09:05 -0700 (PDT) X-Google-Smtp-Source: AMsMyM64RXcT+Cv72vZwmKveUNmcVxA2UYfzDTz6jk6HcYWRJr+Bd1fLQYQPR29j9rVHX0kBL34y X-Received: by 2002:a65:6c08:0:b0:448:c216:fe9 with SMTP id y8-20020a656c08000000b00448c2160fe9mr38370868pgu.243.1666814945257; Wed, 26 Oct 2022 13:09:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666814945; cv=none; d=google.com; s=arc-20160816; b=o1GcvEvNYIzOpx9DdBgcqxKxkBsu6FaZ2cy/p6e8z8KOphG4Vw2cQNRmBy8VL6u3nA kV4KOpGq+5jGBbuAUS57aLib1qq6whH7933+DUnLS4A+KlOcbKvhXfdTkoTSzJD1TG01 GJf5QurLBmsHJ+CwlXztDQQf9dNCeFBH3J+yQGsapGmupkVVPAzePotnF/3flydKQ3fc bONzv/jocRsOVese6K4a/h+nn5g0yMMynx8zoF5/iLu1A+fYExR0q0/q9VIb7U7tm/M/ cCrYskt5OvKHw44h/2K220/4aXHnd7iSeAgv3YPTArdYc3Px6lmLuK8yTPZGWw5sjkOd Zrdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ky2K+rZxKLCb66uyKr5M2WMk95oP3pO36xhDJSOo6yc=; b=oAhmHJfQog1MQjv0SCkr7/ytDhRVGsBZ+08F74QQ50WaqK2Bas1xOErjruImXPHn1k ysbS0H9hbm1XsOPIsCUwmk3SGszaRCKcqMPdajIXn6h0O0PmsWzi9udLUizeHarf2l2h 6BuCpKunK8PuuUBzHspr2wifaOrJTh5n7AEnfnl5rORqC4GJ5XDS5BBAfEk8Wa3pYyKb YDSOOkfS0kIK0BEkMBia2gBGUY/z543bVNAk6cLLsMVhC2uw21jdxPId8wWHA7m7XUby hX02LB6JGxr/N/ZwfmZZk2J5hT2nekFkiMFpuWNhm98SMKPGQ8ET8fN00k9nza2wTXJ7 jLFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="gZo/NaYh"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i9-20020a628709000000b00555463cd9e6si7847015pfe.238.2022.10.26.13.08.49; Wed, 26 Oct 2022 13:09:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="gZo/NaYh"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234062AbiJZUFU (ORCPT + 99 others); Wed, 26 Oct 2022 16:05:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234795AbiJZUEt (ORCPT ); Wed, 26 Oct 2022 16:04:49 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F8B4119BC2; Wed, 26 Oct 2022 13:04:44 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29QIorMI008386; Wed, 26 Oct 2022 20:04:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=Ky2K+rZxKLCb66uyKr5M2WMk95oP3pO36xhDJSOo6yc=; b=gZo/NaYh3zZxlo32Xox1aVbAFrls0RAeJ54NiUp+a7ik1v3ms2NDufGDLWkmPmI1MCC1 BAXoZq+PRllAC32WBprUwiJVC55nrr//xp8Ri3ApXZ8KFL+gYBjRb5fpc69dBnptwaHt yxamgu5Cbk9BzQNVS7snsU9K30Hk92XpNU5sDURj+9hsbbGXVu8tIhf+anB+2wfiR0gG M11n7YQ+SjxJ5HVLAW+24SigvFdj0BrS7z2dg+79xTorFJ4tothlElzEiAXQekUJLo6B 8JcFcKt0XLdhg6uWnG3L3t2ipPVOfmKOZjRcLayntuSLD9DKhfGY2ONA5TC9gMf1pKfg QQ== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfahc87e8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Oct 2022 20:04:41 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29QK4f9i027455 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Oct 2022 20:04:41 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 26 Oct 2022 13:04:40 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski CC: , , , Melody Olvera Subject: [PATCH v3 1/4] dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes Date: Wed, 26 Oct 2022 13:04:26 -0700 Message-ID: <20221026200429.162212-2-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026200429.162212-1-quic_molvera@quicinc.com> References: <20221026200429.162212-1-quic_molvera@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 8PkwljJPbcOT9jt5pEmDy81tiXnjHiwe X-Proofpoint-GUID: 8PkwljJPbcOT9jt5pEmDy81tiXnjHiwe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-26_08,2022-10-26_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=684 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210260111 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747782147877892040?= X-GMAIL-MSGID: =?utf-8?q?1747782147877892040?= Update the bindings to allow for generic regulator nodes instead of device-specific node names. Signed-off-by: Melody Olvera --- Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index 4a50f1d27724..0e7e07975f3a 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -109,7 +109,7 @@ properties: $ref: /schemas/power/qcom,rpmpd.yaml# patternProperties: - '-regulators$': + 'regulators$': $ref: /schemas/regulator/qcom,rpmh-regulator.yaml# required: From patchwork Wed Oct 26 20:04:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 11428 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp462040wru; Wed, 26 Oct 2022 13:07:34 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6/4iZY4v31jYHJMaBKOs06GlYkwIYXbsU7jD1XSBavMIEhlhJSeadwWHAv+xcuuRjy4KQi X-Received: by 2002:a05:6402:4148:b0:440:cb9f:d10f with SMTP id x8-20020a056402414800b00440cb9fd10fmr42122228eda.77.1666814854772; Wed, 26 Oct 2022 13:07:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666814854; cv=none; d=google.com; s=arc-20160816; b=ydATT+AfIyNUU5MfnCGbpDUxqrTAaHEQkEhwnXW8dBHjp2rH11A+FqRLf82JQsmVDH rb1VIi10DBQpQEtonmJl2qCz656ML50e6TZmctYP7p7QMT1zKhqOUibwN2B9Aifc7SIw zwpqJ52GqXsWtv2BM0bJ1XOKOyZGu1b+uhIZmJ+hxWs5oMQIGLtl+ZM5ZszBWzDs9XKj KR+2uMsysoo0Oj5/tbZBAwBgGBejuniULS2tDiYm7i0jTL0ErJCtPYmuMMuavf3sPtIr VPoCGV4xkH3luKHuZvW5DCtmMRjVZLE9Rf1vGZ1VEJUXIulXBwviW8OO+wzQsaK92g6M yctA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yDosjeGjGHK2UYHOmIaxl4hBmdnpZ/nBZe3ArKUemP4=; b=Yr62nR/mZznCyL34heEY91gm9SDBV72jC4RJ6uPrUq8aMRuq6ngIqqYCvaDczgUgbV 0gc97uyfYNbcFR9pycujZ8n43anJRBBxpVbyswOBNyb8ncPEgQsntMBTik0rsXpGEcmX 2GWh9C2SQb8iiVCX28baVG4n6nFLiH+Vae7Mj2wlniBXTPVE3kKF9P4N9/bV+syOPss5 Dkm9NFvweeFJUWyPc2mhZHLqn4qlylraWmRYfL+dUFq81tvs2fb8y5dBwER1r0BXmS+L 9NDK/GPqsV0ioHt7Ln7zun3iRyWgYS6K1exKTzIy0nyU2Ul0qrwqITZRjEpzJk7Mpsym nNDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=N9Kie64l; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gb21-20020a170907961500b0078e2bd72aedsi6876007ejc.811.2022.10.26.13.07.09; Wed, 26 Oct 2022 13:07:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=N9Kie64l; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234904AbiJZUFK (ORCPT + 99 others); Wed, 26 Oct 2022 16:05:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234960AbiJZUEq (ORCPT ); Wed, 26 Oct 2022 16:04:46 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 795D2134DF8; Wed, 26 Oct 2022 13:04:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1666814682; x=1698350682; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yDosjeGjGHK2UYHOmIaxl4hBmdnpZ/nBZe3ArKUemP4=; b=N9Kie64lp0NIOehlfweN4gz3M7tr1+3HPpfLfqA2Ld1PszoNooz2eNEZ 3O9XCu/Z1UxJcKODs/5IxLWu0aJ0E+Yv2x2sSvfVY8xuwLTO2bLAnu1Jv k9UxH6UQk+LbgicNZ1znR2X5BrwtMZNHDAcpYQXUlG3l5LX1eli+Pqkux Q=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 26 Oct 2022 13:04:41 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2022 13:04:41 -0700 Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 26 Oct 2022 13:04:41 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski CC: , , , Melody Olvera Subject: [PATCH v3 2/4] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Date: Wed, 26 Oct 2022 13:04:27 -0700 Message-ID: <20221026200429.162212-3-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026200429.162212-1-quic_molvera@quicinc.com> References: <20221026200429.162212-1-quic_molvera@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747782053171301226?= X-GMAIL-MSGID: =?utf-8?q?1747782053171301226?= Document the QDU1000 and QRU1000 SoC bindings and the boards that use them. Signed-off-by: Melody Olvera Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 207e28260206..410df0bbae70 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -40,6 +40,8 @@ description: | msm8996 msm8998 qcs404 + qdu1000 + qru1000 sa8155p sa8540p sc7180 @@ -76,6 +78,7 @@ description: | mtp qrd sbc + x100 The 'soc_version' and 'board_version' elements take the form of v. where the minor number may be omitted when it's zero, i.e. v1.0 is the same @@ -271,6 +274,19 @@ properties: - qcom,ipq8074-hk10-c2 - const: qcom,ipq8074 + - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform + items: + - enum: + - qcom,qdu1000-idp + - qcom,qdu1000-x100 + - const: qcom,qdu1000 + + - description: Qualcomm Technologies, Inc. Radio Unit 1000 platform + items: + - enum: + - qcom,qru1000-idp + - const: qcom,qru1000 + - description: Qualcomm Technologies, Inc. SC7180 IDP items: - enum: From patchwork Wed Oct 26 20:04:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 11430 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp462074wru; Wed, 26 Oct 2022 13:07:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7fECgi7pzcDZc6rdgGNVHSsMvpL89pwFcX0XHNC5q3AGqpP/kOoKXfE4p5WqJbu3aQIqoE X-Received: by 2002:a17:906:db0c:b0:77b:7d7d:5805 with SMTP id xj12-20020a170906db0c00b0077b7d7d5805mr40372623ejb.726.1666814861640; Wed, 26 Oct 2022 13:07:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666814861; cv=none; d=google.com; s=arc-20160816; b=WfRYlGSXifG+Fllrp2UVTaFi3ZYa4sjtLRRIbrSaiZwW/zwt2cw/fIPTkf5uFvnOvG wW3DibQIQqlcuPTmGJq5CfttP8eR3PFn1LkBfQr6a072oLUsIujHddpqe7V+FwFRYCWi uwNrHm26++8DTXUb8QzOUtkj2iYfad39fykWHj++XFbbl2ZpG/gG48aeIqv6u/Uw2sJ9 sGwAVQ1n/wpLqY7J0PR09p/P0vaqQJB0+YAc5GLY2IIQ8uan1zZ0kkrMcDjPaT5TQS2S ykvNT/T7HauDvLKpjRgUZwRHwwqqVqV1fLEOqsLHbTg1N+DIGyvvufKZf8EjJ0X0rOiR 9AJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9Vh3TpPYeQWbbpkGtMEJ3U6UEwgTVEPfFf7Sea3wpQs=; b=O8+FgOyrx9PyKQM+igKhCOO2beNMIri7yPceBrwyKAUNZOslfrfIF6/rDT15NrDqez Dyzc3O3wc1P+clx7bkjv7STuxASWmYBE2OvFCQ2MjaU2aehxq52wQNAdRtYcx5pUXjM+ BkHtqXNLrzyaa8XSb6MUZaVOoBMECrxunw9jp4cfgYiL9EgmtfayPiEATQgf5e2bsLIv h02sDoJ3JD1BMCICz5ClTJLYbSbJPpLjKh5cS7vscRefBt5xEttLQZlvrZ2xjU6FbyK9 3BIOf25dlx2Pxitv/Ls+rer12n7t9a9g1hswqIRVsQANsDW0/0W70HNsx61CrQPgtDqv gasw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=dELJTcZi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cr18-20020a170906d55200b007807e2ff1besi3260583ejc.918.2022.10.26.13.07.17; Wed, 26 Oct 2022 13:07:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=dELJTcZi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234973AbiJZUFZ (ORCPT + 99 others); Wed, 26 Oct 2022 16:05:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235014AbiJZUEu (ORCPT ); Wed, 26 Oct 2022 16:04:50 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FB2C134DFB; Wed, 26 Oct 2022 13:04:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1666814684; x=1698350684; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9Vh3TpPYeQWbbpkGtMEJ3U6UEwgTVEPfFf7Sea3wpQs=; b=dELJTcZicGJHff/Tcj8vHw9gEyQu/neMdTeD9cbUb4u44cXyMjtsPauI 0/nC6RpGGZeaIU4ThjIWd9SqL/YdsDSU6WnBH7vbWwdwbauHIG91DQI6E zyZTmGsi3mrNhYVR8aGQr4IQJwQ+JraROMXDWQgB2qZcxiRAanZv0QhEC I=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 26 Oct 2022 13:04:42 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2022 13:04:42 -0700 Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 26 Oct 2022 13:04:41 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski CC: , , , Melody Olvera Subject: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Date: Wed, 26 Oct 2022 13:04:28 -0700 Message-ID: <20221026200429.162212-4-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026200429.162212-1-quic_molvera@quicinc.com> References: <20221026200429.162212-1-quic_molvera@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747782060078625339?= X-GMAIL-MSGID: =?utf-8?q?1747782060078625339?= Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller to boot to shell with console on these SoCs. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + 2 files changed, 1433 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi new file mode 100644 index 000000000000..76474106e931 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -0,0 +1,1406 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen: chosen { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domain-names = "psci"; + power-domains = <&CPU_PD0>; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_OFF: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-latency-us = <274>; + exit-latency-us = <480>; + min-residency-us = <3934>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + entry-latency-us = <584>; + exit-latency-us = <2332>; + min-residency-us = <6118>; + arm,psci-suspend-param = <0x41000044>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + entry-latency-us = <2893>; + exit-latency-us = <4023>; + min-residency-us = <9987>; + arm,psci-suspend-param = <0x41003344>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-qdu1000", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,qdu1000-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,qdu1000-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_dt_log_mem: memory@80600000 { + no-map; + reg = <0x0 0x80600000 0x0 0x40000>; + }; + + xbl_ramdump_mem: memory@80640000 { + no-map; + reg = <0x0 0x80640000 0x0 0x1c0000>; + }; + + aop_image_mem: memory@80800000 { + no-map; + reg = <0x0 0x80800000 0x0 0x60000>; + }; + + aop_cmd_db_mem: memory@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + aop_config_mem: memory@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x20000>; + }; + + tme_crash_dump_mem: memory@808a0000 { + no-map; + reg = <0x0 0x808a0000 0x0 0x40000>; + }; + + tme_log_mem: memory@808e0000 { + no-map; + reg = <0x0 0x808e0000 0x0 0x4000>; + }; + + uefi_log_mem: memory@808e4000 { + no-map; + reg = <0x0 0x808e4000 0x0 0x10000>; + }; + + /* secdata region can be reused by apps */ + + smem_mem: memory@80900000 { + compatible = "qcom,smem"; + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: memory@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + xbl_sc_mem: memory@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x40000>; + }; + + /* uefi region can be reused by apps */ + + tz_stat_mem: memory@81d00000 { + no-map; + reg = <0x0 0x81d00000 0x0 0x100000>; + }; + + tags_mem: memory@81e00000 { + no-map; + reg = <0x0 0x81e00000 0x0 0x500000>; + }; + + qtee_mem: memory@82300000 { + no-map; + reg = <0x0 0x82300000 0x0 0x500000>; + }; + + ta_mem: memory@82800000 { + no-map; + reg = <0x0 0x82800000 0x0 0xa00000>; + }; + + fs1_mem: memory@83200000 { + no-map; + reg = <0x0 0x83200000 0x0 0x400000>; + }; + + fs2_mem: memory@83600000 { + no-map; + reg = <0x0 0x83600000 0x0 0x400000>; + }; + + fs3_mem: memory@83a00000 { + no-map; + reg = <0x0 0x83a00000 0x0 0x400000>; + }; + + /* Linux kernel image is loaded at 0x83e00000 */ + + ipa_fw_mem: memory@8be00000 { + no-map; + reg = <0x0 0x8be00000 0x0 0x10000>; + }; + + ipa_gsi_mem: memory@8be10000 { + no-map; + reg = <0x0 0x8be10000 0x0 0x14000>; + }; + + mpss_mem: memory@8c000000 { + no-map; + reg = <0x0 0x8c000000 0x0 0x12c00000>; + }; + + q6_mpss_dtb_mem: memory@9ec00000 { + no-map; + reg = <0x0 0x9ec00000 0x0 0x80000>; + }; + + tenx_mem: memory@a0000000 { + no-map; + reg = <0x0 0xa0000000 0x0 0x19600000>; + }; + + oem_tenx_mem: memory@b9600000 { + no-map; + reg = <0x0 0xb9600000 0x0 0x6a00000>; + }; + + tenx_q6_buffer_mem: memory@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x3200000>; + }; + + ipa_buffer_mem: memory@c3200000 { + no-map; + reg = <0x0 0xc3200000 0x0 0x12c00000>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@80000 { + compatible = "qcom,gcc-qdu1000", "syscon"; + reg = <0x0 0x80000 0x0 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + }; + + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sm6350-gpi-dma"; + #dma-cells = <3>; + reg = <0x0 0x900000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0xf6 0x0>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x9c0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 + &clk_virt SLAVE_QUP_CORE_0 0>; + interconnect-names = "qup-core"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart0: serial@980000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x980000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x984000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x988000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x98c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x990000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x994000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x998000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x998000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + status = "disabled"; + }; + + uart7: serial@99c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x99c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm6350-gpi-dma"; + #dma-cells = <3>; + reg = <0x0 0xa00000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x116 0x0>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xac0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x103 0x0>; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + status = "disabled"; + + uart8: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart8_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa94000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart13: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa94000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart13_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa98000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa98000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa9c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + interrupts = ; + pinctrl-0 = <&qup_i2c15_data_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa9c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + status = "disabled"; + }; + }; + + system_noc: interconnect@1640000 { + reg = <0x0 0x1640000 0x0 0x45080>; + compatible = "qcom,qdu1000-system-noc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x1f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,qdu1000-pdc", "qcom,pdc"; + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, + <94 609 31>, <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0xc400000 0x0 0x3000>, + <0x0 0xc500000 0x0 0x400000>, + <0x0 0xc440000 0x0 0x80000>, + <0x0 0xc4c0000 0x0 0x10000>, + <0x0 0xc42d000 0x0 0x4000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,qdu1000-tlmm"; + reg = <0x0 0xf000000 0x0 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc>; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "qup00"; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + pins = "gpio10", "gpio11"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + pins = "gpio10", "gpio11", "gpio12"; + function = "qup01"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio13"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + pins = "gpio12", "gpio13"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + pins = "gpio12", "gpio13", "gpio10"; + function = "qup02"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio11"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + pins = "gpio14", "gpio15"; + function = "qup03"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + pins = "gpio14", "gpio15", "gpio16"; + function = "qup03"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio17"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + pins = "gpio16", "gpio17"; + function = "qup04"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + pins = "gpio16", "gpio17", "gpio14"; + function = "qup04"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio15"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + pins = "gpio130", "gpio131"; + function = "qup05"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + pins = "gpio130", "gpio131", "gpio132"; + function = "qup05"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio133"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + pins = "gpio132", "gpio133"; + function = "qup06"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + pins = "gpio132", "gpio133", "gpio130"; + function = "qup06"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio131"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart7_rx: qup-uart7-rx-state { + pins = "gpio135"; + function = "qup07"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins = "gpio134"; + function = "qup07"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart8_default: qup-uart8-default-state { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "qup10"; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + pins = "gpio22", "gpio23"; + function = "qup11"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + pins = "gpio22", "gpio23", "gpio24"; + function = "qup11"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio25"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + pins = "gpio24", "gpio25"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + pins = "gpio24", "gpio25", "gpio22"; + function = "qup12"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio23"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + pins = "gpio26", "gpio27"; + function = "qup13"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + pins = "gpio26", "gpio27", "gpio28"; + function = "qup13"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio29"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + pins = "gpio28", "gpio29"; + function = "qup14"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + pins = "gpio28", "gpio29", "gpio26"; + function = "qup14"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio27"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + pins = "gpio30", "gpio31"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + pins = "gpio30", "gpio31", "gpio32"; + function = "qup15"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio33"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart13_default: qup-uart13-default-state { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "qup15"; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + pins = "gpio34", "gpio35"; + function = "qup16"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + pins = "gpio34", "gpio35", "gpio36"; + function = "qup16"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio37", "gpio38"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + pins = "gpio40", "gpio41"; + function = "qup17"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + pins = "gpio40", "gpio41", "gpio30"; + function = "qup17"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ + interrupts = ; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0 0x17420000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x17423000 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x17425000 0x1000>, + <0x17426000 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x17427000 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x17429000 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x1742b000 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x1742d000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,qdu1000-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,qdu1000-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d90000 { + compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <1>; + }; + + gem_noc: interconnect@19100000 { + reg = <0x0 0x19100000 0x0 0xB8080>; + compatible = "qcom,qdu1000-gem-noc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + clock-frequency = <19200000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi new file mode 100644 index 000000000000..074fe126e85e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "qdu1000.dtsi" + +&reserved_memory { + /delete-node/ memory@a0000000; + /delete-node/ memory@b9600000; + /delete-node/ memory@c0000000; + + oem_tenx_mem: memory@a0000000 { + no-map; + reg = <0x0 0xa0000000 0x0 0x6400000>; + }; + + mpss_diag_buffer_mem: memory@aea00000 { + no-map; + reg = <0x0 0xaea00000 0x0 0x6400000>; + }; + + tenx_q6_buffer_mem: memory@b4e00000 { + no-map; + reg = <0x0 0xb4e00000 0x0 0x3200000>; + }; +}; From patchwork Wed Oct 26 20:04:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 11431 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp462109wru; Wed, 26 Oct 2022 13:07:46 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7mmYWD8SY1+SN401bZF54ZSWD6SWdN7N2ZX3Y/D6TbffQMRwLgvMQMvnjripJIZo89AnpW X-Received: by 2002:a05:6402:35c9:b0:45c:de2e:ae1c with SMTP id z9-20020a05640235c900b0045cde2eae1cmr42429004edc.393.1666814866725; Wed, 26 Oct 2022 13:07:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666814866; cv=none; d=google.com; s=arc-20160816; b=vjnrxEP2p3cFtQeY+xvuOWZerHTZVvo5pUrGejeU09BkzR24xLgrVLZK/sfn+3VU97 xGjWzVzQX4fQhuvevwbp70noPPCYyUxaqWFHs0p3AA3LDglJ21c+cj6m8Yt35oT7IejZ Zc4isX+FuTF605iP/gmX9ILFITxF0mXcy0WzC8pW+HJ02LJ7pTG4q48+IQsO7Ch/mGq/ r99F6KGT3CETjgPkJWK0ta1D783aOXWaUPOPZGOwAWBspljR1qYqt3uvWL4ryJw3G7T8 ANuPe79u6Us6vpsLhr84fuXlOEG32Cq6IYaON0S91iY+c2sB5EPk5QB71yzYAkelVbpP VecQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RqyFUSgvzCC/feYsP5SkHq0z5MpcspdNqQuMBiHUac8=; b=TGMk+deEFLw9+yGKNSrs6d7hdd5wH+EOwBZRbIpo/iA9FashF4oX8+w4fphU/LM0rX MBsam7bJaPiRVm0gh5bwG//iPA4gtcAUcqcDmyZSoDtRLXmcPaPFD6HAsWmUqfhcbYZt jmIbkh5s3wgpdtP75wg0apXPh2w3iMOMaxEQnD7Jt3+F6s/4ujw6NT7Kg4lmlmZE4wnc 2RIXhSeF9iJZTd4KDj2nVYv2LzdsEatfFXcz+0EXAxgorhq+dHrVV23tAuMQeqLgAD0r YQLD9fcamBIW0a0W7e6uQ4mUWKFotZvWooffSA8PX8DRr5aYI4H8S5+bzTH8eUVBmEB7 eTtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=H97ihRoy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qf33-20020a1709077f2100b007803e371aedsi7193387ejc.161.2022.10.26.13.07.22; Wed, 26 Oct 2022 13:07:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=H97ihRoy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233614AbiJZUFi (ORCPT + 99 others); Wed, 26 Oct 2022 16:05:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234912AbiJZUEw (ORCPT ); Wed, 26 Oct 2022 16:04:52 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72A89DE7; Wed, 26 Oct 2022 13:04:46 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29QJrNJl002105; Wed, 26 Oct 2022 20:04:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=RqyFUSgvzCC/feYsP5SkHq0z5MpcspdNqQuMBiHUac8=; b=H97ihRoyG+tk+Mbc2v8WEA7jSppzxMIkS7JazgHZ7EP45djvRQDx8xXj7zG1GLlzayLr 1lYuUsJQKJkbhHEzLW4HR6bmL3J6iqWfggY+5LBdFwXkj/EXXtQmdb44WrRvReAVmIbQ Gi/pDXKzmqaFcRhCeOYbd4q2F123CqKatCq8PGGWbuFuwn5h1Ochfce6OLYod/Kd/fno pdFEgeV4KZ8Avy/Qfn8zU/WVdym5NZMHjIg/w9CFUGfkdSl87LHskDncMm/O8TMju2XQ O2twxRVyF4WAHvGDo9WI8wmIMtwpyl1JYjLw8qtt+vDDyROWB72mpbCR63tVd741sTTz 0w== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfahc87ec-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Oct 2022 20:04:43 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29QK4grn019017 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Oct 2022 20:04:42 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 26 Oct 2022 13:04:41 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski CC: , , , Melody Olvera Subject: [PATCH v3 4/4] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Date: Wed, 26 Oct 2022 13:04:29 -0700 Message-ID: <20221026200429.162212-5-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026200429.162212-1-quic_molvera@quicinc.com> References: <20221026200429.162212-1-quic_molvera@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Y95sBJLCstG9midtj7nXE4UAZ6V1hbrv X-Proofpoint-GUID: Y95sBJLCstG9midtj7nXE4UAZ6V1hbrv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-26_08,2022-10-26_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210260111 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747782065594674961?= X-GMAIL-MSGID: =?utf-8?q?1747782065594674961?= Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 245 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qru1000-idp.dts | 245 +++++++++++++++++++++++ 3 files changed, 492 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0558d3389e5..8ee949a58ce7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -51,7 +51,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts new file mode 100644 index 000000000000..e4fd6e2b656b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include "qdu1000.dtsi" +#include "pm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QDU1000 IDP"; + compatible = "qcom,qdu1000-idp", "qcom,qdu1000"; + + aliases { + serial0 = &uart7; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; +}; + +&apps_rsc { + regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vph_pwr>; + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>; + vdd-l6-l9-supply = <&vreg_s6a_0p9>; + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>; + vdd-l13-l16-l17-supply = <&vph_pwr>; + + vreg_s2a_0p5: smps2 { + regulator-name = "vreg_s2a_0p5"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <570000>; + }; + + vreg_s3a_1p05: smps3 { + regulator-name = "vreg_s3a_1p05"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-name = "vreg_s5a_2p0"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-name = "vreg_s6a_0p9"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s7a_1p2: smps7 { + regulator-name = "vreg_s7a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_s8a_1p3: smps8 { + regulator-name = "vreg_s8a_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name = "vreg_l1a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l2a_2p3: ldo2 { + regulator-name = "vreg_l2a_2p3"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name = "vreg_l3a_1p2"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p8: ldo5 { + regulator-name = "vreg_l5a_0p8"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l6a_0p91: ldo6 { + regulator-name = "vreg_l6a_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + + }; + + vreg_l8a_0p91: ldo8 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <888000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vreg_l9a_0p91: ldo9 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l10a_2p95: ldo10 { + regulator-name = "vreg_l10a_2p95"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l11a_0p91: ldo11 { + regulator-name = "vreg_l11a_0p91"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l16a_1p8: ldo16 { + regulator-name = "vreg_l16a_1p8"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p3: ldo17 { + regulator-name = "vreg_l17a_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name = "vreg_l18a_1p2"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts new file mode 100644 index 000000000000..445124e84485 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include "qru1000.dtsi" +#include "pm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QRU1000 IDP"; + compatible = "qcom,qru1000-idp", "qcom,qru1000"; + + aliases { + serial0 = &uart7; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; +}; + +&apps_rsc { + regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vph_pwr>; + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>; + vdd-l6-l9-supply = <&vreg_s6a_0p9>; + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>; + vdd-l13-l16-l17-supply = <&vph_pwr>; + + vreg_s2a_0p5: smps2 { + regulator-name = "vreg_s2a_0p5"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <570000>; + }; + + vreg_s3a_1p05: smps3 { + regulator-name = "vreg_s3a_1p05"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-name = "vreg_s5a_2p0"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-name = "vreg_s6a_0p9"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s7a_1p2: smps7 { + regulator-name = "vreg_s7a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_s8a_1p3: smps8 { + regulator-name = "vreg_s8a_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name = "vreg_l1a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l2a_2p3: ldo2 { + regulator-name = "vreg_l2a_2p3"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name = "vreg_l3a_1p2"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p8: ldo5 { + regulator-name = "vreg_l5a_0p8"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l6a_0p91: ldo6 { + regulator-name = "vreg_l6a_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + + }; + + vreg_l8a_0p91: ldo8 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <888000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vreg_l9a_0p91: ldo9 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l10a_2p95: ldo10 { + regulator-name = "vreg_l10a_2p95"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l11a_0p91: ldo11 { + regulator-name = "vreg_l11a_0p91"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l16a_1p8: ldo16 { + regulator-name = "vreg_l16a_1p8"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p3: ldo17 { + regulator-name = "vreg_l17a_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name = "vreg_l18a_1p2"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +};