From patchwork Wed Oct 26 19:42:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 11411 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp453395wru; Wed, 26 Oct 2022 12:44:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6ofjE3DUQOXdOm8FJJRw+TRSGhpd84xf3O4eMwYl62QMt9zxHwpVem/0GniXlowkyybgHb X-Received: by 2002:a17:902:ea06:b0:185:4c1f:7460 with SMTP id s6-20020a170902ea0600b001854c1f7460mr45895908plg.99.1666813480787; Wed, 26 Oct 2022 12:44:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666813480; cv=none; d=google.com; s=arc-20160816; b=fbaTPiXvnGhQ22lJ5friWI8RGnTFeqze85XjK67uYmKXKhC2MWAIWQEOkQRoL1gu+Y eZEYwQ9p+6/edUToIO2A+pYBXwiFHykTks13NNcjjK2VjOHrVQHmXvNEYa9Es19W6Vhd SzvLrgp+fCKUrQ8vDE2cmor+1tgZZcy7XKk2XhexHccJJ5eget3ri+xqzlbpZ+vkxM0S Jh1VcrMlbfPZ5cgezoxKdD5Ki/tLrer6eXrdp9wZ23FIIuQ8WqLpMypBTBKUn7vncO6C P3G+f/V6PSxTPg8/PW0vzkEbzWnGYepW5VlWSDrkUzXna2Q71KhTAiG+TnWO2PBEstF2 av1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PdKdi7U4SmFj0opqdWI8W6jamLQm1HEBWFpXKlflndY=; b=N2Z4OAnRFbr8xm2KfF6tX3kf9Spt840/UG0Qjjb/1/zgzmOFfJ0kegstB27gPLNRNu Jj3wC/IqICZLOErp2tAhW2O+O+JoFVP4jXFNx/cUvjzGoQlDT5beVWFgFffP0DA7t1BP NHQmitWQx80uaOOBsAFOubkgtiMWcBoda6uht4qmxfT0rORG4m6ViiMqSJw28ano5ykm HNQmSgv6Xt/TB+xhe/FUDuLWYkfTLYh7EkW3RUq+Acdrxn9UMZ947F7rym54T1VhBRFC E4Igj3OI+6PRedcDUqlGWZgJxrznYtX4gKsYKxgw2k0i5iBwajLULevRys0uyssrSdmG 9HYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=SWTE6P9Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k2-20020a17090a3e8200b002130f4827afsi3616958pjc.87.2022.10.26.12.44.27; Wed, 26 Oct 2022 12:44:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=SWTE6P9Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233856AbiJZTnC (ORCPT + 99 others); Wed, 26 Oct 2022 15:43:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235065AbiJZTmn (ORCPT ); Wed, 26 Oct 2022 15:42:43 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EEC4CD5F2 for ; Wed, 26 Oct 2022 12:42:29 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9so4971789pll.7 for ; Wed, 26 Oct 2022 12:42:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PdKdi7U4SmFj0opqdWI8W6jamLQm1HEBWFpXKlflndY=; b=SWTE6P9QNXY1Z9Rs2EGlY2N1EtdUHngKz+3tEaOqDETcbCRxqr5XVtVo+tzidBfnly rdUMvhgihdoOVRoThHw1Lqo55HesJYQqRoXpK+SsSHkWsd22be5pn11cdJr9iYT7Nptg k1K/YF78Bo9W5QKKZOPDz7epnyS4bNuYrDNDs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PdKdi7U4SmFj0opqdWI8W6jamLQm1HEBWFpXKlflndY=; b=Rhi5JkwKFxmM/em/Lvxf+QGluPSSCWHwl5/xbN9MwVvudKnc7PxCQzGHZSYEMjXcR6 7QNFF+9ahsTMbV+61dQ2HrVSX119qQO638AY/nRycUu1KYSWs9uGfeQyH/LDYH7jBclg 7+AfnixKGXoYK5pQg6qZJWOMrIe0HtigcK61/lNomjVJNIqiK9I1z/A7DPEdcCDQT9zB Vp505lVvL8JaqVDoYdzdAMRgTzVZULO+aEa60eDf0umFUjxQ4Y9MVqmVHkKoNgP2xfib 3wYnYnVc4KMmAi47PDbyv00CCo08vlV0DCqbDX0XnH2PhyzGQKa774RcAuFUehlutKfp oFpQ== X-Gm-Message-State: ACrzQf0uSeQoRnZVd3qLRwLzpsu2j2TbNhGjuVUgc/mB0GaqbSeu+5ez 8FqRPW9krSl7kYez1j6oII8Rgw== X-Received: by 2002:a17:903:22cb:b0:186:a8ae:d0ff with SMTP id y11-20020a17090322cb00b00186a8aed0ffmr17416652plg.71.1666813348867; Wed, 26 Oct 2022 12:42:28 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:c9e3:74f3:6b2b:135]) by smtp.gmail.com with UTF8SMTPSA id h11-20020a170902f2cb00b001837463f654sm3245037plc.251.2022.10.26.12.42.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 12:42:28 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Guo , linux-mmc@vger.kernel.org, Adrian Hunter , Shawn Lin , Michal Simek , Sascha Hauer , Bjorn Andersson , Thierry Reding , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Jonathan Hunter , Andy Gross , Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Konrad Dybcio , Al Cooper , Fabio Estevam , Florian Fainelli , NXP Linux Team , Haibo Chen , Sowjanya Komatineni , Brian Norris , stable@vger.kernel.org Subject: [PATCH v4 1/7] mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI Date: Wed, 26 Oct 2022 12:42:03 -0700 Message-Id: <20221026124150.v4.1.Ie85faa09432bfe1b0890d8c24ff95e17f3097317@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221026194209.3758834-1-briannorris@chromium.org> References: <20221026194209.3758834-1-briannorris@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747780612221044135?= X-GMAIL-MSGID: =?utf-8?q?1747780612221044135?= Several SDHCI drivers need to deactivate command queueing in their reset hook (see sdhci_cqhci_reset() / sdhci-pci-core.c, for example), and several more are coming. Those reset implementations have some small subtleties (e.g., ordering of initialization of SDHCI vs. CQHCI might leave us resetting with a NULL ->cqe_private), and are often identical across different host drivers. We also don't want to force a dependency between SDHCI and CQHCI, or vice versa; non-SDHCI drivers use CQHCI, and SDHCI drivers might support command queueing through some other means. So, implement a small helper, to avoid repeating the same mistakes in different drivers. Simply stick it in a header, because it's so small it doesn't deserve its own module right now, and inlining to each driver is pretty reasonable. This is marked for -stable, as it is an important prerequisite patch for several SDHCI controller bugfixes that follow. Cc: Signed-off-by: Brian Norris Acked-by: Adrian Hunter Reviewed-by: Florian Fainelli --- Changes in v4: - Whitespace fixup - Add Adrian's Ack Changes in v3: - New in v3 (replacing a simple 'cqe_private == NULL' patch in v2) drivers/mmc/host/sdhci-cqhci.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 drivers/mmc/host/sdhci-cqhci.h diff --git a/drivers/mmc/host/sdhci-cqhci.h b/drivers/mmc/host/sdhci-cqhci.h new file mode 100644 index 000000000000..cf8e7ba71bbd --- /dev/null +++ b/drivers/mmc/host/sdhci-cqhci.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2022 The Chromium OS Authors + * + * Support that applies to the combination of SDHCI and CQHCI, while not + * expressing a dependency between the two modules. + */ + +#ifndef __MMC_HOST_SDHCI_CQHCI_H__ +#define __MMC_HOST_SDHCI_CQHCI_H__ + +#include "cqhci.h" +#include "sdhci.h" + +static inline void sdhci_and_cqhci_reset(struct sdhci_host *host, u8 mask) +{ + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && + host->mmc->cqe_private) + cqhci_deactivate(host->mmc); + + sdhci_reset(host, mask); +} + +#endif /* __MMC_HOST_SDHCI_CQHCI_H__ */ From patchwork Wed Oct 26 19:42:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 11412 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp453443wru; Wed, 26 Oct 2022 12:44:51 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7LJmUXu2GSFd3TKakmxQmr+79XLX8E9Fxag7OxQh2HtNk4JLNa3dGwlpBRmcG38pgqG74D X-Received: by 2002:a17:90b:4a4c:b0:213:622f:62fa with SMTP id lb12-20020a17090b4a4c00b00213622f62famr2832901pjb.137.1666813490766; Wed, 26 Oct 2022 12:44:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666813490; cv=none; d=google.com; s=arc-20160816; b=snq81rhs5mZry6vqcdrUL6zAmkLloAsL/bYD+s5Cu71jUCiE54CRyJaqVTbNwfu5o1 cKbrHFLItgIyA+YRwqCfikT0/J+6QB+155t/HcIg8Wohohj4XsjNv0fGIRq3zx4MGeWa qCOot8vQJnpk+F1s5M4HZHGde5Rkx1kyBMxNMn9JmHbKwOzFO1el7TCS/jC0Mu0oSWBA GKgo7ESqoISQ0n5bUAVGTbwnNBrU5l99oT0uiepC7OWW538JyqcyTDUL8ESZo+IDxleM EkYC5/tvEux7Y05K+pAv4bMcqLMgxciXYkLzElM8jvSI7OJWPYTaiAdoBohrHZ9er2TK iYnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LFkN1+K+3c6IFRt45FwrvvUQl9YtYqgay0mkP7wZUzI=; b=iw/RNruAPk2z0PE0eEY+S4x/dbbbVOz0NaGIrOAUk3/pw/mNFHG4JCjpXHiOc0WB8F Mm+IEl23iQqMUhb8/GRwdyi7NpdYRbEU6BOaBL58lO+EgBekePyb5JnlYaMNa7nIHvbZ RNnxljAdZZreGG82ej1h9SmjpmF2CMSljTQqR2ndRzJBbIx9nUxJnjMLTI9b4n0AZvSe KEN8ns474wfgoUO48o2D1C3bwcw7fz8esE+Xm9RWALdwt9beqiS4xBrdei649Xf9Gsvt Fs/M9wpWFlmf2u3NftJaXqvJOkA2ZRyHxA1FAFYaBsy6WB3OvIN294VFq5ApmmedkACH 7NIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b="Ptd/qvcQ"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. 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When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but one particular case I hit commonly enough: mmc_suspend() -> mmc_power_off(). Typically we will eventually deactivate CQE (cqhci_suspend() -> cqhci_deactivate()), but that's not guaranteed -- in particular, if we perform a partial (e.g., interrupted) system suspend. The same bug was already found and fixed for two other drivers, in v5.7 and v5.9: 5cf583f1fb9c ("mmc: sdhci-msm: Deactivate CQE during SDHC reset") df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers") The latter is especially prescient, saying "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." So like these other patches, deactivate CQHCI when resetting the controller. Do this via the new sdhci_and_cqhci_reset() helper. This patch depends on (and should not compile without) the patch entitled "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Fixes: 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") Cc: Signed-off-by: Brian Norris Reviewed-by: Guenter Roeck Acked-by: Adrian Hunter --- Changes in v4: - Improve for-stable cherry-picking notes - Add Adrian's Ack Changes in v3: - Refactor to a "SDHCI and CQHCI" helper -- sdhci_and_cqhci_reset() Changes in v2: - Rely on cqhci_deactivate() to safely handle (ignore) not-yet-initialized CQE support drivers/mmc/host/sdhci-of-arasan.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 3997cad1f793..cfb891430174 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -25,6 +25,7 @@ #include #include "cqhci.h" +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 @@ -366,7 +367,7 @@ static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); From patchwork Wed Oct 26 19:42:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 11414 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp453642wru; Wed, 26 Oct 2022 12:45:22 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7QfVh5G5cmApHLBHcUGbFPzhIDzMU6bSWCPu43jJVQ2U7RstWiEzICFnE4FU+20j/u880+ X-Received: by 2002:a63:7e4d:0:b0:43c:8ce9:2a9f with SMTP id o13-20020a637e4d000000b0043c8ce92a9fmr38084428pgn.528.1666813522517; Wed, 26 Oct 2022 12:45:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666813522; cv=none; d=google.com; s=arc-20160816; b=ZQaBtMlKh0AywIFXEY4VpPofe4MCannN79hGrpWWCvNnkZcey3HbFDnrQFyf9qWHDT t9v8jiqL9bo2fd6aZNukySZ4xV539FF9Qp4S1DBUhvLn7ASpIEWk2U27crC6ucpSckxc DJIO8HMBSGvqWirB5vab6AlNrbxyU+MxVaULvZ6/hc5H2PWGj67sxxOAdATy74g8MX1K +VwYAqj2t8DxBNef9RNmG8fz1WDgIof0UaC8v1WMK+1mKmXl5BiPD2i10nBPt4ciZRos vzEvAyKJmhhyF51oWTgok4VbeTba+HqCfjR+Pe8E+78euW/HeC+imhzfiZXT4dPGR/1v OI+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OP/jpiXLlD32ihmuaQEisQ+o2cyp9ywlsHpK/BoVXYw=; b=rbaAiqasjn4XCYoWqqtO++3noWlAiSHgkZT19dxjM072JEFqczbJerY5NP4zaS4Jgz P8erTW60KV9Ir4jSTHB8ZrKF5qccNnCHbVr8qGZ2iO3TPs+kNr1V3HIe8FuhzFvHvM0T O07Db7ZE9ccupRQGfBx1aX2wAXoVrH+V0a3nnXFnVQfyXfxN5ob+IA/ngvjOKMZiFI0u KSLSOL+MjfraKU4TcGPK6j+dE9uCNg2qbbemkhWbgzDrm/TYU7q2pZEoWw5gXSW4izhg HV7SV0ZGo8cIFLq45SmnLOBeo7n8eQBVZi/GuCpbRhO+WfNPP36Ys1lS9hQuLS/7IlYV RWNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=jIbj4VPf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k17-20020a170902f29100b00180680b8f1bsi6381391plc.264.2022.10.26.12.44.58; Wed, 26 Oct 2022 12:45:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=jIbj4VPf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234321AbiJZTne (ORCPT + 99 others); Wed, 26 Oct 2022 15:43:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235051AbiJZTms (ORCPT ); Wed, 26 Oct 2022 15:42:48 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3514FBCCF for ; Wed, 26 Oct 2022 12:42:34 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id f23so15202195plr.6 for ; Wed, 26 Oct 2022 12:42:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OP/jpiXLlD32ihmuaQEisQ+o2cyp9ywlsHpK/BoVXYw=; b=jIbj4VPfhvDYQIKBdqCPB7rCCl8cb8N0uMtORU/8idM1msip0PJNFW8t1Tsq6UghFQ 1NVt00V8DqN9+0rdST/hMLOLcAixEjGcC4+0AJtX6OPzOYc7mVA+cH/cYq9oKQY+vYPR Cr8pF7qUMSS4oL2KezQ3wAEovOTMTkvDVNa2s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OP/jpiXLlD32ihmuaQEisQ+o2cyp9ywlsHpK/BoVXYw=; b=wyrcEbart3vRjnwA+yJSzkaApp8pwaTlianEmki3GDfmNUTjCt9ZMrUoYcqFwcRSSd MguVh9jQdIFq4BAT2zhK8Ga9GSNtNYlu9WWDB7K7R2ggViPHv0WVEsDAxoCOx7P57SRZ z+/Fj/+ERGsPxmWStXCGG+inDDRNBvweCJ6oumrCxePV5Ur40RpJyW8GuZH7JDzY74eB isp+25tolUwqg6WH1V6jzs3TY6k5Y9WD2HkoHfsbTjLOJrjidP10+vTtnl7DizsPcoQ/ f1LwcvhxWcivOPfM5zj4zrfZvmmRvsbo3a0tV6IMxtPRoIpc/1HH+oq8lcsGLn8P9vVQ NsKA== X-Gm-Message-State: ACrzQf05N8DDcxMb50l5f6AwCq4JaIzrcqAmYs90i864mMR0BtQsyaIB PL4NrOT/oNomXzJbsXgdlWYHcg== X-Received: by 2002:a17:902:b18d:b0:186:9bb5:a92 with SMTP id s13-20020a170902b18d00b001869bb50a92mr20552157plr.11.1666813354356; Wed, 26 Oct 2022 12:42:34 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:c9e3:74f3:6b2b:135]) by smtp.gmail.com with UTF8SMTPSA id e21-20020a635015000000b004582e25a595sm3151642pgb.41.2022.10.26.12.42.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 12:42:33 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Guo , linux-mmc@vger.kernel.org, Adrian Hunter , Shawn Lin , Michal Simek , Sascha Hauer , Bjorn Andersson , Thierry Reding , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Jonathan Hunter , Andy Gross , Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Konrad Dybcio , Al Cooper , Fabio Estevam , Florian Fainelli , NXP Linux Team , Haibo Chen , Sowjanya Komatineni , Brian Norris Subject: [PATCH v4 3/7] mmc: sdhci-brcmstb: Fix SDHCI_RESET_ALL for CQHCI Date: Wed, 26 Oct 2022 12:42:05 -0700 Message-Id: <20221026124150.v4.3.I6a715feab6d01f760455865e968ecf0d85036018@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221026194209.3758834-1-briannorris@chromium.org> References: <20221026194209.3758834-1-briannorris@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747780656418490044?= X-GMAIL-MSGID: =?utf-8?q?1747780656418490044?= [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. I only patch the bcm7216 variant even though others potentially *could* provide the 'supports-cqe' property (and thus enable CQHCI), because d46ba2d17f90 ("mmc: sdhci-brcmstb: Add support for Command Queuing (CQE)") and some Broadcom folks confirm that only the 7216 variant actually supports it. This patch depends on (and should not compile without) the patch entitled "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Fixes: d46ba2d17f90 ("mmc: sdhci-brcmstb: Add support for Command Queuing (CQE)") Signed-off-by: Brian Norris Reviewed-by: Florian Fainelli Acked-by: Adrian Hunter --- Changes in v4: - Improve commit notes - Add Adrian's Ack - Add Florian's Reviewed-by Changes in v3: - Use new SDHCI+CQHCI helper Changes in v2: - Rely on cqhci_deactivate() to handle NULL cqe_private, instead of moving around CQE capability flags drivers/mmc/host/sdhci-brcmstb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index aff36a933ebe..55d8bd232695 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -12,6 +12,7 @@ #include #include +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "cqhci.h" @@ -55,7 +56,7 @@ static void brcmstb_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); /* Reset will clear this, so re-enable it */ if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK) From patchwork Wed Oct 26 19:42:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 11419 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp454046wru; Wed, 26 Oct 2022 12:46:32 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4w5/1sQPpEVhR0j7vxjZGJkmCHMxfz1sABvjhzUnrQuX2fPQ7Yl5jc3k6jRHm3IiZmYe92 X-Received: by 2002:a17:907:75e5:b0:78d:cb12:6dcc with SMTP id jz5-20020a17090775e500b0078dcb126dccmr38292894ejc.550.1666813592500; Wed, 26 Oct 2022 12:46:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666813592; cv=none; d=google.com; s=arc-20160816; b=TK0jLpspD6JoVHx819sr1YwwTUm8DiDxkN8bx1k05k26GbKyN42Cy4AhyCbOnAu0gU p1bZRTZiHxoWg6ZhXvSX8cGyboQgvc/0ixDqbSKYvYyeeC8ojAP+59smMgIXGwJIpcJW 1K05CWI9SHguWJWRzRSxNCcEiVE01WgcOA69M3iVFK/uya2LYh3B/eRKISfD89wFDmS/ 3yj+LSu0Qj3yCOATLqK+iqg8BlhKtIVqL5laBC2QqjmRrI4YR0QVHRYxRSPF6YuZrj9r ub3Y8F9BQBnpr8Zb28uBAxFXVxozAy90LhAuZIRzfmTY4MYMpcLDo+eonDiqjRbw1FGx bnCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y45Z9F5+/R9uqywDzN7icoG5SzFxInaah2IApmdYfxw=; b=qgfhpejVjdtS0IvZM/XcHZGbMlFPmy+uyvXNa8GS0ZeTmIR5qzi6oSDtSHBcualia5 ZjRZpx33U1ZTpaPBy0173HBWeO0hXwvw6y9v/K1HBQL1hwFSxW/exQ6D3oTqayLCsxyD ybvpPxJ6jBrMweRCE1qe6HEIADiwMZICb1ZTgr8JrMcXoYx8FW9doUtKt135K0beLNfs Z6utmQ5QDrfsqDiH22cUjGTUam8M3JxBB9AXjk8VH3loiPSABnbIzZRuMQKrENFSw/3l 3xgz4h6EQWckHBbXVgEoKGNwzogWg16Gv/tNwjB/VL7guDY41EBbULniQezTfGlgctCZ urlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=Iy9rHMtN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o14-20020a1709064f8e00b0078d20d71475si3088050eju.413.2022.10.26.12.46.08; Wed, 26 Oct 2022 12:46:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=Iy9rHMtN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235051AbiJZTnh (ORCPT + 99 others); Wed, 26 Oct 2022 15:43:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234580AbiJZTm4 (ORCPT ); Wed, 26 Oct 2022 15:42:56 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 860C9105361 for ; Wed, 26 Oct 2022 12:42:37 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id jo13so11595602plb.13 for ; Wed, 26 Oct 2022 12:42:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y45Z9F5+/R9uqywDzN7icoG5SzFxInaah2IApmdYfxw=; b=Iy9rHMtN9Rv2jganlhmWgo4QVH8Z7RUUGpg2ylFrGCK3WZN2XS7hhrGR9N3EkAipMB Iwx6g7aDxY2T1V1+Jm761uVArvrg2ri/fPYwbk0fiE4ko/o4cdje9BwYuxpIrfgvmK72 KB/rlobuS5mS4s+bNIjyb46By3UIsEOQ4qZwA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y45Z9F5+/R9uqywDzN7icoG5SzFxInaah2IApmdYfxw=; b=w4LZCNjHR8rFCfS73SfTgfzk+HwrTA07NQztTTq3iCl916H0QwC+KGg0JF3KswOUlC CbyOrEl8dIbbEAV3p4OxPhDxHl/MjjTUj33J88T2fxy3fK//LHTF4o1FuFn1hScQrCNd a+5E00NfUwfk/q4U/7paN63HiO0OmU2YjU2yYZhkkMzaP1qII3nLKNQCF+VkFOZGJxgE e2YSTK79eQJgvu1F0vXWwNbJS4GkICrJ50GBpSjbpClfr//Bx4C8gfRjXkXTrV3Fct82 BNo9e+/jHxPIrTGC+AJbnYocI38hrGFhz6nwULJTLdwcHigVIweqpq/W1jbCLERkL8x5 1n2g== X-Gm-Message-State: ACrzQf0bTaFCV4hEo1qrgMAGJ1+OZ/5Qr/nhb6iaTMm1matqWqleWhYY uZXz//Ybrxsi/uKGbFWF+j1O5iNqVDKt8w== X-Received: by 2002:a17:90b:1e49:b0:20b:36a3:aba6 with SMTP id pi9-20020a17090b1e4900b0020b36a3aba6mr6128720pjb.2.1666813357227; Wed, 26 Oct 2022 12:42:37 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:c9e3:74f3:6b2b:135]) by smtp.gmail.com with UTF8SMTPSA id s27-20020aa78bdb000000b0056bc30e618dsm3341776pfd.38.2022.10.26.12.42.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 12:42:36 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Guo , linux-mmc@vger.kernel.org, Adrian Hunter , Shawn Lin , Michal Simek , Sascha Hauer , Bjorn Andersson , Thierry Reding , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Jonathan Hunter , Andy Gross , Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Konrad Dybcio , Al Cooper , Fabio Estevam , Florian Fainelli , NXP Linux Team , Haibo Chen , Sowjanya Komatineni , Brian Norris Subject: [PATCH v4 4/7] mms: sdhci-esdhc-imx: Fix SDHCI_RESET_ALL for CQHCI Date: Wed, 26 Oct 2022 12:42:06 -0700 Message-Id: <20221026124150.v4.4.I7d01f9ad11bacdc9213dee61b7918982aea39115@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221026194209.3758834-1-briannorris@chromium.org> References: <20221026194209.3758834-1-briannorris@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747780729525810428?= X-GMAIL-MSGID: =?utf-8?q?1747780729525810428?= [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. This patch depends on (and should not compile without) the patch entitled "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Fixes: bb6e358169bf ("mmc: sdhci-esdhc-imx: add CMDQ support") Signed-off-by: Brian Norris Reviewed-by: Haibo Chen Acked-by: Adrian Hunter --- Changes in v4: - Add dependency notes - Add Adrian's Ack Changes in v3: - Use new SDHCI+CQHCI helper - Add Reviewed-by Changes in v2: - Drop unnecessary ESDHC_FLAG_CQHCI check drivers/mmc/host/sdhci-esdhc-imx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 55981b0f0b10..b297c3c360eb 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -25,6 +25,7 @@ #include #include #include +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "sdhci-esdhc.h" #include "cqhci.h" @@ -1288,7 +1289,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) static void esdhc_reset(struct sdhci_host *host, u8 mask) { - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); From patchwork Wed Oct 26 19:42:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 11415 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp453653wru; Wed, 26 Oct 2022 12:45:24 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4I45MHH/dBvEJCYFrXSF6Bht+Pe6eKzCm6fx0KxCT//xpMIa4dCaz+xCRzPAMaiEqIFpjh X-Received: by 2002:a63:fe13:0:b0:452:2b86:50fb with SMTP id p19-20020a63fe13000000b004522b8650fbmr3899761pgh.167.1666813524357; Wed, 26 Oct 2022 12:45:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666813524; cv=none; d=google.com; s=arc-20160816; b=U/P3+pGt+dBYGvP+/4b9W4kgHhNWZ3D5+jSQzEYN7EhqSg+QfR61voNSzfZ4NgxonJ 8L7WIA9tozD+pBpvSc5jmFfu0KQl9WvlpSAHBnlqwAf5aHwZoNI6geefl4z3DxTgIFwd FcGJywK+klEJih8UbvLg/0NXEAF380Euf7RSwPK9ltf6rYqk0ozGo5vLIUQpABY6Y/iZ FgNlBnkP+qNgCJijD4tT+KxDwKhjIbCqxzMUBjwPlR9QtH/rYXSZojYiHPudJS5gmdyO zU3YsKJUwZYhXNwWKSKxz9oOoc6clz9XFCrpQB0ChYUFThWuGJufMwkDGBiVe+XrIPIK uJMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Fb+b4UKJ1KFBJbCRol+gACElv5iiq7jjhJ1g0l5c5FA=; b=Z2ZoXEHI3r+ou/sEo3FcApZbbCvKNune0j1GkirHHznM9ahYsqaNOXm/GN8MIOjPW0 fOAN5s4iuLxme+ToHxrDgVbbu71M+vI9Xsv8mbD+waYxZYqEHDXs/+/2r+icFwD/J77s zy07396NZulH+84kxjyWBY226xjhdQHsGpu5ZfMgKONPprip3LktZXgYcBwpAJBk170W 9sDkBMjUnfktqfHH+iyNDWeibtA6JZRqpNZtIiaTLJa76veGrBmZZfB45S7LgkrqmIw3 VirMf72qNXp31cCvYcbY7WokCdbJqj8mSo5RaO78fQ8AvchbrPV7NwfR558Tl5Kh7uO1 GQ5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=hRt2H2uD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. 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We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. This patch depends on (and should not compile without) the patch entitled "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Fixes: 3c4019f97978 ("mmc: tegra: HW Command Queue Support for Tegra SDMMC") Signed-off-by: Brian Norris Acked-by: Adrian Hunter --- Changes in v4: - Add dependency notes - Add Adrian's Ack Changes in v3: - Use new SDHCI+CQHCI helper Changes in v2: - Drop unnecessary 'enable_hwcq' check drivers/mmc/host/sdhci-tegra.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 413925bce0ca..c71000a07656 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -28,6 +28,7 @@ #include +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "cqhci.h" @@ -367,7 +368,7 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; u32 misc_ctrl, clk_ctrl, pad_ctrl; - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); if (!(mask & SDHCI_RESET_ALL)) return; From patchwork Wed Oct 26 19:42:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 11416 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp453669wru; Wed, 26 Oct 2022 12:45:27 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6OXqAjEeX/tNPsII6ORYtmlWEE5sxTANXizP4Sgj8rJGU31wIu6Em3RRH+L8zfy+aI0z5A X-Received: by 2002:a17:902:eb8c:b0:186:de22:9117 with SMTP id q12-20020a170902eb8c00b00186de229117mr4381124plg.41.1666813526851; Wed, 26 Oct 2022 12:45:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666813526; cv=none; d=google.com; s=arc-20160816; b=KTDwg0WTdDHdFzJoGprbN+oLy08F7sAMqOyAcH3/mnpubkUY7AEX9rbsY1+mlQdO7t luT3cZrgAg95qwBfGdNwVY+SM9fBYD/EONcO/jJX/puZsMOX3y2ScayGILrzhCobfYH0 LXi7LTUN/DP+VoI7r/jcgoFtTpIznjY0NQC8Okg9097L9nwj3NCc8WndKnNcMtCVLta2 bE4H5YVerYmUinJM5aOyrRyQIPVzG7wr6OcgUgCrFVoq1Z00BRlECCY/TN5gq/rO7MKg AkxNelsTbdqn4OlmvulhtXfiNI/d3v3zDltr7ogUxjUm3tzPkvwFLw9X7JsJfaRINfDE BIyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uFvAy1Yx9bF2vsbUT1HqGJtHQU9f7u8fB33iw92Qf8Q=; b=hnnWaw6SmX/Gxm+6TQXJcLcpyeCnwGb9ezkq9TL67CTgTkAXpXPMRvKv3f000edfit 1cf+Z7dlbPth5TUp+tUhnme4UgprV7y5X3V6zH7PgVomqcz9aUfsNk9Q8jjAUFwGQ6d5 6igCQBKXnByO/b/IKGRdvOlB8cMbb66kP9bU5nq09Lmkz0HQk3rVoLysv+ul+LSY7tA2 DCXFVykVlZ2zp05hvaLV1cCDxTVMRs15u+S/9AX55+2jE+2ZafZ7uOySHimjsLiDPfbv Bg/d2qmn0t73CnoBvyRIYkfjPbc4YGNN+/XittH6VVTDfpyMfzxMrVnA5/Np8BsQ34Rs Frxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=oKBbVUwj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d6-20020a056a0010c600b0055f8c0018b0si8280613pfu.288.2022.10.26.12.45.13; Wed, 26 Oct 2022 12:45:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=oKBbVUwj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234792AbiJZTnr (ORCPT + 99 others); Wed, 26 Oct 2022 15:43:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235034AbiJZTnA (ORCPT ); Wed, 26 Oct 2022 15:43:00 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF207108256 for ; Wed, 26 Oct 2022 12:42:42 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id f23so15202682plr.6 for ; Wed, 26 Oct 2022 12:42:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uFvAy1Yx9bF2vsbUT1HqGJtHQU9f7u8fB33iw92Qf8Q=; b=oKBbVUwj0ewG2ZP2F3fTEFFC5mwv4W+c9kZCqjl7JXd4iDbGJEY0AoQ8UYLEbFN5Ra 0x7RjJ30MNig+oRb1brPsUeEwBwRiuFhggpgiWrCKI86pV0GVPWln+FXhDLy0iIYorOi D2M5OJERgyDjOH1XHcjM7eR7XT3klUoE64Go4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uFvAy1Yx9bF2vsbUT1HqGJtHQU9f7u8fB33iw92Qf8Q=; b=NIELn19pzNK2aJnXCqTArl60az+mRrne8fRkYjP9lFVdqa1Sw42h6oV5JsbZy2f3dB MyuGYodi33OImsoNFuEiWMgWKeTVnO4U2AHcL/d3sqFPiXL0OEwWO4PceOJ+zE3rJ+6y b9TEdBe+6jOCh47p8yjR7fhFKnwG5JUFOAm2bSp+8xuhaMe/h56a4b0J28RXnzqIvqFg wa76j9NpC1qHRVwdYH4AFsUFCro/vLIV9QOtDFNvZyFu/bQGT3Z/tRlf7WDCV2m4G0JC zLU0AfwoMXdS4yZkS1C/8e4W+XIkVPwdXlkog3maHm6F0tc2OKh0qywsksYJVXu6sb16 5Z3Q== X-Gm-Message-State: ACrzQf009WvLbvGmasRht7j/8gkR1Rhrq74//zKReV6/wPdU5cYajk62 HxRF7jFNiQ5rh0aj758nKFq5Tw== X-Received: by 2002:a17:90b:4a02:b0:213:63e7:d0b1 with SMTP id kk2-20020a17090b4a0200b0021363e7d0b1mr2659334pjb.208.1666813362670; Wed, 26 Oct 2022 12:42:42 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:c9e3:74f3:6b2b:135]) by smtp.gmail.com with UTF8SMTPSA id p5-20020a17090ac00500b0020ae09e9724sm1424933pjt.53.2022.10.26.12.42.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 12:42:42 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Guo , linux-mmc@vger.kernel.org, Adrian Hunter , Shawn Lin , Michal Simek , Sascha Hauer , Bjorn Andersson , Thierry Reding , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Jonathan Hunter , Andy Gross , Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Konrad Dybcio , Al Cooper , Fabio Estevam , Florian Fainelli , NXP Linux Team , Haibo Chen , Sowjanya Komatineni , Brian Norris Subject: [PATCH v4 6/7] mmc: sdhci_am654: Fix SDHCI_RESET_ALL for CQHCI Date: Wed, 26 Oct 2022 12:42:08 -0700 Message-Id: <20221026124150.v4.6.I35ca9d6220ba48304438b992a76647ca8e5b126f@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221026194209.3758834-1-briannorris@chromium.org> References: <20221026194209.3758834-1-briannorris@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747780660437164346?= X-GMAIL-MSGID: =?utf-8?q?1747780660437164346?= [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. This patch depends on (and should not compile without) the patch entitled "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Fixes: f545702b74f9 ("mmc: sdhci_am654: Add Support for Command Queuing Engine to J721E") Signed-off-by: Brian Norris Acked-by: Adrian Hunter --- Changes in v4: - Also fix sdhci_am654_ops, sdhci_j721e_8bit_ops - Add dependency notes - Drop bouncing Faiz Abbas address Changes in v3: - Use new SDHCI+CQHCI helper drivers/mmc/host/sdhci_am654.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 8f1023480e12..c2333c7acac9 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -15,6 +15,7 @@ #include #include "cqhci.h" +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" /* CTL_CFG Registers */ @@ -378,7 +379,7 @@ static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); @@ -464,7 +465,7 @@ static struct sdhci_ops sdhci_am654_ops = { .set_clock = sdhci_am654_set_clock, .write_b = sdhci_am654_write_b, .irq = sdhci_am654_cqhci_irq, - .reset = sdhci_reset, + .reset = sdhci_and_cqhci_reset, }; static const struct sdhci_pltfm_data sdhci_am654_pdata = { @@ -494,7 +495,7 @@ static struct sdhci_ops sdhci_j721e_8bit_ops = { .set_clock = sdhci_am654_set_clock, .write_b = sdhci_am654_write_b, .irq = sdhci_am654_cqhci_irq, - .reset = sdhci_reset, + .reset = sdhci_and_cqhci_reset, }; static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { From patchwork Wed Oct 26 19:42:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 11424 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp454473wru; Wed, 26 Oct 2022 12:47:43 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4tdebONwWgQo6/Iz4YWg3u/gQToRuw/cUIlB7xp1wkbtTHxotdPAoqbljRILlzLXVPtYIC X-Received: by 2002:a17:90b:1982:b0:212:fe7f:4a49 with SMTP id mv2-20020a17090b198200b00212fe7f4a49mr6017222pjb.156.1666813663322; Wed, 26 Oct 2022 12:47:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666813663; cv=none; d=google.com; s=arc-20160816; b=g2TwDhlrumkz2i1O/YYrNRGusGgbhgju3KowhJ4p4swvsOdEgXyGXgwi/D99KAd45r 7ERPk6L0Xl1Nf0/IR8SWECG90g8HGVo2ICRzaRtYhuoNRgAkNtxLPUWYlbEodTly0xEB zMavqIW7wVKG5+rdi66dwX3zc5+tJBANxQ96XBmrPHWnBNRhjv29YFjZIlANcrMj9KcB c2MW/Sbnf5DA2bLgx69/OCi8tJO3usqzEPpolXlBsG2REqnLiPtbJPQXcNQoaa16eWy1 5HeVKldaxc0hXM2rlr10q17M4HLHLkNEYo45xHT3muiFo4UmRRcLpWyVLseDZsPkHUe5 jiMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Oi/ns2/+lR1+ddU/1Ugq5i2XZ8iCGI8EoPh2M4YhQ8o=; b=WKtdAYvC6PnNdGBtWSRYTiGzR6fgbhxN9Dsr7QuhuusQlmIohVwteLK+yXJgATXk45 n0NdNOh/jbsO+YZFpq2Rb2RvArNwCMY4XXGxxQGIdivqAm/wX0hylzXlyoZrVdoRpe+l 7bBAWP6Bas63ojmI7VWUc9O0PBE4fVD1TK/JtucQL6yHk6MuGOszXVxQ0Hnl3//ty8x2 /i6r+FAqZFmKq2eD6o0aLytGkQAtTJGaah5xvgsofZQeTuFaitG9ZAHhKrD+0IVJt4aU MZOD2Eqt7+Q9ieWDFA14A+KDkVpyB3KVuljz2toPb/JdqerQeYuYWmU0GPWiJY6uUcl8 6ftw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=ne3Bjzj3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b125-20020a636783000000b0044ed36e4c57si8287428pgc.217.2022.10.26.12.47.30; Wed, 26 Oct 2022 12:47:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=ne3Bjzj3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235098AbiJZToA (ORCPT + 99 others); Wed, 26 Oct 2022 15:44:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233628AbiJZTnM (ORCPT ); Wed, 26 Oct 2022 15:43:12 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC654D03A6 for ; Wed, 26 Oct 2022 12:42:45 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id j12so15198591plj.5 for ; Wed, 26 Oct 2022 12:42:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Oi/ns2/+lR1+ddU/1Ugq5i2XZ8iCGI8EoPh2M4YhQ8o=; b=ne3Bjzj3/Xp33Sha2f/cKqGXdoH6Vyr5pOV6EuuqvioSpyWEaWuiHEeTUPPxMmITZy AjpY81WAkjUG4NkFO4CzRkknSFFYVH/HDZGTHQ2cTgwST8YhakPg/9CIkJjqjV7sWNZ6 sRvl6FHFKEQGE626YqbWeD7+B8j5Ajygbqwxg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Oi/ns2/+lR1+ddU/1Ugq5i2XZ8iCGI8EoPh2M4YhQ8o=; b=3rXTmFwUjS87scbJhkzhUxR4xxtukSlGtqldLIA2Y1pm1ScWHYnP3FGrQgjpTVjtNT bq6G8bUNejlJ11PSOgA6PzaVCf4sN8UsYQ0oGXv2+eQzxtrpVIO6GtwlH0B7XtRZyLNr nUciPGkH5TrDn2fiYktXDPqoSC+cMPQge1j4rrl/daokIRXzuk+T5Dp1iL6yuc1/r9Yc WkyBK3QLhRMmfMN5IX1sX9nTP2Gkx4Gf85QiZv+/R5IgHqZxlmI5FlHZ2Bvu+kDYlR+w q4iaB0e3Gjt+FcLt7yqTVfJUPsYWz1ADaOHqSn/RvOmBVZ5AxqEB5bZ0xgbcU0eHVPta DvfQ== X-Gm-Message-State: ACrzQf1yg5UozlDbzwrz74tz4dxEmT3z7F2icgYCWJAV4m5TTAkL5OYH 7Wcv7gUyBWPOetZ0Nt9ygxE4eQ== X-Received: by 2002:a17:902:da84:b0:186:dd94:bbed with SMTP id j4-20020a170902da8400b00186dd94bbedmr4430426plx.20.1666813365417; Wed, 26 Oct 2022 12:42:45 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:c9e3:74f3:6b2b:135]) by smtp.gmail.com with UTF8SMTPSA id b3-20020a170903228300b00186b55e3cd6sm3293223plh.133.2022.10.26.12.42.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 12:42:45 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Guo , linux-mmc@vger.kernel.org, Adrian Hunter , Shawn Lin , Michal Simek , Sascha Hauer , Bjorn Andersson , Thierry Reding , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Jonathan Hunter , Andy Gross , Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Konrad Dybcio , Al Cooper , Fabio Estevam , Florian Fainelli , NXP Linux Team , Haibo Chen , Sowjanya Komatineni , Brian Norris Subject: [PATCH v4 7/7] mmc: sdhci-*: Convert drivers to new sdhci_and_cqhci_reset() Date: Wed, 26 Oct 2022 12:42:09 -0700 Message-Id: <20221026124150.v4.7.Ia91f031f5f770af7bd2ff3e28b398f277606d970@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221026194209.3758834-1-briannorris@chromium.org> References: <20221026194209.3758834-1-briannorris@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747780803999002966?= X-GMAIL-MSGID: =?utf-8?q?1747780803999002966?= An earlier patch ("mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI") does these operations for us. I keep these as a separate patch, since the earlier patch is a prerequisite to some important bugfixes that need to be backported via linux-stable. Signed-off-by: Brian Norris Acked-by: Adrian Hunter --- Changes in v4: - Add Adrian's Ack Changes in v3: - Rewrite to new helper, patch sdhci-msm too Changes in v2: - Factor out ->cqe_private helpers drivers/mmc/host/sdhci-msm.c | 10 ++-------- drivers/mmc/host/sdhci-pci-core.c | 11 ++--------- drivers/mmc/host/sdhci-pci-gli.c | 11 ++--------- 3 files changed, 6 insertions(+), 26 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 3a091a387ecb..03f76384ab3f 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -19,6 +19,7 @@ #include #include +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "cqhci.h" @@ -2304,13 +2305,6 @@ static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host) pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps); } -static void sdhci_msm_reset(struct sdhci_host *host, u8 mask) -{ - if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) - cqhci_deactivate(host->mmc); - sdhci_reset(host, mask); -} - static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host) { int ret; @@ -2450,7 +2444,7 @@ static const struct of_device_id sdhci_msm_dt_match[] = { MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); static const struct sdhci_ops sdhci_msm_ops = { - .reset = sdhci_msm_reset, + .reset = sdhci_and_cqhci_reset, .set_clock = sdhci_msm_set_clock, .get_min_clock = sdhci_msm_get_min_clock, .get_max_clock = sdhci_msm_get_max_clock, diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index 169b84761041..cc039155b5c7 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -38,6 +38,7 @@ #include "cqhci.h" #include "sdhci.h" +#include "sdhci-cqhci.h" #include "sdhci-pci.h" static void sdhci_pci_hw_reset(struct sdhci_host *host); @@ -234,14 +235,6 @@ static void sdhci_pci_dumpregs(struct mmc_host *mmc) sdhci_dumpregs(mmc_priv(mmc)); } -static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) -{ - if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && - host->mmc->cqe_private) - cqhci_deactivate(host->mmc); - sdhci_reset(host, mask); -} - /*****************************************************************************\ * * * Hardware specific quirk handling * @@ -703,7 +696,7 @@ static const struct sdhci_ops sdhci_intel_glk_ops = { .set_power = sdhci_intel_set_power, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_cqhci_reset, + .reset = sdhci_and_cqhci_reset, .set_uhs_signaling = sdhci_intel_set_uhs_signaling, .hw_reset = sdhci_pci_hw_reset, .irq = sdhci_cqhci_irq, diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index 4d509f656188..633a8ee8f8c5 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -15,6 +15,7 @@ #include #include #include "sdhci.h" +#include "sdhci-cqhci.h" #include "sdhci-pci.h" #include "cqhci.h" @@ -922,14 +923,6 @@ static int gl9763e_add_host(struct sdhci_pci_slot *slot) return ret; } -static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask) -{ - if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && - host->mmc->cqe_private) - cqhci_deactivate(host->mmc); - sdhci_reset(host, mask); -} - static void gli_set_gl9763e(struct sdhci_pci_slot *slot) { struct pci_dev *pdev = slot->chip->pdev; @@ -1136,7 +1129,7 @@ static const struct sdhci_ops sdhci_gl9763e_ops = { .set_clock = sdhci_set_clock, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_gl9763e_reset, + .reset = sdhci_and_cqhci_reset, .set_uhs_signaling = sdhci_set_gl9763e_signaling, .voltage_switch = sdhci_gli_voltage_switch, .irq = sdhci_gl9763e_cqhci_irq,