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[8.43.85.97]) by mx.google.com with ESMTPS id de42-20020a1709069bea00b009745c724e4esi5731518ejc.304.2023.06.06.00.49.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 00:49:29 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@oss.cipunited.com header.s=feishu2303200042 header.b=dn9ApG3S; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BD74A3857712 for ; Tue, 6 Jun 2023 07:49:27 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from s01.bc.larksuite.com (s01.bc.larksuite.com [209.127.230.19]) by sourceware.org (Postfix) with UTF8SMTPS id 56C353858416 for ; Tue, 6 Jun 2023 07:49:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 56C353858416 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1686037754; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=Zkz/VSZGaS+/NX3qeUS5vvR0Izkn5RIv2/i4wiqphgQ=; b=dn9ApG3S1sXmhgMEtGZJXyq4Y3th+/K/SvuIt4Un5ilZWhcARe8J1UaqMDnxSwJJhS80qX F46/YxHG22LZR8jYGAswJpdgfW5brm1ZdLCkQ5Amfuez9Kl12uqHbaJXmf3fO3MOyG3HiM PaCMjSJvHfPIl35olpQb26uS/OKSOGoth5MK92SRtjdU3ZB5rQbRqgNqzvEJAhHV6S4wpz 21k4tMsGMk+DkB3GhUBsXXVsRpvacT8rM1U6khU9uSvJZjdOnZaJ+xTDOe4ZcQFSgX+Mzw y19NhT+X5vsLnDusLnxF0i9SPVNNhZlvsUsGOoYKtaK51evcarirl1C5xL2yVw== To: Subject: [PATCH v2] Add GINV(+VIRT) ASE for MIPSr6 From: "Tsing" Date: Tue, 06 Jun 2023 15:49:13 +0800 Message-Id: <20230606074856.3463253-1-lei.wang@oss.cipunited.com> Mime-Version: 1.0 X-Lms-Return-Path: X-Mailer: git-send-email 2.40.1 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, HTML_MESSAGE, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767938740613880159?= X-GMAIL-MSGID: =?utf-8?q?1767938740613880159?= This patch adds the VZ extension to MIPSr6 as part of the GINV ASE. gas/ * config/tc-mips.c (mips_ases): Add microMIPS ASE. (mips_set_ase): Set combination VZ+GINV ASE flag. gas/testsuite/ * gas/mips/ginv.s: Add test case. * gas/mips/ginv-virt.d: New test. * gas/mips/mips.exp: Run the new tests. include/ * opcode/mips.h: Add note for micromips +\ format descriptor. (ASE_GINV_VIRT): New macro. opcodes/ *mips-dis.c (mips_calculate_combination_ases): Set ASE_GINV_VIRT. *mips-opc.c (GINVVZ): New macro. (mips_opcode): Add instruction GINVGT.Description of the `GINVGT` instruction on page 176 of the MIPS64 I6500 System Instruction Guide. https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MIPS_Warrior_I6500_ProgrammerGuide_MD01179_P_1.00.pdf --- gas/config/tc-mips.c | 11 ++++++++++- gas/testsuite/gas/mips/ginv-virt.d | 22 ++++++++++++++++++++++ gas/testsuite/gas/mips/ginv.s | 5 +++++ gas/testsuite/gas/mips/mips.exp | 1 + include/opcode/mips.h | 6 ++++++ opcodes/mips-dis.c | 2 ++ opcodes/mips-opc.c | 2 ++ 7 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/mips/ginv-virt.d diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 077993cf..de8ea1dd 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -2227,7 +2227,7 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, /* Clear combination ASE flags, which need to be recalculated based on updated regular ASE settings. */ - opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6); + opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6 | ASE_GINV_VIRT); if (enabled_p) opts->ase |= ase->flags; @@ -2255,6 +2255,15 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, mask |= ASE_EVA_R6; } + /* The Virtualization ASE has Global INValidate (GINV) instructions + which are only valid when both ASEs are enabled. This sets the + ASE_GINV_VIRT flag when both ASEs are present. */ + if ((opts->ase & (ASE_GINV | ASE_VIRT)) == (ASE_GINV | ASE_VIRT)) + { + opts->ase |= ASE_GINV_VIRT; + mask |= ASE_GINV_VIRT; + } + return mask; } diff --git a/gas/testsuite/gas/mips/ginv-virt.d b/gas/testsuite/gas/mips/ginv-virt.d new file mode 100644 index 00000000..92e06681 --- /dev/null +++ b/gas/testsuite/gas/mips/ginv-virt.d @@ -0,0 +1,22 @@ +#objdump: -pdr --prefix-addresses --show-raw-insn +#name: MIPS GINV Virtualization +#as: --defsym VX=1 -mginv -mvirt -32 +#source: ginv.s + +# Test GINV+VZ instructions. + +.*: +file format .*mips.* +#... +ASEs: +#... + VZ ASE + GINV ASE +#... + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7c40003d ginvi v0 +[0-9a-f]+ <[^>]*> 7c6000bd ginvt v1,0x0 +[0-9a-f]+ <[^>]*> 7c8001bd ginvt a0,0x1 +[0-9a-f]+ <[^>]*> 7c8002fd ginvgt a0,0x2 +[0-9a-f]+ <[^>]*> 7ca003fd ginvgt a1,0x3 + \.\.\. diff --git a/gas/testsuite/gas/mips/ginv.s b/gas/testsuite/gas/mips/ginv.s index 63cfb150..80159948 100644 --- a/gas/testsuite/gas/mips/ginv.s +++ b/gas/testsuite/gas/mips/ginv.s @@ -4,6 +4,11 @@ test: ginvt $3,0 ginvt $4,1 + .ifdef VX + ginvgt $4,2 + ginvgt $5,3 + .endif + # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... .align 2 .space 8 diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index fafed2dc..e9617154 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -2131,6 +2131,7 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test_arches "ginv" [mips_arch_list_matching mips32r6] run_dump_test_arches "ginv-err" [mips_arch_list_matching mips32r6] + run_dump_test_arches "ginv-virt" [mips_arch_list_matching mips32r6] run_dump_test_arches "llpscp-32" [mips_arch_list_matching mips32r6] run_dump_test_arch "llpscp-64" "" mips64r6 diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 75d3fc25..3d6447c4 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1316,6 +1316,9 @@ static const unsigned int mips_isa_table[] = { /* The Enhanced VA Scheme (EVA) extension has instructions which are only valid for the R6 ISA. */ #define ASE_EVA_R6 0x02000000 +/* The Virtualization ASE has Global INValidate (GINV) + instructions which are only valid when both ASEs are enabled. */ +#define ASE_GINV_VIRT 0x08000000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -2351,6 +2354,9 @@ extern const int bfd_mips16_num_opcodes; "+*" 5-bit register vector element index at bit 16 "+|" 8-bit mask at bit 16 + GINV ASE usage: + "+\" 2-bit Global TLB invalidate type at bit 8 + Other: "()" parens surrounding optional value "," separates operands diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 6a513cd8..77b35b60 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -866,6 +866,8 @@ mips_calculate_combination_ases (int opcode_isa, unsigned long opcode_ases) && ((opcode_isa & INSN_ISA_MASK) == ISA_MIPS64R6 || (opcode_isa & INSN_ISA_MASK) == ISA_MIPS32R6)) combination_ases |= ASE_EVA_R6; + if ((opcode_ases & (ASE_GINV | ASE_VIRT)) == (ASE_GINV | ASE_VIRT)) + combination_ases |= ASE_GINV_VIRT; return combination_ases; } diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 2a1a6cbb..7421c6a4 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -412,6 +412,7 @@ decode_mips_operand (const char *p) /* Global INValidate (GINV) support. */ #define GINV ASE_GINV +#define GINVVZ ASE_GINV_VIRT /* Loongson MultiMedia extensions Instructions (MMI) support. */ #define LMMI ASE_LOONGSON_MMI @@ -3329,6 +3330,7 @@ const struct mips_opcode mips_builtin_opcodes[] = /* MIPS Global INValidate (GINV) ASE. */ {"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 }, {"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 }, +{"ginvgt", "s,+\\", 0x7c0000fd, 0xfc1ffcff, RD_1, 0, 0, GINVVZ, 0 }, /* Move bc0* after mftr and mttr to avoid opcode collision. */ {"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 },