From patchwork Mon Jun 5 20:20:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 103492 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2942176vqr; Mon, 5 Jun 2023 13:43:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7TEClD9nsew4RXwf4dNNnKQWXerqzUJebVSTx+BHoiRaei28cDXO31iZ/Za92sMTWN2bbT X-Received: by 2002:a17:90a:4f4b:b0:255:70e4:ad25 with SMTP id w11-20020a17090a4f4b00b0025570e4ad25mr5094667pjl.15.1685997816921; Mon, 05 Jun 2023 13:43:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685997816; cv=none; d=google.com; s=arc-20160816; b=RqPuI6P8bAcmy6Tg6+4kVtDgZ9sgG+539qOfRx4Cm4Pigs1BO9iyhbhKHvrk7AXCP3 qAZrlnDzSvk/CEXSZcySgk03IGvm+HVTk3mvVzfdB17AmlzllQrX1k13bDbp309bv8g0 kFKu39bGSk8+yTXYrA1UXWf5dir4PgLfDIrHI5FoEBkmOUlDCERnECZVLnDeEXXEjeqI MxC3ghX3zWyfgdqL0bvM+37u0irplHPVBwdshjS1t2UH0Dw3ErhYpMIlQozzsSuyHdQB sDOphTg80ucftlo/8kTGkFPjItMcxA37T18MOFaFCN6n3wnKnpMJ9i9bOjq8ukaUWu/U N8Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=b17CQCE1ZeraKjrObp7LSmyJHhNj8xLcjCll18YYpVU=; b=cQB3XDJ2xhUx1+F3nB7dy2t3SKOdCOyDQUrc1ewC3aR96fPPvf4OG5GhzMIYmHqyn+ whY+88Ux813lccO2qln2R10vA2iswstlCferaFfXLWQkOLjf5hTq8zclNUySXy6vPkT7 oVMP1nOqhpvTvDkA4MS+ATOv7ohb9Iajpo6r8wNshj9D+R76xlI+stBe9dPM0X3GJo/d f076Hyfqqbou77dmnmDhBRz1HoOQ1kXexHQn6ggXBDi/wynAzCK36aLxNKxhj9PtFSqL 4iLBawPe/UHlGFS7RM5sjEGLCiWA6EWayhDS4cowzS/15WsHqkn5Y6AuweZDWqSACIM6 bbaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=aBVGpgbL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v8-20020a17090a898800b002507aba141asi6062524pjn.171.2023.06.05.13.43.23; Mon, 05 Jun 2023 13:43:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=aBVGpgbL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233137AbjFEUVO (ORCPT + 99 others); Mon, 5 Jun 2023 16:21:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233175AbjFEUUz (ORCPT ); Mon, 5 Jun 2023 16:20:55 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75B6C131; Mon, 5 Jun 2023 13:20:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685996452; x=1717532452; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=8NoLDzTaDtX8oRYZuAAFVVjzeCX1nMQzM5M2Hww1+yw=; b=aBVGpgbLAbi9kRKnPXgEC5f+wIpS7twoSt8pXtdCbemZ1qMFqT+cll3T T4aDjlS5Rb+kEjxnMfL7K4gC26annif8PK6ma+zoiaBbe8mY2XZMikHIw muBl6YnRE6hP5Tt6C+A2UQvyFrCT+K3WRwffcp4gAzQ560tqbRqfipfBQ Lszm95QcMdhzuPIDqjWils/JgWlTIaYKRDvB0NHv1eHiyBRMnxYk8yhsh J+AVnGNWpJkTgQgcu8sABCl0X96pLyJs2leCrijKPLHg61P6tqTURno9C d9Elme6LFMO5pCo70wFrVPiiS5xInwexDB4w2hP1BG/LXNGw5VwB6cuQN A==; X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="336093124" X-IronPort-AV: E=Sophos;i="6.00,218,1681196400"; d="scan'208";a="336093124" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 13:20:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="832934188" X-IronPort-AV: E=Sophos;i="6.00,218,1681196400"; d="scan'208";a="832934188" Received: from kmsalzbe-mobl1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.209.52.9]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 13:20:50 -0700 From: Vishal Verma Date: Mon, 05 Jun 2023 14:20:22 -0600 Subject: [PATCH v2 1/4] cxl: add a firmware update mechanism using the sysfs firmware loader MIME-Version: 1.0 Message-Id: <20230602-vv-fw_update-v2-1-e9e5cd5adb44@intel.com> References: <20230602-vv-fw_update-v2-0-e9e5cd5adb44@intel.com> In-Reply-To: <20230602-vv-fw_update-v2-0-e9e5cd5adb44@intel.com> To: Alison Schofield , Ira Weiny , Dave Jiang , Ben Widawsky , Dan Williams Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Davidlohr Bueso , Jonathan Cameron , Russ Weight , Vishal Verma X-Mailer: b4 0.13-dev-02a79 X-Developer-Signature: v=1; a=openpgp-sha256; l=17271; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=8NoLDzTaDtX8oRYZuAAFVVjzeCX1nMQzM5M2Hww1+yw=; b=owGbwMvMwCXGf25diOft7jLG02pJDCl1zgtnZix/f3vqrN5Vbc18Py8sit+pzPXpgc/FA/GNz 5XPO6n96ChlYRDjYpAVU2T5u+cj4zG57fk8gQmOMHNYmUCGMHBxCsBEFMsYGR7t5M/slnOLfFq8 wNT93xUeNb9Z+l+yd79fKNixd/Jex2kMf6W1/bWzvqh5XGTiYz7MfO2PP6O1W4WYxA8xg+Len+z d3AA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767896846915502234?= X-GMAIL-MSGID: =?utf-8?q?1767896846915502234?= The sysfs based firmware loader mechanism was created to easily allow userspace to upload firmware images to FPGA cards. This also happens to be pretty suitable to create a user-initiated but kernel-controlled firmware update mechanism for CXL devices, using the CXL specified mailbox commands. Since firmware update commands can be long-running, and can be processed in the background by the endpoint device, it is desirable to have the ability to chunk the firmware transfer down to smaller pieces, so that one operation does not monopolize the mailbox, locking out any other long running background commands entirely - e.g. security commands like 'sanitize' or poison scanning operations. The firmware loader mechanism allows a natural way to perform this chunking, as after each mailbox command, that is restricted to the maximum mailbox payload size, the cxl memdev driver relinquishes control back to the fw_loader system and awaits the next chunk of data to transfer. This opens opportunities for other background commands to access the mailbox and send their own slices of background commands. Add the necessary helpers and state tracking to be able to perform the 'Get FW Info', 'Transfer FW', and 'Activate FW' mailbox commands as described in the CXL spec. Wire these up to the firmware loader callbacks, and register with that system to create the memX/firmware/ sysfs ABI. Cc: Davidlohr Bueso Cc: Jonathan Cameron Cc: Russ Weight Cc: Alison Schofield Cc: Ira Weiny Cc: Dave Jiang Cc: Ben Widawsky Cc: Dan Williams Signed-off-by: Vishal Verma --- drivers/cxl/cxlmem.h | 85 +++++++++ drivers/cxl/core/memdev.c | 309 +++++++++++++++++++++++++++++++- drivers/cxl/pci.c | 4 + Documentation/ABI/testing/sysfs-bus-cxl | 11 ++ drivers/cxl/Kconfig | 1 + 5 files changed, 409 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 1d8e81c87c6a..835b544812bc 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -49,6 +49,7 @@ struct cxl_memdev { struct work_struct detach_work; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_nvdimm *cxl_nvd; + const char *fw_name; int id; int depth; }; @@ -83,6 +84,7 @@ static inline bool is_cxl_endpoint(struct cxl_port *port) } struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); +int cxl_memdev_setup_fw_upload(struct cxl_dev_state *cxlds); int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, resource_size_t base, resource_size_t len, resource_size_t skipped); @@ -260,6 +262,84 @@ struct cxl_poison_state { struct mutex lock; /* Protect reads of poison list */ }; +/* + * Get FW Info + * CXL rev 3.0 section 8.2.9.3.1; Table 8-56 + */ +struct cxl_mbox_get_fw_info { + u8 num_slots; + u8 slot_info; + u8 activation_cap; + u8 reserved[13]; + char slot_1_revision[16]; + char slot_2_revision[16]; + char slot_3_revision[16]; + char slot_4_revision[16]; +} __packed; + +#define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0) +#define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3) +#define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3 +#define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0) + +/* + * Transfer FW Input Payload + * CXL rev 3.0 section 8.2.9.3.2; Table 8-57 + */ +struct cxl_mbox_transfer_fw { + u8 action; + u8 slot; + u8 reserved[2]; + __le32 offset; + u8 reserved2[0x78]; + u8 data[]; +} __packed; + +#define CXL_FW_TRANSFER_ACTION_FULL 0x0 +#define CXL_FW_TRANSFER_ACTION_INITIATE 0x1 +#define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2 +#define CXL_FW_TRANSFER_ACTION_END 0x3 +#define CXL_FW_TRANSFER_ACTION_ABORT 0x4 + +/* + * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages + * and for each part transferred in a Transfer FW command. + */ +#define CXL_FW_TRANSFER_ALIGNMENT 128 + +/* + * Activate FW Input Payload + * CXL rev 3.0 section 8.2.9.3.3; Table 8-58 + */ +struct cxl_mbox_activate_fw { + u8 action; + u8 slot; +} __packed; + +#define CXL_FW_ACTIVATE_ONLINE 0x0 +#define CXL_FW_ACTIVATE_OFFLINE 0x1 + +/* FW state bits */ +#define CXL_FW_STATE_BITS 32 +#define CXL_FW_CANCEL BIT(0) + +/** + * struct cxl_fw_state - Firmware upload / activation state + * + * @state: fw_uploader state bitmask + * @oneshot: whether the fw upload fits in a single transfer + * @num_slots: Number of FW slots available + * @cur_slot: Slot number currently active + * @next_slot: Slot number for the new firmware + */ +struct cxl_fw_state { + DECLARE_BITMAP(state, CXL_FW_STATE_BITS); + bool oneshot; + int num_slots; + int cur_slot; + int next_slot; +}; + /** * struct cxl_dev_state - The driver device state * @@ -297,6 +377,8 @@ struct cxl_poison_state { * @serial: PCIe Device Serial Number * @event: event log driver state * @poison: poison driver state info + * @fw: firmware upload / activation state + * @fwl: handle for registration with the firmware loader system * @mbox_send: @dev specific transport for transmitting mailbox commands * * See section 8.2.9.5.2 Capacity Configuration and Label Storage for @@ -336,6 +418,8 @@ struct cxl_dev_state { struct cxl_event_state event; struct cxl_poison_state poison; + struct cxl_fw_state fw; + struct fw_upload *fwl; struct rcuwait mbox_wait; int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); @@ -349,6 +433,7 @@ enum cxl_opcode { CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, CXL_MBOX_OP_GET_FW_INFO = 0x0200, + CXL_MBOX_OP_TRANSFER_FW = 0x0201, CXL_MBOX_OP_ACTIVATE_FW = 0x0202, CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 057a43267290..f45c8b174d9d 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2020 Intel Corporation. */ +#include #include #include #include @@ -441,6 +442,7 @@ static void cxl_memdev_unregister(void *_cxlmd) struct cxl_memdev *cxlmd = _cxlmd; struct device *dev = &cxlmd->dev; + kfree(cxlmd->fw_name); cxl_memdev_shutdown(dev); cdev_device_del(&cxlmd->cdev, dev); put_device(dev); @@ -542,6 +544,311 @@ static int cxl_memdev_release_file(struct inode *inode, struct file *file) return 0; } +/** + * cxl_mem_get_fw_info - Get Firmware info + * @cxlds: The device data for the operation + * + * Retrieve firmware info for the device specified. + * + * Return: 0 if no error: or the result of the mailbox command. + * + * See CXL-3.0 8.2.9.3.1 Get FW Info + */ +static int cxl_mem_get_fw_info(struct cxl_dev_state *cxlds) +{ + struct cxl_mbox_get_fw_info info; + struct cxl_mbox_cmd mbox_cmd; + int rc; + + mbox_cmd = (struct cxl_mbox_cmd) { + .opcode = CXL_MBOX_OP_GET_FW_INFO, + .size_out = sizeof(info), + .payload_out = &info, + }; + + rc = cxl_internal_send_cmd(cxlds, &mbox_cmd); + if (rc < 0) + return rc; + + cxlds->fw.num_slots = info.num_slots; + cxlds->fw.cur_slot = FIELD_GET(CXL_FW_INFO_SLOT_INFO_CUR_MASK, + info.slot_info); + + return 0; +} + +/** + * cxl_mem_activate_fw - Activate Firmware + * @cxlds: The device data for the operation + * @slot: slot number to activate + * + * Activate firmware in a given slot for the device specified. + * + * Return: 0 if no error: or the result of the mailbox command. + * + * See CXL-3.0 8.2.9.3.3 Activate FW + */ +static int cxl_mem_activate_fw(struct cxl_dev_state *cxlds, int slot) +{ + struct cxl_mbox_activate_fw activate; + struct cxl_mbox_cmd mbox_cmd; + + if (slot == 0 || slot > cxlds->fw.num_slots) + return -EINVAL; + + mbox_cmd = (struct cxl_mbox_cmd) { + .opcode = CXL_MBOX_OP_ACTIVATE_FW, + .size_in = sizeof(activate), + .payload_in = &activate, + }; + + /* Only offline activation supported for now */ + activate.action = CXL_FW_ACTIVATE_OFFLINE; + activate.slot = slot; + + return cxl_internal_send_cmd(cxlds, &mbox_cmd); +} + +/** + * cxl_mem_abort_fw_xfer - Abort an in-progress FW transfer + * @cxlds: The device data for the operation + * + * Abort an in-progress firmware transfer for the device specified. + * + * Return: 0 if no error: or the result of the mailbox command. + * + * See CXL-3.0 8.2.9.3.2 Transfer FW + */ +static int cxl_mem_abort_fw_xfer(struct cxl_dev_state *cxlds) +{ + struct cxl_mbox_transfer_fw *transfer; + struct cxl_mbox_cmd mbox_cmd; + int rc; + + transfer = kzalloc(struct_size(transfer, data, 0), GFP_KERNEL); + if (!transfer) + return -ENOMEM; + + /* Set a 1s poll interval and a total wait time of 30s */ + mbox_cmd = (struct cxl_mbox_cmd) { + .opcode = CXL_MBOX_OP_TRANSFER_FW, + .size_in = sizeof(*transfer), + .payload_in = transfer, + .poll_interval_ms = 1000, + .poll_count = 30, + }; + + transfer->action = CXL_FW_TRANSFER_ACTION_ABORT; + + rc = cxl_internal_send_cmd(cxlds, &mbox_cmd); + kfree(transfer); + return rc; +} + +static void cxl_fw_cleanup(struct fw_upload *fwl) +{ + struct cxl_dev_state *cxlds = fwl->dd_handle; + + cxlds->fw.next_slot = 0; +} + +static int cxl_fw_do_cancel(struct fw_upload *fwl) +{ + struct cxl_dev_state *cxlds = fwl->dd_handle; + struct cxl_memdev *cxlmd = cxlds->cxlmd; + int rc; + + rc = cxl_mem_abort_fw_xfer(cxlds); + if (rc < 0) + dev_err(&cxlmd->dev, "Error aborting FW transfer: %d\n", rc); + + return FW_UPLOAD_ERR_CANCELED; +} + +static enum fw_upload_err cxl_fw_prepare(struct fw_upload *fwl, const u8 *data, + u32 size) +{ + struct cxl_dev_state *cxlds = fwl->dd_handle; + struct cxl_mbox_transfer_fw *transfer; + + if (!size) + return FW_UPLOAD_ERR_INVALID_SIZE; + + cxlds->fw.oneshot = struct_size(transfer, data, size) < + cxlds->payload_size; + + if (cxl_mem_get_fw_info(cxlds)) + return FW_UPLOAD_ERR_HW_ERROR; + + /* + * So far no state has been changed, hence no other cleanup is + * necessary. Simply return the cancelled status. + */ + if (test_and_clear_bit(CXL_FW_CANCEL, cxlds->fw.state)) + return FW_UPLOAD_ERR_CANCELED; + + return FW_UPLOAD_ERR_NONE; +} + +static enum fw_upload_err cxl_fw_write(struct fw_upload *fwl, const u8 *data, + u32 offset, u32 size, u32 *written) +{ + struct cxl_dev_state *cxlds = fwl->dd_handle; + struct cxl_memdev *cxlmd = cxlds->cxlmd; + struct cxl_mbox_transfer_fw *transfer; + struct cxl_mbox_cmd mbox_cmd; + u32 cur_size, remaining; + size_t size_in; + int rc; + + *written = 0; + + /* Offset has to be aligned to 128B (CXL-3.0 8.2.9.3.2 Table 8-57) */ + if (!IS_ALIGNED(offset, CXL_FW_TRANSFER_ALIGNMENT)) { + dev_err(&cxlmd->dev, + "misaligned offset for FW transfer slice (%u)\n", + offset); + return FW_UPLOAD_ERR_RW_ERROR; + } + + /* Pick transfer size based on cxlds->payload_size */ + cur_size = min_t(size_t, size, cxlds->payload_size - sizeof(*transfer)); + remaining = size - cur_size; + size_in = struct_size(transfer, data, cur_size); + + if (test_and_clear_bit(CXL_FW_CANCEL, cxlds->fw.state)) + return cxl_fw_do_cancel(fwl); + + /* + * Slot numbers are 1-indexed + * cur_slot is the 0-indexed next_slot (i.e. 'cur_slot - 1 + 1') + * Check for rollover using modulo, and 1-index it by adding 1 + */ + cxlds->fw.next_slot = (cxlds->fw.cur_slot % cxlds->fw.num_slots) + 1; + + /* Do the transfer via mailbox cmd */ + transfer = kzalloc(size_in, GFP_KERNEL); + if (!transfer) + return FW_UPLOAD_ERR_RW_ERROR; + + transfer->offset = cpu_to_le32(offset / CXL_FW_TRANSFER_ALIGNMENT); + memcpy(transfer->data, data + offset, cur_size); + if (cxlds->fw.oneshot) { + transfer->action = CXL_FW_TRANSFER_ACTION_FULL; + transfer->slot = cxlds->fw.next_slot; + } else { + if (offset == 0) { + transfer->action = CXL_FW_TRANSFER_ACTION_INITIATE; + } else if (remaining == 0) { + transfer->action = CXL_FW_TRANSFER_ACTION_END; + transfer->slot = cxlds->fw.next_slot; + } else { + transfer->action = CXL_FW_TRANSFER_ACTION_CONTINUE; + } + } + + mbox_cmd = (struct cxl_mbox_cmd) { + .opcode = CXL_MBOX_OP_TRANSFER_FW, + .size_in = size_in, + .payload_in = transfer, + .poll_interval_ms = 1000, + .poll_count = 30, + }; + + rc = cxl_internal_send_cmd(cxlds, &mbox_cmd); + if (rc < 0) { + kfree(transfer); + rc = FW_UPLOAD_ERR_RW_ERROR; + goto out_free; + } + + *written = cur_size; + + /* Activate FW if oneshot or if the last slice was written */ + if (cxlds->fw.oneshot || remaining == 0) { + dev_dbg(&cxlmd->dev, "Activating firmware slot: %d\n", + cxlds->fw.next_slot); + rc = cxl_mem_activate_fw(cxlds, cxlds->fw.next_slot); + if (rc < 0) { + dev_err(&cxlmd->dev, "Error activating firmware: %d\n", + rc); + rc = FW_UPLOAD_ERR_HW_ERROR; + goto out_free; + } + } + + rc = FW_UPLOAD_ERR_NONE; + +out_free: + kfree(transfer); + return rc; +} + +static enum fw_upload_err cxl_fw_poll_complete(struct fw_upload *fwl) +{ + struct cxl_dev_state *cxlds = fwl->dd_handle; + + /* + * cxl_internal_send_cmd() handles background operations synchronously. + * No need to wait for completions here - any errors would've been + * reported and handled during the ->write() call(s). + * Just check if a cancel request was received, and return success. + */ + if (test_and_clear_bit(CXL_FW_CANCEL, cxlds->fw.state)) + return cxl_fw_do_cancel(fwl); + + return FW_UPLOAD_ERR_NONE; +} + +static void cxl_fw_cancel(struct fw_upload *fwl) +{ + struct cxl_dev_state *cxlds = fwl->dd_handle; + + set_bit(CXL_FW_CANCEL, cxlds->fw.state); +} + +static const struct fw_upload_ops cxl_memdev_fw_ops = { + .prepare = cxl_fw_prepare, + .write = cxl_fw_write, + .poll_complete = cxl_fw_poll_complete, + .cancel = cxl_fw_cancel, + .cleanup = cxl_fw_cleanup, +}; + +static void devm_cxl_remove_fw_upload(void *fwl) +{ + firmware_upload_unregister(fwl); +} + +int cxl_memdev_setup_fw_upload(struct cxl_dev_state *cxlds) +{ + struct cxl_memdev *cxlmd = cxlds->cxlmd; + struct fw_upload *fwl; + int rc; + + if (!test_bit(CXL_MEM_COMMAND_ID_GET_FW_INFO, cxlds->enabled_cmds)) + return 0; + + fwl = firmware_upload_register(THIS_MODULE, &cxlmd->dev, + dev_name(&cxlmd->dev), + &cxl_memdev_fw_ops, cxlds); + if (IS_ERR(fwl)) { + dev_err(&cxlmd->dev, "Failed to register firmware loader\n"); + return PTR_ERR(fwl); + } + + cxlds->fwl = fwl; + rc = devm_add_action_or_reset(cxlds->dev, devm_cxl_remove_fw_upload, + cxlds->fwl); + if (rc) + dev_err(&cxlmd->dev, + "Failed to add firmware loader remove action: %d\n", + rc); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(cxl_memdev_setup_fw_upload, CXL); + static const struct file_operations cxl_memdev_fops = { .owner = THIS_MODULE, .unlocked_ioctl = cxl_memdev_ioctl, @@ -581,7 +888,7 @@ struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds) rc = devm_add_action_or_reset(cxlds->dev, cxl_memdev_unregister, cxlmd); if (rc) - return ERR_PTR(rc); + goto err; return cxlmd; err: diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index a78e40e6d0e0..ef0b4821b312 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -842,6 +842,10 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); + rc = cxl_memdev_setup_fw_upload(cxlds); + if (rc) + return rc; + rc = cxl_event_config(host_bridge, cxlds); if (rc) return rc; diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 48ac0d911801..06a7718d3fc3 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -58,6 +58,17 @@ Description: affinity for this device. +What: /sys/bus/cxl/devices/memX/firmware/ +Date: April, 2023 +KernelVersion: v6.5 +Contact: linux-cxl@vger.kernel.org +Description: + (RW) Firmware uploader mechanism. The different files under + this directory can be used to upload and activate new + firmware for CXL devices. The interfaces under this are + documented in sysfs-class-firmware. + + What: /sys/bus/cxl/devices/*/devtype Date: June, 2021 KernelVersion: v5.14 diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index ff4e78117b31..80d8e35fa049 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -82,6 +82,7 @@ config CXL_PMEM config CXL_MEM tristate "CXL: Memory Expansion" depends on CXL_PCI + select FW_UPLOAD default CXL_BUS help The CXL.mem protocol allows a device to act as a provider of "System From patchwork Mon Jun 5 20:20:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 103497 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2944820vqr; Mon, 5 Jun 2023 13:50:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7hVVqr7V932AjM2is50CLE8AZi68qS9+XlzXHPLmCxDb2BmKoQHo4UL0br3C6MQzoUntV2 X-Received: by 2002:a17:90a:19d5:b0:259:45d6:f2dd with SMTP id 21-20020a17090a19d500b0025945d6f2ddmr1981856pjj.18.1685998211991; Mon, 05 Jun 2023 13:50:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685998211; cv=none; d=google.com; s=arc-20160816; b=saITiCRmSGbVs2U9qg8lksCgcZ+FQUV31Nh75HmfuG2foW2k4edYOf6Ocd+0mL+gjt f3k4jRhGowEblcStcNtd1donYhvHOTJ9Kl3w3MornFuqBcT7k3eaUQ4nDAulewPmbb8S GmTCcP68APgjzzkC6UzgCdU0VRwYZ9Y0564TZWcdiFnl32vDnBxXgQweFTQFCXbu6e9x w9Ge5Gn5c7PCtMdTqk8hc2wXgqGD/cg9X86h4N373iGE3qg/cF/nGesPHS26oSmuWO3U l8wDzQ2NR0BmUTIVzbVW0kSsVPQYmWMuylm4c7yV1d2FJeCqL/tjQ67BDuYbFr6MHhLX MEaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=GaD/zRMfsJLJpYxL24duWpwpxp3yjWIc5cJ7pD+KM2E=; b=bpBeuGwQV46GjIPyBrQkKPnvgHzCgaJciJZTrl5wwb72A6Z9DVRMCbRNqR9b2g/4pb SZ3fPKqCroANoF2/VE+dMiuMfUsDbt4kVNY6QOGh6gz8xXXQ9qulyXNQS4Ntw+wv30b0 5BT48JZCi2XKjFuaFw1jbfVxNW4LNm3JTmyulseRyQvAwcp2lrk6IyX/QQ6/m68cFNYc WQ71zQbu8UjcUoXAX9GVm4HhriWy1vRWquijSKhWqS76g5rSRUfEre1sJdNysIrKp0+W mDcdKmRA4BHj4ePmg0nUuvdQemhZmByOvwEee63B2MkFtJyzKMmhloYQFvWRZZCRSi+N CyYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nrnvBANs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q2-20020a632a02000000b00543ad7aa643si2298119pgq.815.2023.06.05.13.49.59; Mon, 05 Jun 2023 13:50:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nrnvBANs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232745AbjFEUVK (ORCPT + 99 others); Mon, 5 Jun 2023 16:21:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232412AbjFEUUy (ORCPT ); Mon, 5 Jun 2023 16:20:54 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B29313A; Mon, 5 Jun 2023 13:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685996453; x=1717532453; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=0+TEi7rDE45s/tGzvp1DbBroD1RgvmAgvEMbWroZX+s=; b=nrnvBANsjK084/uhYMgtubk8uf42DbgcZXELctQkctslY1Oh4wEPdaU6 ID+13/XBKjiS3oajJxVBgpZZG8UpNb/AcpDTNYohqHRQ005q6MI/M0R3K fqid/ILR0uwx9AwVkt0fRo4cBI2XfHx9P4MAdVAGSuIuJyZZbZQ5oAAwR sSpEhFeus5kseybLxB87laHFAzJ8MH9FutKBjUeHvaYoL5HNRuRivnbH9 TUE9Nr/WQ3v2WA5VdQNc2k8M0WWx3qyvoJnppLFFfov5tzNlPygkCpFGw z4apRxl/tpoPvjbj6EdwLXcPOlQHbbr8ExcmObkTH39MJ5ky75VlcFGYK A==; X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="336093130" X-IronPort-AV: E=Sophos;i="6.00,218,1681196400"; d="scan'208";a="336093130" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 13:20:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="832934191" X-IronPort-AV: E=Sophos;i="6.00,218,1681196400"; d="scan'208";a="832934191" Received: from kmsalzbe-mobl1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.209.52.9]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 13:20:51 -0700 From: Vishal Verma Date: Mon, 05 Jun 2023 14:20:23 -0600 Subject: [PATCH v2 2/4] tools/testing/cxl: Fix command effects for inject/clear poison MIME-Version: 1.0 Message-Id: <20230602-vv-fw_update-v2-2-e9e5cd5adb44@intel.com> References: <20230602-vv-fw_update-v2-0-e9e5cd5adb44@intel.com> In-Reply-To: <20230602-vv-fw_update-v2-0-e9e5cd5adb44@intel.com> To: Alison Schofield , Ira Weiny , Dave Jiang , Ben Widawsky , Dan Williams Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Davidlohr Bueso , Jonathan Cameron , Russ Weight , Vishal Verma X-Mailer: b4 0.13-dev-02a79 X-Developer-Signature: v=1; a=openpgp-sha256; l=1090; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=0+TEi7rDE45s/tGzvp1DbBroD1RgvmAgvEMbWroZX+s=; b=owGbwMvMwCXGf25diOft7jLG02pJDCl1zovOGG+8ouP57qlyTsGmmQxzpe4nWK74elt7qVf6g U2qFZZCHaUsDGJcDLJiiix/93xkPCa3PZ8nMMERZg4rE8gQBi5OAZiIjRjD/5x9MjlvOp49fayV fWn1m2ne8+zWuUQpac7n2+4v9cfiTjEjw2P5pGXJDawSm68psRaWCMf7nehlesRSzNe3ZPKnCXo BLAA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767897261033537798?= X-GMAIL-MSGID: =?utf-8?q?1767897261033537798?= The CXL spec (3.0, section 8.2.9.8.4) Lists Inject Poison and Clear Poison as having the effects of "Immediate Data Change". Fix this in the mock driver so that the command effect log is populated correctly. Fixes: 371c16101ee8 ("tools/testing/cxl: Mock the Inject Poison mailbox command") Cc: Alison Schofield Cc: Dan Williams Signed-off-by: Vishal Verma Reviewed-by: Alison Schofield Reviewed-by: Jonathan Cameron --- tools/testing/cxl/test/mem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index 34b48027b3de..403cd3608772 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -52,11 +52,11 @@ static struct cxl_cel_entry mock_cel[] = { }, { .opcode = cpu_to_le16(CXL_MBOX_OP_INJECT_POISON), - .effect = cpu_to_le16(0), + .effect = cpu_to_le16(EFFECT(2)), }, { .opcode = cpu_to_le16(CXL_MBOX_OP_CLEAR_POISON), - .effect = cpu_to_le16(0), + .effect = cpu_to_le16(EFFECT(2)), }, }; From patchwork Mon Jun 5 20:20:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 103484 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2935704vqr; Mon, 5 Jun 2023 13:28:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ40XLUvXZ1e4MxsQP+DfBl1VfRAHup91ABOlL/8o8eoC90IkCDKZJjsMdA3FAynZVon1cZS X-Received: by 2002:a05:6a00:1955:b0:65d:83d8:c3e3 with SMTP id s21-20020a056a00195500b0065d83d8c3e3mr911973pfk.32.1685996933964; Mon, 05 Jun 2023 13:28:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996933; cv=none; d=google.com; s=arc-20160816; b=sQzenFsVbxihebIXmIrVn83dbkjnMLCpq1rmLgzD11heL5i6wocmCNNd05LRVVRij2 6GdRjL3zR9iXFZDWv9kTM8ESrD3V4jVCBZ5iqtv+Bg7oBuLyhc4UUIF/C/YXCg6AG+zG XZwJuus7NdRruxvRmZSc09Ip/WzxHHAI4v6o2aSvQdOJRtmWKzX2jEw0JAwpWPAp3vja CuE/ly7S8eU85/l+6/aFx3ruOHG9LBqUkeKGZQzrTFAji5n0ZwqZFrIjaYZcwJk6TO5o jmg/fB7IgNTYaxzCCcnil2iT/YQdv1YWEMZineXPlfzxCH0cvSptGlxeThhjXByzRBXL RjXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=fisRS1a/DBaAQkbo3QVfbJiKf9uTIoC+UJIQKR7tzx8=; b=WUH2qvT2f1RGVTXLNlHGOraFkvrri6GG4swYI1Sw69+H3gCVHaX0ir/fU35gpx/Gan AQpo2WUsnK965+O0aHWnaKoacj5YSQvEmFgP4C0Bf0sRoDxEXr/cfmxvi/WOty2mZvCF WnMwo3D7mtrDLchdzjCuRuJQfAsufut5pFHP+5t9T2aLRrVWZFteAx4LKZdxRmSaQCLP qB22X82iaaYs/6Ld3vk6BDg5Hr1M61nEPGj8/4dI2pHp4Vyk5cMxwqfsE6fCY7kKRxL/ GBRS3Han6Mdl7LrH3PPFIA25Y5rWGaZPS6lwR3a+v89hkREWcQXedZddmDf7dpvhoAyI RKow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kwHQBRei; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 76-20020a63004f000000b0053ef51d3fa8si5863679pga.401.2023.06.05.13.28.42; Mon, 05 Jun 2023 13:28:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kwHQBRei; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233303AbjFEUVR (ORCPT + 99 others); Mon, 5 Jun 2023 16:21:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233223AbjFEUUz (ORCPT ); Mon, 5 Jun 2023 16:20:55 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5696CE49; Mon, 5 Jun 2023 13:20:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685996454; x=1717532454; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=n4j/XZl+PPPV6uJ0tCXctxrlIofbKWp/qosTAht8r6c=; b=kwHQBReiUL+Wr9yQ2+xfZvYAw9INB6qzi33aK9ylRJGkbdMQYIzMbHBL v7jETbkckZKW9I7mmJHawcO1tbRp/mQC6acwFMaCvZFjgryDi4Znsua1V s5m7TnWR4lKrhl7K0Z494E7lOlVUcCVdfvz1dulR/yGsMdeq9le6f9AYl 59GQimojyqm1zqWRBriIywYHYIe9GVQNCqtyD7eqxPDDE1qtTSc2HkMhm U4bE15wNSsQNhAO3GtquLEEbfhHt0eGuF6U4KBQuKpbBHZcj1fNyD9M8s VWpZMqcxekiD9QvtC6ISlx4LthSg/v2N/SZ4PONdW1n0ObngDBRyg/ThA A==; X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="336093134" X-IronPort-AV: E=Sophos;i="6.00,218,1681196400"; d="scan'208";a="336093134" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 13:20:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="832934195" X-IronPort-AV: E=Sophos;i="6.00,218,1681196400"; d="scan'208";a="832934195" Received: from kmsalzbe-mobl1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.209.52.9]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 13:20:51 -0700 From: Vishal Verma Date: Mon, 05 Jun 2023 14:20:24 -0600 Subject: [PATCH v2 3/4] tools/testing/cxl: Use named effects for the Command Effect Log MIME-Version: 1.0 Message-Id: <20230602-vv-fw_update-v2-3-e9e5cd5adb44@intel.com> References: <20230602-vv-fw_update-v2-0-e9e5cd5adb44@intel.com> In-Reply-To: <20230602-vv-fw_update-v2-0-e9e5cd5adb44@intel.com> To: Alison Schofield , Ira Weiny , Dave Jiang , Ben Widawsky , Dan Williams Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Davidlohr Bueso , Jonathan Cameron , Russ Weight , Vishal Verma X-Mailer: b4 0.13-dev-02a79 X-Developer-Signature: v=1; a=openpgp-sha256; l=2776; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=n4j/XZl+PPPV6uJ0tCXctxrlIofbKWp/qosTAht8r6c=; b=owGbwMvMwCXGf25diOft7jLG02pJDCl1zoscGn/vLPDTf2389OtbgV06Auv+qBZxWW14Hb9x2 ZfmulknOkpZGMS4GGTFFFn+7vnIeExuez5PYIIjzBxWJpAhDFycAjCRosUM/+Nuf877wZs99fWf At2tE4RP/frH9/j9ye0G9Ysu832Tn3GQ4X/gx2Py6uqsuYffntt1ufihj2j2Bk2p6pq6NN3q0PL f/awA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767895920902684379?= X-GMAIL-MSGID: =?utf-8?q?1767895920902684379?= As more emulated mailbox commands are added to cxl_test, it is a pain point to look up command effect numbers for each effect. Replace the bare numbers in the mock driver with an enum that lists all possible effects. Suggested-by: Jonathan Cameron Cc: Davidlohr Bueso Cc: Jonathan Cameron Cc: Russ Weight Cc: Alison Schofield Cc: Ira Weiny Cc: Dave Jiang Cc: Ben Widawsky Cc: Dan Williams Signed-off-by: Vishal Verma Reviewed-by: Alison Schofield Reviewed-by: Jonathan Cameron --- tools/testing/cxl/test/mem.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index 403cd3608772..68668d8df1cd 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -21,42 +21,56 @@ static unsigned int poison_inject_dev_max = MOCK_INJECT_DEV_MAX; +enum cxl_command_effects { + CONF_CHANGE_COLD_RESET = 0, + CONF_CHANGE_IMMEDIATE, + DATA_CHANGE_IMMEDIATE, + POLICY_CHANGE_IMMEDIATE, + LOG_CHANGE_IMMEDIATE, + SECURITY_CHANGE_IMMEDIATE, + BACKGROUND_OP, + SECONDARY_MBOX_SUPPORTED, +}; + +#define CXL_CMD_EFFECT_NONE cpu_to_le16(0) + static struct cxl_cel_entry mock_cel[] = { { .opcode = cpu_to_le16(CXL_MBOX_OP_GET_SUPPORTED_LOGS), - .effect = cpu_to_le16(0), + .effect = CXL_CMD_EFFECT_NONE, }, { .opcode = cpu_to_le16(CXL_MBOX_OP_IDENTIFY), - .effect = cpu_to_le16(0), + .effect = CXL_CMD_EFFECT_NONE, }, { .opcode = cpu_to_le16(CXL_MBOX_OP_GET_LSA), - .effect = cpu_to_le16(0), + .effect = CXL_CMD_EFFECT_NONE, }, { .opcode = cpu_to_le16(CXL_MBOX_OP_GET_PARTITION_INFO), - .effect = cpu_to_le16(0), + .effect = CXL_CMD_EFFECT_NONE, }, { .opcode = cpu_to_le16(CXL_MBOX_OP_SET_LSA), - .effect = cpu_to_le16(EFFECT(1) | EFFECT(2)), + .effect = cpu_to_le16(EFFECT(CONF_CHANGE_IMMEDIATE) | + EFFECT(DATA_CHANGE_IMMEDIATE)), }, { .opcode = cpu_to_le16(CXL_MBOX_OP_GET_HEALTH_INFO), - .effect = cpu_to_le16(0), + .effect = CXL_CMD_EFFECT_NONE, }, { .opcode = cpu_to_le16(CXL_MBOX_OP_GET_POISON), - .effect = cpu_to_le16(0), + .effect = CXL_CMD_EFFECT_NONE, }, { .opcode = cpu_to_le16(CXL_MBOX_OP_INJECT_POISON), - .effect = cpu_to_le16(EFFECT(2)), + .effect = cpu_to_le16(EFFECT(DATA_CHANGE_IMMEDIATE)), }, { .opcode = cpu_to_le16(CXL_MBOX_OP_CLEAR_POISON), - .effect = cpu_to_le16(EFFECT(2)), + .effect = cpu_to_le16(EFFECT(DATA_CHANGE_IMMEDIATE)), }, }; From patchwork Mon Jun 5 20:20:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 103495 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2943798vqr; Mon, 5 Jun 2023 13:47:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7Q/uzo18D9oxyQoOdzCDvva99ospBIaUpA/rxVclMu+Z3mQ/xP3g3nyZapdS0MklQ+5h9I X-Received: by 2002:a17:903:4295:b0:1ae:5914:cbec with SMTP id ju21-20020a170903429500b001ae5914cbecmr128376plb.10.1685998061828; Mon, 05 Jun 2023 13:47:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685998061; cv=none; d=google.com; s=arc-20160816; b=hf83QkjVwowRLdGpK7IT7U+gpP3NGfSRNHXelKzNNxvVA0ayJsIaXKz/7+NOTUCJ7P IhPY/6Q+fBuNKspcbzzSLYpcS2af8CTalu0hljzun5dEWVWMOPI71LN3BtAVb+rj3MyJ /cQGvKTii9+qAgt3D57lx+/m5hT2cG8K4aMvplw0m130UW1y/AjKdqHaHHzOIuv4XXA+ 8sP/4WhMTTxTt7SI45GzvUzlS0NxLHH6w5C0kHmSP/BZMHBWle8QbufShxVrfPU/Rzb+ LcQxzG+ALTvHRHiFvQrJm3r/f1FH0s+KyUdHA4PKW1TCckL0g9ZNBHCMX6ecJ0Dof3PX mmnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=4KbGjY1528AP/FppRCGQH5OYGPQyr7oobo8DqOHk1OQ=; b=sKnuJfT0NHMqbtBvPoFjoVucW+oD4UNxQ9+RQr3OkUt+qB3ZHT49VIE1Md5ie6WEI1 LTxt+poyUkPJhoiKCfZEWL++oVouv2j8OLbv1OjBlGvtJC09cMBZstnOPv2UuQQ2hwx2 dk9IPFzHfc/Y334s8N8gD7JzNTrXkonMcT557z23LF47eIY/haVEHUGbrW2zadljgLQ7 11C+ExZJDERIoKI8YXCCnC6FiSrcAyCWO4rJwnUmHwpaYMfvztg1jNHXRFP1d8C6Gjxm 0sgaCyI05VfQAmgXko6Je5l/omRchEDjo3GFEbMaPd54zLnpCdnT+xBOp7S8p1L0Dz0H 6nxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Zzy1dbl8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e12-20020a17090301cc00b001ae82f13a0fsi5878659plh.643.2023.06.05.13.47.28; Mon, 05 Jun 2023 13:47:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Zzy1dbl8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233441AbjFEUVV (ORCPT + 99 others); Mon, 5 Jun 2023 16:21:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233231AbjFEUUz (ORCPT ); Mon, 5 Jun 2023 16:20:55 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4E1EE51; Mon, 5 Jun 2023 13:20:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685996454; x=1717532454; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=W92jXIm9Uj41TzT4x8llGd5p8AikQXwJ1DpwOqr+LHs=; b=Zzy1dbl8dNMhdUpB8s10P2KvCa2O7ZDBGmgvkBSOTqbm1NMKPxW+6XlA kK+l6Lp/0KwKXPNBt1mGq7JURI9w7kcN4V2WfC4U2ZDOBIdAnMeHl7L4m TDvD+u4AvwqoLy/SXzPej5yQyqA6AdNcErBNC9uGMqnfohcdlZlTssuhV EzfV+P6zry2LCmKvUIXEhwH9o9MLD9PLkh46r0Xz/q5VkwCQYOqj8QguL rVlOQ4nhJZxxv4XXp2W5Z7KW4Y4oA3u+RIG0te4HKKSDt19oay0MV0slE QPI03VZ250htmlYnWzIWfJn8ucXHeSzRB3yrwOv8KY2RFmh/ESEBACZeD g==; X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="336093140" X-IronPort-AV: E=Sophos;i="6.00,218,1681196400"; d="scan'208";a="336093140" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 13:20:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="832934200" X-IronPort-AV: E=Sophos;i="6.00,218,1681196400"; d="scan'208";a="832934200" Received: from kmsalzbe-mobl1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.209.52.9]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 13:20:52 -0700 From: Vishal Verma Date: Mon, 05 Jun 2023 14:20:25 -0600 Subject: [PATCH v2 4/4] tools/testing/cxl: add firmware update emulation to CXL memdevs MIME-Version: 1.0 Message-Id: <20230602-vv-fw_update-v2-4-e9e5cd5adb44@intel.com> References: <20230602-vv-fw_update-v2-0-e9e5cd5adb44@intel.com> In-Reply-To: <20230602-vv-fw_update-v2-0-e9e5cd5adb44@intel.com> To: Alison Schofield , Ira Weiny , Dave Jiang , Ben Widawsky , Dan Williams Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Davidlohr Bueso , Jonathan Cameron , Russ Weight , Vishal Verma X-Mailer: b4 0.13-dev-02a79 X-Developer-Signature: v=1; a=openpgp-sha256; l=7722; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=W92jXIm9Uj41TzT4x8llGd5p8AikQXwJ1DpwOqr+LHs=; b=owGbwMvMwCXGf25diOft7jLG02pJDCl1zos0+5ui7005OyfXq+G6unGt8o8X1ge7lqn7ZuTNX e4cfvl2RykLgxgXg6yYIsvfPR8Zj8ltz+cJTHCEmcPKBDKEgYtTACayXYXhn+lp84nPhW7YvHyQ /a9Ia91/72kbPfUba896uARIM33+3MnwT1/n47X5sxlXnn0Z/IGtcYfce/kjUpyLFy/PN0tVa73 pxgEA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767897103724865549?= X-GMAIL-MSGID: =?utf-8?q?1767897103724865549?= Add emulation for the 'Get FW Info', 'Transfer FW', and 'Activate FW' CXL mailbox commands to the cxl_test emulated memdevs to enable end-to-end unit testing of a firmware update flow. For now, only advertise an 'offline activation' capability as that is all the CXL memdev driver currently implements. Add some canned values for the serial number fields, and create a platform device sysfs knob to calculate the sha256sum of the firmware image that was received, so a unit test can compare it with the original file that was uploaded. Cc: Davidlohr Bueso Cc: Jonathan Cameron Cc: Russ Weight Cc: Alison Schofield Cc: Ira Weiny Cc: Dave Jiang Cc: Ben Widawsky Cc: Dan Williams Signed-off-by: Vishal Verma Reviewed-by: Jonathan Cameron --- tools/testing/cxl/test/mem.c | 162 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 162 insertions(+) diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index 68668d8df1cd..70cedeac0a49 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -8,11 +8,14 @@ #include #include #include +#include #include #include "trace.h" #define LSA_SIZE SZ_128K +#define FW_SIZE SZ_64M +#define FW_SLOTS 3 #define DEV_SIZE SZ_2G #define EFFECT(x) (1U << x) @@ -72,6 +75,20 @@ static struct cxl_cel_entry mock_cel[] = { .opcode = cpu_to_le16(CXL_MBOX_OP_CLEAR_POISON), .effect = cpu_to_le16(EFFECT(DATA_CHANGE_IMMEDIATE)), }, + { + .opcode = cpu_to_le16(CXL_MBOX_OP_GET_FW_INFO), + .effect = CXL_CMD_EFFECT_NONE, + }, + { + .opcode = cpu_to_le16(CXL_MBOX_OP_TRANSFER_FW), + .effect = cpu_to_le16(EFFECT(CONF_CHANGE_COLD_RESET) | + EFFECT(BACKGROUND_OP)), + }, + { + .opcode = cpu_to_le16(CXL_MBOX_OP_ACTIVATE_FW), + .effect = cpu_to_le16(EFFECT(CONF_CHANGE_COLD_RESET) | + EFFECT(CONF_CHANGE_IMMEDIATE)), + }, }; /* See CXL 2.0 Table 181 Get Health Info Output Payload */ @@ -123,6 +140,10 @@ struct mock_event_store { struct cxl_mockmem_data { void *lsa; + void *fw; + int fw_slot; + int fw_staged; + size_t fw_size; u32 security_state; u8 user_pass[NVDIMM_PASSPHRASE_LEN]; u8 master_pass[NVDIMM_PASSPHRASE_LEN]; @@ -1128,6 +1149,89 @@ static struct attribute *cxl_mock_mem_core_attrs[] = { }; ATTRIBUTE_GROUPS(cxl_mock_mem_core); +static int mock_fw_info(struct cxl_dev_state *cxlds, + struct cxl_mbox_cmd *cmd) +{ + struct cxl_mockmem_data *mdata = dev_get_drvdata(cxlds->dev); + struct cxl_mbox_get_fw_info fw_info = { + .num_slots = FW_SLOTS, + .slot_info = (mdata->fw_slot & 0x7) | + ((mdata->fw_staged & 0x7) << 3), + .activation_cap = 0, + }; + + strcpy(fw_info.slot_1_revision, "cxl_test_fw_001"); + strcpy(fw_info.slot_2_revision, "cxl_test_fw_002"); + strcpy(fw_info.slot_3_revision, "cxl_test_fw_003"); + strcpy(fw_info.slot_4_revision, ""); + + if (cmd->size_out < sizeof(fw_info)) + return -EINVAL; + + memcpy(cmd->payload_out, &fw_info, sizeof(fw_info)); + return 0; +} + +static int mock_transfer_fw(struct cxl_dev_state *cxlds, + struct cxl_mbox_cmd *cmd) +{ + struct cxl_mbox_transfer_fw *transfer = cmd->payload_in; + struct cxl_mockmem_data *mdata = dev_get_drvdata(cxlds->dev); + void *fw = mdata->fw; + size_t offset, length; + + offset = le32_to_cpu(transfer->offset) * CXL_FW_TRANSFER_ALIGNMENT; + length = cmd->size_in - sizeof(*transfer); + if (offset + length > FW_SIZE) + return -EINVAL; + + switch (transfer->action) { + case CXL_FW_TRANSFER_ACTION_FULL: + if (offset != 0) + return -EINVAL; + fallthrough; + case CXL_FW_TRANSFER_ACTION_END: + if (transfer->slot == 0 || transfer->slot > FW_SLOTS) + return -EINVAL; + mdata->fw_size = offset + length; + break; + case CXL_FW_TRANSFER_ACTION_INITIATE: + case CXL_FW_TRANSFER_ACTION_CONTINUE: + break; + case CXL_FW_TRANSFER_ACTION_ABORT: + return 0; + default: + return -EINVAL; + } + + memcpy(fw + offset, transfer->data, length); + return 0; +} + +static int mock_activate_fw(struct cxl_dev_state *cxlds, + struct cxl_mbox_cmd *cmd) +{ + struct cxl_mbox_activate_fw *activate = cmd->payload_in; + struct cxl_mockmem_data *mdata = dev_get_drvdata(cxlds->dev); + + if (activate->slot == 0 || activate->slot > FW_SLOTS) + return -EINVAL; + + switch (activate->action) { + case CXL_FW_ACTIVATE_ONLINE: + mdata->fw_slot = activate->slot; + mdata->fw_staged = 0; + break; + case CXL_FW_ACTIVATE_OFFLINE: + mdata->fw_staged = activate->slot; + break; + default: + return -EINVAL; + } + + return 0; +} + static int cxl_mock_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) { struct device *dev = cxlds->dev; @@ -1194,6 +1298,15 @@ static int cxl_mock_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd * case CXL_MBOX_OP_CLEAR_POISON: rc = mock_clear_poison(cxlds, cmd); break; + case CXL_MBOX_OP_GET_FW_INFO: + rc = mock_fw_info(cxlds, cmd); + break; + case CXL_MBOX_OP_TRANSFER_FW: + rc = mock_transfer_fw(cxlds, cmd); + break; + case CXL_MBOX_OP_ACTIVATE_FW: + rc = mock_activate_fw(cxlds, cmd); + break; default: break; } @@ -1209,6 +1322,11 @@ static void label_area_release(void *lsa) vfree(lsa); } +static void fw_buf_release(void *buf) +{ + vfree(buf); +} + static bool is_rcd(struct platform_device *pdev) { const struct platform_device_id *id = platform_get_device_id(pdev); @@ -1241,10 +1359,19 @@ static int cxl_mock_mem_probe(struct platform_device *pdev) mdata->lsa = vmalloc(LSA_SIZE); if (!mdata->lsa) return -ENOMEM; + mdata->fw = vmalloc(FW_SIZE); + if (!mdata->fw) + return -ENOMEM; + mdata->fw_slot = 2; + rc = devm_add_action_or_reset(dev, label_area_release, mdata->lsa); if (rc) return rc; + rc = devm_add_action_or_reset(dev, fw_buf_release, mdata->fw); + if (rc) + return rc; + cxlds = cxl_dev_state_create(dev); if (IS_ERR(cxlds)) return PTR_ERR(cxlds); @@ -1286,6 +1413,10 @@ static int cxl_mock_mem_probe(struct platform_device *pdev) if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); + rc = cxl_memdev_setup_fw_upload(cxlds); + if (rc) + return rc; + cxl_mem_get_event_records(cxlds, CXLDEV_EVENT_STATUS_ALL); return 0; @@ -1324,9 +1455,40 @@ static ssize_t security_lock_store(struct device *dev, struct device_attribute * static DEVICE_ATTR_RW(security_lock); +static ssize_t fw_buf_checksum_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); + u8 hash[SHA256_DIGEST_SIZE]; + unsigned char *hstr, *hptr; + struct sha256_state sctx; + ssize_t written = 0; + int i; + + sha256_init(&sctx); + sha256_update(&sctx, mdata->fw, mdata->fw_size); + sha256_final(&sctx, hash); + + hstr = kzalloc((SHA256_DIGEST_SIZE * 2) + 1, GFP_KERNEL); + if (!hstr) + return -ENOMEM; + + hptr = hstr; + for (i = 0; i < SHA256_DIGEST_SIZE; i++) + hptr += sprintf(hptr, "%02x", hash[i]); + + written = sysfs_emit(buf, "%s\n", hstr); + + kfree(hstr); + return written; +} + +static DEVICE_ATTR_RO(fw_buf_checksum); + static struct attribute *cxl_mock_mem_attrs[] = { &dev_attr_security_lock.attr, &dev_attr_event_trigger.attr, + &dev_attr_fw_buf_checksum.attr, NULL }; ATTRIBUTE_GROUPS(cxl_mock_mem);