From patchwork Wed Oct 26 14:16:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11288 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp295101wru; Wed, 26 Oct 2022 07:18:31 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5XpNgZ3ip/0HgTtSut0tXPg48u8ZT4nA0qknRg7JAgF00CcyVNunAWjD0XQR9SmP+6PFTW X-Received: by 2002:a62:5e81:0:b0:563:1f18:62ab with SMTP id s123-20020a625e81000000b005631f1862abmr43901185pfb.76.1666793911239; Wed, 26 Oct 2022 07:18:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666793911; cv=none; d=google.com; s=arc-20160816; b=Fk32oxBnTCoXXEGV0k4HeA6bwVtegOeQgEW7ztDnL+gKZG6RXKtSLYPh/Q0RCB3Nra 1VUgofoBXa7l85ggggCPCw0kUS90s/YG4uRNCvKE4/D36qRijsy7b+Wg0b9u8TqBFa+x yFf7RGIIi7GSE7rJl4+8vU9E0wI6vEusD2QlbR+29BAXpfpOjTTJqSIrnUb65Xua8OMc LmVptJa/hpIm6ZmTIN7Te+JbNf2OMYXv2LVDUYMCTydx8wkaKGqTUN1H1yzAWdAhuRDR GlviMRRTIatliE3mJLxbfxdmHenlUyyPIrfzHV9EheRZcfUH4aS1LnTI4n/U+oeisam7 aSKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=jzDxtWm1hAxBK/2Cn8zYbtv1BJCSFJA3H9ka3nwoics=; b=kALrI6EGvY/kjE6gaTW0rGPmlQdZ/t+8GIMzlD7MgV6lfM2vN/O4d28pSpZRbAheLC la9zsRxcj+URNZYj1B9oHU/jUfHSCyZbPouoFtizng3QGVye/sbV+kZRDTcUcpzBpRDJ 8NFbQoBNiyvokHT8iE2A4PnEat2CBsuFUIDQ69V5v3wnBtnH4m4KfsDvdBT3eFRypmzy cP3e34dw7Qa98kpF3lq25H/QRUTSI9Z0mgOxOMm4/MwBEFZCFjgOTZQoZZz2i2bgH4WO VWQIrPqoPlZQWouZp3fwC9IySWQCCBF1U8S4dtq28BY86Dirpyqlw5c4BhsLnNxKgCUo sS2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=tRcZLhtk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m33-20020a635821000000b00451b094d74bsi7189841pgb.454.2022.10.26.07.18.17; Wed, 26 Oct 2022 07:18:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=tRcZLhtk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233957AbiJZOQp (ORCPT + 99 others); Wed, 26 Oct 2022 10:16:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232906AbiJZOQn (ORCPT ); Wed, 26 Oct 2022 10:16:43 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54FC8F682C; Wed, 26 Oct 2022 07:16:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E5E6561F08; Wed, 26 Oct 2022 14:16:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2F146C433D6; Wed, 26 Oct 2022 14:16:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666793802; bh=4sbYQ1JjOf2cO851WHCHY1Zq78kCtJj8OQbcl0ns6Wc=; h=From:To:Cc:Subject:Date:From; b=tRcZLhtkJvU8yKeyyubVEGg+DXBbc1HY/0UNCdAgOpzQyoUF1OazH9+UOZf1nehfR qWqlGu07+4CP+8J3jordoCgUepnM4owBzenmDpn5/nAVkfLmHbHtLE9Hedht+dTRkv RLxilEJYU2bjy3FqWtntfgVvR8DOrglOeWkW0f60TQSKYJicGaXnkzP7aQkI/8wq6P XNExJVm9vn0+pV75FFAdwnXj83n+Jzx0TsIfvE+4RRUnl7mZ1bW5aabFEqAqrT7Wtl plM4OJfyOxQzAQH3s+ef3X6wWee/s9WMopIa+naIPDoOxx8yiqiDnL6jocMzTw4Ecd tTtOhw9yzIy/Q== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv6 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Date: Wed, 26 Oct 2022 09:16:26 -0500 Message-Id: <20221026141631.696863-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747760091907021873?= X-GMAIL-MSGID: =?utf-8?q?1747760091907021873?= Document the optional "altr,sysmgr-syscon" binding that is used to access the System Manager register that controls the SDMMC clock phase. Signed-off-by: Dinh Nguyen --- v6: make "altr,sysmgr-syscon" optional v5: document reg shift v4: add else statement v3: document that the "altr,sysmgr-syscon" binding is only applicable to "altr,socfpga-dw-mshc" v2: document "altr,sysmgr-syscon" in the MMC section --- .../bindings/mmc/synopsys-dw-mshc.yaml | 23 ++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..0e2024eb9018 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller Binding -allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" - maintainers: - Ulf Hansson @@ -38,6 +35,26 @@ properties: - const: biu - const: ciu +allOf: + - $ref: synopsys-dw-mshc-common.yaml# + + - if: + properties: + compatible: + contains: + const: altr,socfpga-dw-mshc + then: + properties: + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + - description: register shift for the smplsel(drive in) setting + else: + properties: + altr,sysmgr-syscon: false + required: - compatible - reg From patchwork Wed Oct 26 14:16:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11287 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp295087wru; Wed, 26 Oct 2022 07:18:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7gfRrfX981BJXzwK+5SgO3UTYwASjDpfk1z5l06THevro0+6dICpBVndTRORAdPXNIoxZS X-Received: by 2002:a63:8141:0:b0:460:5be4:f6a9 with SMTP id t62-20020a638141000000b004605be4f6a9mr37357993pgd.368.1666793910129; Wed, 26 Oct 2022 07:18:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666793910; cv=none; d=google.com; s=arc-20160816; b=gujDU+qNfDFDJ21rXG0qaHYjdzkn4Py/e14V2b/6TXnd1HdS6QZGeYSpZmb9XDO89I qUseKmeUR9ZxK4+yLRhJkosvg+2B+OgLmmxWmNNxY37cZWGIovLSEpZuDtL2ezk5F9rA 1W5d6bOt5RrdkjDgO/BOW0THcw16rX1jPpsAJyyB66XnNttdaZ5v+tFfz5hiGV5CyFjw 1Cpw+7McyMfpVjHhLu52OObi68jmsGqWxc8lQ0Q/p6gSkMWtL7uTJMQ0/MTwWuHv7xCB lmkY+qhYlzevm55YSQb1RW6j3aDZYRDoxN3FBfPLxV0dNtsI+m8KfZ/7UWt2/RqOY35V +4ZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dl/nIKUl6ZzWfIj5p34z+xL6I1Jeog2aEDnPRqUCekI=; b=JSGHtftHI7n1CuUqHJTX6n0GYU+8zFjyJNoAeJcEEsHyyuzCCBSY2PUd6l8vUERH+a okdJcHVtxUxMPVQ8nvjRzfbimjIzIXf8ztqUQ9uW1/qHZxoN7Iev65cufL/R0/hGpaHm Iz7q1NweseFwIERahtHzEaVae34OktL5OxBimGPfMc/0gVKlligmaGmFd4iKZS492FSV uuwJTDnfmTpwVLWy0dI1/plcR0N8EG4kqV3DwKOifoOEirADYaHSfskMNke/4s4Tncxf ziSVSPG4tdZvLuE2ptLy28Xey6iFB9jKUFylnPWlrNzXGffilDifsGHlND9tcE5+Ey9l Td9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=TsLbQArU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z7-20020a170903018700b0016c44b7c8c5si7746387plg.11.2022.10.26.07.18.16; Wed, 26 Oct 2022 07:18:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=TsLbQArU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234212AbiJZOQs (ORCPT + 99 others); Wed, 26 Oct 2022 10:16:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234040AbiJZOQq (ORCPT ); Wed, 26 Oct 2022 10:16:46 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 404A3F682C; Wed, 26 Oct 2022 07:16:44 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7F74661F08; Wed, 26 Oct 2022 14:16:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A29BC4347C; Wed, 26 Oct 2022 14:16:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666793803; bh=JNusVUTUYyQfT5S+TAUJirTaGbJaVIsL6OpDEajfEfE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TsLbQArU9UhJieLBFmK/CktWUcozAMlKf3cUSYV/VsHHtUDWalpc99hxzg7P8TSht j+Lp8qrbMb3lLm5Hd3s5vb4OhdAGO9GuAY5lZYUKd4XygqitrAg2rwMEuxiZ9zOdgh vfv0iwg9y1Wz4rnOBsxwAq6b73UcnyQOfweghOVI6roBuVNXwmIk6hC/Nkp7a6Bltl Futm1pjSQVkslJo7pJgNid30tbERZPoRorxFZTF9ZMJo1K7XizSdA9ZAxdZIIlCmXi 9fktYalVMBFzooq3SsBUQQpv35OsJER8UUlxaKXQLo8Wj3oahjzyrj4BiJIerlfEnU J5ytqselcBwvw== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv6 2/6] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Date: Wed, 26 Oct 2022 09:16:27 -0500 Message-Id: <20221026141631.696863-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026141631.696863-1-dinguyen@kernel.org> References: <20221026141631.696863-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747760090960051182?= X-GMAIL-MSGID: =?utf-8?q?1747760090960051182?= The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen --- v6: no changes v5: add back reg_shift v4: no change v3: removed unnecessary property in "altr,sysmgr-syscon" --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 + arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 + arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 14c220d87807..55c5e1fdddc7 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -309,6 +309,7 @@ mmc: mmc@ff808000 { <&clkmgr STRATIX10_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 48424e459f12..19e7284b4cd5 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -105,6 +105,7 @@ &mmc { cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 7bbec8aafa62..849b46dd8098 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -313,6 +313,7 @@ mmc: mmc@ff808000 { <&clkmgr AGILEX_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 26cd3c121757..07c3f8876613 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -83,6 +83,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 62c66e52b656..08c088571270 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -74,6 +74,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { From patchwork Wed Oct 26 14:16:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11293 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp295762wru; Wed, 26 Oct 2022 07:19:48 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6sWG2eJCG4aV2Dzp6gWvdLH50sQ2BEzN0jn/f6NXp0UWEeefAXgvbRF87CGx9EYHFEOAke X-Received: by 2002:a17:902:ccc2:b0:178:29f9:5c5e with SMTP id z2-20020a170902ccc200b0017829f95c5emr42131901ple.21.1666793977189; Wed, 26 Oct 2022 07:19:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666793977; cv=none; d=google.com; s=arc-20160816; b=j5TD3uIg6L5BFGIfOvfrSKMZNR7mWM7w9Y+KOQVdCsFELRJTddMjSKv1+YChqqP2L3 a12g9Jx0lU2zSfMT8PSt4ajP+DknSjxsVsQR4eYVhO3L4Wz3XCCMQXtMWUsfOYl70zjF VSY16pHYyVCDfaeEeuxCXOuwfaM7BKZBkdpFgNXgjdQIi5wOGiiN+pMdH33t8Ms8ovln Kn62T6mxTwLW/+0D4UrNSfdkM6G+LbqKZUiV2501yxgjVE7U444j4JOiwhp5owDZSIus Ce2w+DYza2hfZk2vwNY9c1XgTcPA2pPpf5Tvf8z5kgGtQtwCBihQNpOzfpC8TuHJiP5V X98A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nMih3yYAF+yTQFQglnUR0KhkgUPiz7U6LcyprygoGhA=; b=k3L+ircy3KCvs1osCp/5aCQUAeVRkaAm+SqQp9E6BAlz/DT6O7xbvSNLpkHgflsAW1 u84KfMuZlQr+ASit1WAjdf6OHtU/ESwYwQ9lfpjs1AD/Q2uMFI7bc1IIWy4oJ0a8cIDv SgVS1pRlDcUM7w6SYZVdyZmLbT+vGYRu91QDiiHkxh3uhTm/erUr34QvvHsTA+RMewnw Bt8R4zAlI+o27wgzrzLLj4wVLCoZJCVVMfwDmkXySFXm1RW5jVn7mJyU52voy5Wiy6rV IfZY6sZQdgUmpIV2UOfQbWGkWOYXj9p4m3EyQOcfvro4tLLvwqgnkdo9zA+oS9awFV6q zKLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=AinmZBcR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k5-20020a628405000000b0054342bb20e2si6850334pfd.66.2022.10.26.07.19.23; Wed, 26 Oct 2022 07:19:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=AinmZBcR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234223AbiJZOQv (ORCPT + 99 others); Wed, 26 Oct 2022 10:16:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234215AbiJZOQt (ORCPT ); Wed, 26 Oct 2022 10:16:49 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E204310F8A4; Wed, 26 Oct 2022 07:16:47 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A0243B822B2; Wed, 26 Oct 2022 14:16:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3572DC433D7; Wed, 26 Oct 2022 14:16:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666793805; bh=y6BpGTh+5WA+hwTvUftgaEwVfmogQE8WdCM7HwR5eH8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AinmZBcRkYh1owKvF/k2zWOi+C8b6Y0vv3hrQ28/vd2HC7EjlZ06CeeicVO6Ttebd zufJVjma94VUqWssVYpJaRmvc+ybV+BsEKXX7q/iO5dyROrm7tHt0GGsU8r5g49j+N tZJJjDEZrhnlXjBtD/18y7qze3dqYaV20sbFTqkZod7IbUS+1wipQhGUSeL7LeHbF7 0yutKrjddLY4v0lroHwW+vprfYg2/ScF7/riAv+HVB4no1rHftiBFsPK1LtmSORP8s UPhQ72IR+Una5SCriN+Pt0GQGlkOPlKj/sqVAdNOHwEKGUpOz2V/TnrgyYhQ69txbS SQ4efyWgWc05g== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv6 3/6] arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Date: Wed, 26 Oct 2022 09:16:28 -0500 Message-Id: <20221026141631.696863-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026141631.696863-1-dinguyen@kernel.org> References: <20221026141631.696863-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747760161385370791?= X-GMAIL-MSGID: =?utf-8?q?1747760161385370791?= The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen --- v6: no changes v5: new --- arch/arm/boot/dts/socfpga.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 1 + arch/arm/boot/dts/socfpga_arria5.dtsi | 1 + arch/arm/boot/dts/socfpga_cyclone5.dtsi | 1 + arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2459f3cd7dd9..604fc6e0c4ad 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -765,6 +765,7 @@ mmc: dwmmc0@ff704000 { clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x108 3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4370e3cbbb4b..b6ebe207e2bc 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -666,6 +666,7 @@ mmc: dwmmc0@ff808000 { clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index ad7cd14de6b6..41f865c8c098 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -73,6 +73,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts index 64dc0799f3d7..d3969367f4b5 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts @@ -12,6 +12,7 @@ &mmc { cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &eccmgr { diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 22dbf07afcff..b531639ce7dc 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 { bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 319a71e41ea4..a9d1ba66f1ff 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 { bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi index bd92806ffc12..3b9daddf91cd 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi @@ -18,5 +18,6 @@ memory@0 { &mmc0 { /* On-SoM eMMC */ bus-width = <8>; + clk-phase-sd-hs = <0>, <135>; status = "okay"; }; From patchwork Wed Oct 26 14:16:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11292 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp295448wru; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t4-20020a656084000000b0045a048683dcsi5987447pgu.236.2022.10.26.07.18.45; Wed, 26 Oct 2022 07:18:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=iniyl5UY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234217AbiJZOQz (ORCPT + 99 others); Wed, 26 Oct 2022 10:16:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234221AbiJZOQu (ORCPT ); Wed, 26 Oct 2022 10:16:50 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A85610F881; Wed, 26 Oct 2022 07:16:49 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 2BA78B822B3; Wed, 26 Oct 2022 14:16:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94B68C43143; Wed, 26 Oct 2022 14:16:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666793806; bh=20zEspJzMm9fflHXzbJ8RnT9WirOG5GHjev3+HrUS8I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iniyl5UY1LvOsCYnn2hXyaYBmj0zNdLE7/xJmDtUT12Gsa+C9ki81nB0bewpGT5zv n1jFBUj+LYHhoTgX04OZ/g1qvWqlY9T1ZIXsl377gAnTvd5Ul6iO8fUHWdQdhkjHTK pdpyKLk2219g+G3/Z40KUTeBTZWJLxDMX29Muo0vY3NnsYei+cbj/y9OaUG8lpenBY euZnNK+bXJK9hd/NuFQGkmfez6b8b74gGBKgblZvjc++FnD5bb/8EPXXCs+bjaJnSX UlfHtTgOoTY7atAQMmIF5xc6iRxAP4x0UDlAqCEuyPhHer4z8MsXGSLqjtQIYh+K4e 6lDj8qrrLuwwQ== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv6 4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Date: Wed, 26 Oct 2022 09:16:29 -0500 Message-Id: <20221026141631.696863-4-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026141631.696863-1-dinguyen@kernel.org> References: <20221026141631.696863-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747760121800963189?= X-GMAIL-MSGID: =?utf-8?q?1747760121800963189?= The clock-phase settings for the SDMMC controller in the SoCFPGA platforms reside in a register in the System Manager. Add a method to access that register through the syscon interface. Signed-off-by: Dinh Nguyen --- v6: not getting the clk-phase-sd-hs is not a hard failure v5: change error handling from of_property_read_variable_u32_array() support arm32 by reading the reg_shift v4: no change v3: add space before &socfpga_drv_data v2: simplify clk-phase calculations make property optional in driver --- drivers/mmc/host/dw_mmc-pltfm.c | 43 ++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index 9901208be797..fff6222d58e4 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -17,10 +17,16 @@ #include #include #include +#include +#include #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP 45 +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ + ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0)) + int dw_mci_pltfm_register(struct platform_device *pdev, const struct dw_mci_drv_data *drv_data) { @@ -62,9 +68,44 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = { }; EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); +static int dw_mci_socfpga_priv_init(struct dw_mci *host) +{ + struct device_node *np = host->dev->of_node; + struct regmap *sys_mgr_base_addr; + u32 clk_phase[2] = {0}, reg_offset, reg_shift; + int i, rc, hs_timing; + + rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); + if (rc < 0) { + dev_info(host->dev, "Optional: clk-phase-sd-hs not found!\n"); + return 0; + } + + sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); + if (IS_ERR(sys_mgr_base_addr)) { + dev_info(host->dev, "Optional: failed to find altr,sys-mgr regmap!\n"); + return 0; + } + + of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); + of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); + + for (i = 0; i < ARRAY_SIZE(clk_phase); i++) + clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP; + + hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift); + regmap_write(sys_mgr_base_addr, reg_offset, hs_timing); + + return 0; +} + +static const struct dw_mci_drv_data socfpga_drv_data = { + .init = dw_mci_socfpga_priv_init, +}; + static const struct of_device_id dw_mci_pltfm_match[] = { { .compatible = "snps,dw-mshc", }, - { .compatible = "altr,socfpga-dw-mshc", }, + { .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, }, { .compatible = "img,pistachio-dw-mshc", }, {}, }; From patchwork Wed Oct 26 14:16:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11290 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp295294wru; Wed, 26 Oct 2022 07:18:53 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6vpRdn3EDsxaIQHNlyg0u1wLsrnxcbRpSOoCOcPle5WJShpq1CIo7KyxnwFHl+E1mZ+zSH X-Received: by 2002:a63:7909:0:b0:458:1ba6:ec80 with SMTP id u9-20020a637909000000b004581ba6ec80mr38395236pgc.414.1666793932989; Wed, 26 Oct 2022 07:18:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666793932; cv=none; d=google.com; s=arc-20160816; b=SufJsJOGyCVIJRVve6m6Gjf/dTyvDJxB7t555/hmEHXAQMuhYq1dchvm6kFvqS6xx2 7Gp5acmYKIdpuyiekp4CUQjgsK9nTCUM8/mZVVYrw6EyGx2mUr4ON8XeXOZwcjgBvx6E yH6gRFKw/BjvdFGz03OO5268h/IgnXsdJ16qAl37stL1mqbE94b92TBauKq120A2WHEi 9Lj43R7pxZ+P+xyEGIvXRvsDAuMrJ2BpHe1eSaBqa4Atf64MkzmIF//+stZK7adJ8XQs 9i/1tCAI0ScYPl6GxC9oIJwr0h+nF98l0EuBNvud7BuHqFQFo/Iwm9kSu584LRenjsGl ubqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AgpdiZqKuA+KRlSG8T3IJiI0hmz8qyVa8ZO4oK15Q7E=; b=R7V0gUCU3ZsJ6wIGOduDy5fkX3y3YKkduLY/CbehbvLS3nLyf3A5eDP3KDDKiOGCbV fWA7nXvQT6ASn+JeWqsG2fn8nrD/nqGMmrt/Rqzj4OB+Kq78vSWrSLXtqjxV7gfnGZWJ 4azKlxsyljs/KNPyUqst5lVX25PfgN/HiIkWlaV3WfGxTRMV4R4LRK9T6L3ZdvVPaccj Wjfujhc56rMgib9M1Mxjeg8EKzbMCAeu/zVGVfXCs2kpYOLED37G15c0BFBGb7P5YekI 8/o5jFTtZPtvthjD/yOeZNvPDtGEJM4fKmiIkJ3TkdOtv0C73ziWisGL9al4GeZIugcc eTOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=k89Yhgqz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m14-20020a170902db0e00b001782a6fbc7csi8102812plx.463.2022.10.26.07.18.39; Wed, 26 Oct 2022 07:18:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=k89Yhgqz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234229AbiJZORF (ORCPT + 99 others); Wed, 26 Oct 2022 10:17:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234225AbiJZOQw (ORCPT ); Wed, 26 Oct 2022 10:16:52 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F256510F8A6; Wed, 26 Oct 2022 07:16:50 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A41F3B8224D; Wed, 26 Oct 2022 14:16:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 27F3FC433D6; Wed, 26 Oct 2022 14:16:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666793808; bh=F/UkwECDYYfjVBSUKXbQqh8KWSiKfMvFy1f9yNwcZu0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k89YhgqzFPugPebWzK3/JC8WlnveKq+SQq/RI+srPT1QPBBrvhWpBh0vmpMPsr8Zj rgJPVec7FSbj3XXd5x2+c62Kjr5ajVoEZs17gbb5ELDPwCD2y+JgrjKYKD82S+b2eM yL+p4C4z7x/QgwL/vS5+EUKtbfn7zNOR0+cldMxfkamxC/krIQEGL19L3mu8LYutnZ x7zymVfneyl+wT1RBRqTd0U1XNhRFvlBixs3a6W2qd78opgi50cYsyMZHpVK+D1lXJ jrO1uOJKUeCQn2KSJVj0DeIAtlT6HLRoKVn/Raqh1ofJ5IYcbwNylwLyyufv0SS7Sy fXgKbuz/7iHNA== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv6 5/6] clk: socfpga: remove the setting of clk-phase for sdmmc_clk Date: Wed, 26 Oct 2022 09:16:30 -0500 Message-Id: <20221026141631.696863-5-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026141631.696863-1-dinguyen@kernel.org> References: <20221026141631.696863-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747760115128631228?= X-GMAIL-MSGID: =?utf-8?q?1747760115128631228?= Now that the SDMMC driver supports setting the clk-phase, we can remove the need to do it in the clock driver. Signed-off-by: Dinh Nguyen Acked-by: Stephen Boyd --- v6: remove unused clk_phase in clk-gate.c v5: new --- drivers/clk/socfpga/clk-gate-a10.c | 68 ------------------------------ drivers/clk/socfpga/clk-gate.c | 61 --------------------------- drivers/clk/socfpga/clk.h | 1 - 3 files changed, 130 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index 738c53391e39..7cdf2f07c79b 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -35,59 +35,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk, return parent_rate / div; } -static int socfpga_clk_prepare(struct clk_hw *hwclk) -{ - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); - int i; - u32 hs_timing; - u32 clk_phase[2]; - - if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { - for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { - switch (socfpgaclk->clk_phase[i]) { - case 0: - clk_phase[i] = 0; - break; - case 45: - clk_phase[i] = 1; - break; - case 90: - clk_phase[i] = 2; - break; - case 135: - clk_phase[i] = 3; - break; - case 180: - clk_phase[i] = 4; - break; - case 225: - clk_phase[i] = 5; - break; - case 270: - clk_phase[i] = 6; - break; - case 315: - clk_phase[i] = 7; - break; - default: - clk_phase[i] = 0; - break; - } - } - - hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]); - if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) - regmap_write(socfpgaclk->sys_mgr_base_addr, - SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing); - else - pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n", - __func__); - } - return 0; -} - static struct clk_ops gateclk_ops = { - .prepare = socfpga_clk_prepare, .recalc_rate = socfpga_gate_clk_recalc_rate, }; @@ -96,7 +44,6 @@ static void __init __socfpga_gate_init(struct device_node *node, { u32 clk_gate[2]; u32 div_reg[3]; - u32 clk_phase[2]; u32 fixed_div; struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; @@ -136,21 +83,6 @@ static void __init __socfpga_gate_init(struct device_node *node, socfpga_clk->div_reg = NULL; } - rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); - if (!rc) { - socfpga_clk->clk_phase[0] = clk_phase[0]; - socfpga_clk->clk_phase[1] = clk_phase[1]; - - socfpga_clk->sys_mgr_base_addr = - syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) { - pr_err("%s: failed to find altr,sys-mgr regmap!\n", - __func__); - kfree(socfpga_clk); - return; - } - } - of_property_read_string(node, "clock-output-names", &clk_name); init.name = clk_name; diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 53d6e3ec4309..3e347b9e9eff 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -108,61 +108,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, return parent_rate / div; } -static int socfpga_clk_prepare(struct clk_hw *hwclk) -{ - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); - struct regmap *sys_mgr_base_addr; - int i; - u32 hs_timing; - u32 clk_phase[2]; - - if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { - sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(sys_mgr_base_addr)) { - pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); - return -EINVAL; - } - - for (i = 0; i < 2; i++) { - switch (socfpgaclk->clk_phase[i]) { - case 0: - clk_phase[i] = 0; - break; - case 45: - clk_phase[i] = 1; - break; - case 90: - clk_phase[i] = 2; - break; - case 135: - clk_phase[i] = 3; - break; - case 180: - clk_phase[i] = 4; - break; - case 225: - clk_phase[i] = 5; - break; - case 270: - clk_phase[i] = 6; - break; - case 315: - clk_phase[i] = 7; - break; - default: - clk_phase[i] = 0; - break; - } - } - hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); - regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET, - hs_timing); - } - return 0; -} - static struct clk_ops gateclk_ops = { - .prepare = socfpga_clk_prepare, .recalc_rate = socfpga_clk_recalc_rate, .get_parent = socfpga_clk_get_parent, .set_parent = socfpga_clk_set_parent, @@ -172,7 +118,6 @@ void __init socfpga_gate_init(struct device_node *node) { u32 clk_gate[2]; u32 div_reg[3]; - u32 clk_phase[2]; u32 fixed_div; struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; @@ -218,12 +163,6 @@ void __init socfpga_gate_init(struct device_node *node) socfpga_clk->div_reg = NULL; } - rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); - if (!rc) { - socfpga_clk->clk_phase[0] = clk_phase[0]; - socfpga_clk->clk_phase[1] = clk_phase[1]; - } - of_property_read_string(node, "clock-output-names", &clk_name); init.name = clk_name; diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index d80115fbdd6a..9a2fb2dde5b8 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -50,7 +50,6 @@ struct socfpga_gate_clk { u32 width; /* only valid if div_reg != 0 */ u32 shift; /* only valid if div_reg != 0 */ u32 bypass_shift; /* only valid if bypass_reg != 0 */ - u32 clk_phase[2]; }; struct socfpga_periph_clk { From patchwork Wed Oct 26 14:16:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11294 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp295831wru; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m11-20020a170902bb8b00b00176db576db9si6235492pls.275.2022.10.26.07.19.42; Wed, 26 Oct 2022 07:19:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=KPtsDd4p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234215AbiJZORK (ORCPT + 99 others); Wed, 26 Oct 2022 10:17:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234231AbiJZOQy (ORCPT ); Wed, 26 Oct 2022 10:16:54 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4972910F89F; Wed, 26 Oct 2022 07:16:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 00932B822B3; Wed, 26 Oct 2022 14:16:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 92519C43141; Wed, 26 Oct 2022 14:16:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666793809; bh=g/TFpBgxMMZqURiLLWUGN40leXx3CKJGLqcUxhIb9O8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KPtsDd4pw0/CTvV7jbKIiAIVPMA0P47HPqLp7hxifJy8HStyY2YRHqPh2uNUQD3P1 FnOehrCj7USbQ+uFtkxFMTHPyxpZWHQwzpYWEedebmByviObeXisSBCtzENfPt9Qm5 DlTWDYCOZvLP95xLk2rwNEczaxJPdZZLBD1FZS7eunwOdHPi/KMXBsMo5a/epjneSP Y7an2IoAMm0+vR4SQ62nu0+jChrOk+529eu0bQHPBtOeuzdaG23ViqYqQAp9OUTBc9 A54fCkW9o2t3VquDnJyj5gbNvRrfjb+vNSeWnNpQQKmQBRLgib5b2MpRK64SxkrpG7 8Pcjk5OsX3P5Q== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv6 6/6] arm: dts: socfpga: remove "clk-phase" in sdmmc_clk Date: Wed, 26 Oct 2022 09:16:31 -0500 Message-Id: <20221026141631.696863-6-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026141631.696863-1-dinguyen@kernel.org> References: <20221026141631.696863-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747760182467389204?= X-GMAIL-MSGID: =?utf-8?q?1747760182467389204?= Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't need the clk-phase in the sdmmc_clk anymore. Signed-off-by: Dinh Nguyen --- v6: no changes v5: new --- arch/arm/boot/dts/socfpga.dtsi | 1 - arch/arm/boot/dts/socfpga_arria10.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 604fc6e0c4ad..a2419a5c6c26 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -453,7 +453,6 @@ sdmmc_clk: sdmmc_clk { compatible = "altr,socfpga-gate-clk"; clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; clk-gate = <0xa0 8>; - clk-phase = <0 135>; }; sdmmc_clk_divided: sdmmc_clk_divided { diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index b6ebe207e2bc..eb528c103d70 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -365,7 +365,6 @@ sdmmc_clk: sdmmc_clk { compatible = "altr,socfpga-a10-gate-clk"; clocks = <&sdmmc_free_clk>; clk-gate = <0xC8 5>; - clk-phase = <0 135>; }; qspi_clk: qspi_clk {