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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z130-20020a633388000000b0053f4a727d96si2436523pgz.717.2023.06.01.02.41.44; Thu, 01 Jun 2023 02:41:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hjueGzHB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232617AbjFAJim (ORCPT + 99 others); Thu, 1 Jun 2023 05:38:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231995AbjFAJik (ORCPT ); Thu, 1 Jun 2023 05:38:40 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C97CF2; Thu, 1 Jun 2023 02:38:37 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3519cUnv026858; Thu, 1 Jun 2023 04:38:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685612310; bh=h3PdSyqSDpxSmvPFWLWZ6ObQIDZ1OIFUgqBWLd29Q2E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hjueGzHBCYe0PlQxoPQ/R/lKKsYDPjbwqxANPOGOwcOIiFYLnAIxZcguMVl4T014I 7by0Ql/OSvAyT04O03zyIRWcQKusbktEzir5+uWs4xNkDzKRL5Jprloj9/KurZVtku pPz3Zq0ElRsw3L6dh74jh7rOKQKNA0bUWgytVjBo= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3519cUnH012109 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 Jun 2023 04:38:30 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 04:38:30 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 04:38:30 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3519cNqT072495; Thu, 1 Jun 2023 04:38:27 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar Subject: [PATCH v2 1/5] arm64: dts: ti: k3-j7200: Add general purpose timers Date: Thu, 1 Jun 2023 15:07:40 +0530 Message-ID: <20230601093744.1565802-2-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230601093744.1565802-1-u-kumar1@ti.com> References: <20230601093744.1565802-1-u-kumar1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767492831984607162?= X-GMAIL-MSGID: =?utf-8?q?1767492831984607162?= There are 20 general purpose timers on j721e that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. The odd numbered timers have the option of being cascaded to even timers to create a 64 bit non-atomic counter which is racy in simple usage, hence the clock muxes are explicitly setup to individual 32 bit counters driven off system crystal (HFOSC) as default. Signed-off-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 240 ++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 130 ++++++++++ 2 files changed, 370 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index ef352e32f19d..c6b15aceea82 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -971,6 +971,246 @@ watchdog1: watchdog@2210000 { assigned-clock-parents = <&k3_clks 253 5>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 49 1>; + assigned-clock-parents = <&k3_clks 49 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; + assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 51 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 51 1>; + assigned-clock-parents = <&k3_clks 51 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 52 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; + assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 53 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 53 1>; + assigned-clock-parents = <&k3_clks 53 2>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 54 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; + assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 55 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 55 1>; + assigned-clock-parents = <&k3_clks 55 2>; + power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 57 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; + assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 58 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 58 1>; + assigned-clock-parents = <&k3_clks 58 2>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 59 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; + assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 60 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 60 1>; + assigned-clock-parents = <&k3_clks 60 2>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 62 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; + assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; + assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; + assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; + assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; + assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_r5fss0: r5fss@5c00000 { compatible = "ti,j7200-r5fss"; ti,cluster-mode = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 674e695ef844..dcb6696cff17 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -34,6 +34,136 @@ k3_reset: reset-controller { }; }; + mcu_timer0: timer@40400000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer1: timer@40410000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; + assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer2: timer@40420000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer3: timer@40430000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; + assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer4: timer@40440000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer5: timer@40450000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; + assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer6: timer@40460000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer7: timer@40470000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; + assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer8: timer@40480000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer9: timer@40490000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; + assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + mcu_conf: syscon@40f00000 { compatible = "syscon", "simple-mfd"; reg = <0x00 0x40f00000 0x00 0x20000>; From patchwork Thu Jun 1 09:37:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 101834 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp171559vqr; Thu, 1 Jun 2023 02:42:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4L8WWY56yLGTTj3jNQeGKzWiUWNz8iepKyZEp1M2tG5rWHgL9cYDWfSHj3EK43bNHfPdEm X-Received: by 2002:a05:6358:7208:b0:123:57ad:62b6 with SMTP id h8-20020a056358720800b0012357ad62b6mr7000925rwa.0.1685612566111; Thu, 01 Jun 2023 02:42:46 -0700 (PDT) ARC-Seal: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id lw17-20020a17090b181100b0025652802e12si816057pjb.175.2023.06.01.02.42.32; Thu, 01 Jun 2023 02:42:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=npV0p7iH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232900AbjFAJi5 (ORCPT + 99 others); Thu, 1 Jun 2023 05:38:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232891AbjFAJix (ORCPT ); Thu, 1 Jun 2023 05:38:53 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93921193; Thu, 1 Jun 2023 02:38:48 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3519cYtR102210; Thu, 1 Jun 2023 04:38:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685612314; bh=dzR/M89RZSFt3KI0fZN4F/Ibnuh5m91ANq22uH4vIAY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=npV0p7iHHf6PIUqZKgXRW1bcua1urrppso4+nk5Mddxow0PUiWBMwb9xATX03C3DD ifz5cgzxAoZQOeKr/xVpWvLrSabiNICkTzGAsj+9yKUbANc4zssXXLiPtfOXNZ9rOb 2ifdCeJsO4h3rYPKbif3X0Tcar94W/mxs/1p/IZc= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3519cYvW040582 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 Jun 2023 04:38:34 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 04:38:34 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 04:38:34 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3519cNqU072495; Thu, 1 Jun 2023 04:38:30 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar , Tony Lindgren Subject: [PATCH v2 2/5] arm64: dts: ti: k3-j7200: Configure pinctrl for timer IO pads Date: Thu, 1 Jun 2023 15:07:41 +0530 Message-ID: <20230601093744.1565802-3-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230601093744.1565802-1-u-kumar1@ti.com> References: <20230601093744.1565802-1-u-kumar1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767492882207198258?= X-GMAIL-MSGID: =?utf-8?q?1767492882207198258?= There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. The MCU timer controls are also marked as reserved for usage by the MCU firmware. Cc: Nishanth Menon Cc: Vignesh Raghavendra Cc: Tony Lindgren Signed-off-by: Udit Kumar Reviewed-by: Tony Lindgren --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 18 +++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 20 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index c6b15aceea82..a9b3bf8a5c6a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -392,6 +392,24 @@ cpts@3d000 { }; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x0 0x104200 0x0 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000001ff>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x0 0x104280 0x0 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index dcb6696cff17..b518ec9eea32 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -183,6 +183,26 @@ chipid@43000014 { reg = <0x00 0x43000014 0x00 0x4>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04200 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04280 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ From patchwork Thu Jun 1 09:37:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 101835 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp171653vqr; Thu, 1 Jun 2023 02:42:56 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5xcnrTkBgMAzLQ4ZYNNbxW7UEhIvZrhb8lNt4HyAVylNg2Sehd1Y5iVeoPRGDg8vz/weww X-Received: by 2002:a05:6a20:c702:b0:106:3b67:b5db with SMTP id hi2-20020a056a20c70200b001063b67b5dbmr5832538pzb.18.1685612576182; Thu, 01 Jun 2023 02:42:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685612576; cv=none; d=google.com; s=arc-20160816; b=e8LwNEtTa/e76SaBPCi8608UhEkVgJTDzs1MtgItGuolKI0lKnThIOuxlZ5kBauqXU OEZaSI5bVr/IDtK0Nz5jxSPbrAUpJ/2ziVG7UNZnGwRqBDKf4/bQfhanNqKk/W6hgQEU qDYilAUM/PyP9rcEegoVG3AmpfjaUjx7iQrtWu+curkBK4ul94E+0oJcH5cSSW0ZWaXm CxGBJMXtRPl+2LA3MLyl1AmNNbE0Tz/a/MVr30bKM3zumFGj0HlAR0pxfp/fW9m94CIc MZaeP2Xl5umGwONTJQUHfqDgfd4UMYVsF2CjAaCRqtyBFzJZTKOJDGDjaMDED2e9bsOG gCIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4BRSb3rd3F9dj/PuZiosOk0R6+mUWSddKQ8mwvmUAl4=; b=vu1omsMQQQM1DnblJ+Q9L6OI2cdbXETEktJ9EkhyXAV2CDvCLlukZBev34molZbZQC zy3Swq7YWm8e6myVl/jNQq6DGMTU+lpFxu+ksaFBxyfG/rEni9jRHDgkKpFcHaQGXToy PfxIrf7y8OxCHWyM1d9pMk+BH8Goe02kSJvtalRiO6p+HznJNhdOxchRokINwZDTjl9G WcbKAAz9a9mtPRkv7R/N8/iHtG7SExs3Ywx9VM0r9p1MqwmcYinvwCMN0KNkyj+6fY2P BiW/edydk91WYzqBqErE5i2uGrkoXWEREWr6LTbV16uGhYCYzJkE0K+S6HF2nt5/peEB KZjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fqGQKmub; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Thu, 1 Jun 2023 04:38:37 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3519cNqV072495; Thu, 1 Jun 2023 04:38:34 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar Subject: [PATCH v2 3/5] arm64: dts: ti: k3-j7200-common-proc-board: main_pmx0 clean up Date: Thu, 1 Jun 2023 15:07:42 +0530 Message-ID: <20230601093744.1565802-4-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230601093744.1565802-1-u-kumar1@ti.com> References: <20230601093744.1565802-1-u-kumar1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767492892364530775?= X-GMAIL-MSGID: =?utf-8?q?1767492892364530775?= Add main_uart0 pin mux in board common file Signed-off-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 0cc0e1dc40c5..02d2e4b36b18 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -113,6 +113,15 @@ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ >; }; + main_uart0_pins_default: main_uart0_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ + J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ + J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ + J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ @@ -162,6 +171,8 @@ &main_uart0 { status = "okay"; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; }; &main_uart1 { From patchwork Thu Jun 1 09:37:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 101837 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp176651vqr; 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So removing duplicated node from common file Signed-off-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 02d2e4b36b18..e12d93f56c51 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -106,13 +106,6 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; - main_uart0_pins_default: main_uart0_pins_default { pinctrl-single,pins = < J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ From patchwork Thu Jun 1 09:37:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 101836 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp175532vqr; Thu, 1 Jun 2023 02:50:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5as0zT6oJ0JxFslE7tUzJpmyD+Ic/RH7J4sbWzNhuth58ScAe7xv2ghs61/w/98/OV+K5i X-Received: by 2002:a17:902:e54e:b0:1b1:8ca9:10ca with SMTP id n14-20020a170902e54e00b001b18ca910camr1387934plf.33.1685613045765; Thu, 01 Jun 2023 02:50:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685613045; cv=none; d=google.com; s=arc-20160816; b=Ms4PMThzL2PST7nMTpr21aI+/UqXhi7Q/LOA/ZcwcRmCnqcuaToE2Y0LSBalSTGldX +ZMTzYpXsS9H9+kBWcxlVoUIJSd9CD7m0E1WjdZ6+DfuD2322BgCODzJaNSMCm7DVYSu a+znG6qwJVeB2KlACXUgL0I75XlXN9m3xEAqKeAZovA2tGRawefvSaERSvIWBcbRS43h ajGUc46R82IZfp2EaXGTBO3a2ZTSWy1UiZgaC1j9bFs6m/QkiQA/eF2lsvlunGId7fBy n93Ql1w0MX0qX4DYUlO+U5OLLqOJQnh1hCXMC6WttIkaT9tFJagtngemmixUyQ1oEc7H /hFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mUPXXCSkpwsEOqke/okB5aqGoM+uGctd5B5F0mRWei8=; b=SGIC/UfYHGTyFmEf/Zcz9Ai0B+P1Efj+H/6oBoEL5u1dyrE6z4lS+Mg5qzOaPembeS 9yLieujOpSDaozGx7hswyPu8gAzGBgKiw1JQQ9Z/SpOBvAObuYIojcyKwWKUc0b8hb30 qoAx8SoVKy9Dla3ZpiVv0o41rzI3I0fdpexrIuaDIXKxKtYuznPfuIqsI9VYgevumInj Kkk/5iyTTC9O7dFuGi13p3efj+lsexIv+NahZL1OWMu7lDhdYH5uZAb9srfd4m4qqtEU dLZvg0kIS9+QQNXhHzNfr7iq7oDL41A9HVJEqUr++8e29UzHbaMZeyQmfHrmor7fGpDq irqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZVJ0Tpe7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l5-20020a170903244500b001ae3fa8de08si1167097pls.576.2023.06.01.02.50.34; Thu, 01 Jun 2023 02:50:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZVJ0Tpe7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232929AbjFAJjI (ORCPT + 99 others); Thu, 1 Jun 2023 05:39:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232912AbjFAJiy (ORCPT ); Thu, 1 Jun 2023 05:38:54 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F008819F; Thu, 1 Jun 2023 02:38:50 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3519ci8d102239; Thu, 1 Jun 2023 04:38:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685612324; bh=mUPXXCSkpwsEOqke/okB5aqGoM+uGctd5B5F0mRWei8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZVJ0Tpe7DBsJ/0spJXODVOIuhYpjKy/XP0qFsE5q4iVShgvQpStyxGGCKfSo8mSWQ 69OWs6GruXdD3eIifXQHSiB52s7i1YefyuLhe6cEtOKotHmupxibJkQ2ua3uO56rF3 nTiKMHdWot0wCvZmc5f76z9iwr6tU/BztbXkS//s= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3519civG012203 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 Jun 2023 04:38:44 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 04:38:44 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 04:38:44 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3519cNqX072495; Thu, 1 Jun 2023 04:38:41 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar Subject: [PATCH v2 5/5] arm64: dts: ti: k3-j7200-common-proc-board: Add uart pin mux in wkup_pmx0 Date: Thu, 1 Jun 2023 15:07:44 +0530 Message-ID: <20230601093744.1565802-6-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230601093744.1565802-1-u-kumar1@ti.com> References: <20230601093744.1565802-1-u-kumar1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767493385068460367?= X-GMAIL-MSGID: =?utf-8?q?1767493385068460367?= Add uart pin mux of wkup domain into common board file. Signed-off-by: Udit Kumar --- .../dts/ti/k3-j7200-common-proc-board.dts | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index e12d93f56c51..809d1c910015 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -79,6 +79,24 @@ vdd_sd_dv: gpio-regulator-TLV71033 { }; }; +&wkup_pmx0 { + mcu_uart0_pins_default: mcu_uart0_pins_default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ + J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + >; + }; + + wkup_uart0_pins_default: wkup_uart0_pins_default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + >; + }; +}; + &wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < @@ -157,7 +175,9 @@ &wkup_uart0 { &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + clock-frequency = <96000000>; }; &main_uart0 {