From patchwork Thu Jun 1 08:51:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 101808 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp149393vqr; Thu, 1 Jun 2023 01:57:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7HexcMFuey+hlzYsNzdmApYIDtE1Cx79UoEmWgZsh90khfCC7jx3xYPQQS/YO4HmIt1U9q X-Received: by 2002:a05:6a20:7347:b0:104:7454:d858 with SMTP id v7-20020a056a20734700b001047454d858mr1454546pzc.19.1685609873477; Thu, 01 Jun 2023 01:57:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685609873; cv=none; d=google.com; s=arc-20160816; b=E0HDQ8mVrSOjK7GdvBJnnQnuPN7leMUz99AJ9bRKtt66H29v4lVdDBWf7caxBcy2aj 0GT2Fa4d/LymQwrTwGsAzMmsgvROy9bEvNpDhtmkX4oD/4gu+H1nhknABVMA6y+EbyN1 KP9eesbgtf+TsxGcvH3KbCdBjHeoOSYNV4rhy+Aa2nPxxKRzeWN1NDp/8XiPTksOwNRe wMP/T46Qs1nmtzCzV9O6aOq9IOC5nNGr2eo6e1p0Q9GqTXA1VNzRfyno+hE2/bIOOYoa Ks6lSPhErLJt+yqubwfgVSO+ugk6h3u7p7Xd4WbpqbGCXQCVjI0/gBnXuTbHNer/z7+c iv0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=tZB1Gpl6nVRZRmMpfmbs0mFiZCBVmuVfTXoMiXC2tgw=; b=qAhlmOkg7T10SSXS9uTzSmNVtcIE2kMYUTM4N90rvSv19YZxtVbkPgAi7qctrb5jm/ zPxEFkF8d/W4fVI8hqxh56xtSK17ZDQ9uiPwCc1lfbKIJYooEuOB/kPjOK0feA32bc2B +1+FhJNXEpJT5ZsGM6E5fhpHtZp/nqCP52Y5tSiZVRw1cqh0Qc40uFcvPCZkenOazJVv jRvhrlQbzSNaYLJkC9jmUDv7ZOlsEn787VUNSNZbHjjlJONgjEBVFABELqDhO/qLsOUB Z/PfUq0WcKSHLnKtk+SlsVnEdyrHaus+DaNyrnzGIcHlh1LKndXqxVcOq6m+Cupn3clZ fjmg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b27-20020a63931b000000b0053f1387ecfcsi1216474pge.356.2023.06.01.01.57.40; Thu, 01 Jun 2023 01:57:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232366AbjFAIwF convert rfc822-to-8bit (ORCPT + 99 others); Thu, 1 Jun 2023 04:52:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232070AbjFAIwD (ORCPT ); Thu, 1 Jun 2023 04:52:03 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AFC7132; Thu, 1 Jun 2023 01:51:59 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id EA52D7FC9; Thu, 1 Jun 2023 16:51:56 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 1 Jun 2023 16:51:56 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 1 Jun 2023 16:51:56 +0800 From: William Qiu To: , , , CC: Thierry Reding , Philipp Zabel , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Emil Renner Berthing , Hal Feng , William Qiu Subject: [PATCH v4 1/4] dt-bindings: pwm: Add StarFive PWM module Date: Thu, 1 Jun 2023 16:51:51 +0800 Message-ID: <20230601085154.36938-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230601085154.36938-1-william.qiu@starfivetech.com> References: <20230601085154.36938-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767490058736817105?= X-GMAIL-MSGID: =?utf-8?q?1767490058736817105?= Add documentation to describe StarFive Pulse Width Modulation controller driver. Signed-off-by: William Qiu Reviewed-by: Krzysztof Kozlowski Reviewed-by: Hal Feng --- .../bindings/pwm/starfive,jh7100-pwm.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml new file mode 100644 index 000000000000..6f1937beb962 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/starfive,jh7100-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 and JH7110 PWM controller + +maintainers: + - William Qiu + +description: + StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates + binary signal with user-programmable low and high periods. Clock source for the + PWM can be either system clock or external clock. Each PWM timer block provides 8 + PWM channels. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - starfive,jh7100-pwm + - starfive,jh7110-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible = "starfive,jh7100-pwm"; + reg = <0x12490000 0x10000>; + clocks = <&clkgen 181>; + resets = <&rstgen 109>; + #pwm-cells = <3>; + }; From patchwork Thu Jun 1 08:51:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 101810 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp155720vqr; Thu, 1 Jun 2023 02:08:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4zNoz1cVGO9hpjcTyrErtguRiPqgCfReommjSgpideIwwmbU7VDeFQq8wCoMkVd3HWojsZ X-Received: by 2002:a05:6358:52d3:b0:122:7f7f:7995 with SMTP id z19-20020a05635852d300b001227f7f7995mr3148498rwz.19.1685610533544; Thu, 01 Jun 2023 02:08:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685610533; cv=none; d=google.com; s=arc-20160816; b=KRpvOo8NbJKyJ3wFrZTinzX4QAIqzqGVAO2O7gD+NGC2XIajSDVV92e8YbQQKVJci1 DDBWDg9FpzZ9EJJPMu+ikCufohBLQ19FK3clcz3HlwAGjHtQnMIRzWK/Q9ux3tI75lur F1GAOMsQc0YpyQFt8VRX9xDEfWPH6D2PHOcaf4+9MGiooWMXVW50anvBquUttdbUU/Jd elTLfuiGoFS6nRA52HFe/9vpsDkZrnEsFrlSJQjfM6fsuj4riCylKpWUaPxgha99wM6W Q/FLJbGuTVWwTlvO552nKvm+c7T40OBi8akQYUuFDxNYoob1shHmZEqeYUn1S2ECwyt/ Q7UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=0yhvKY/Q1l14Y6gVrqncKiL5nZx/Dw4a/GE548vuRZg=; b=z76qRg7EE3dDqIRhIGXgaQmFA1CJ5jqUo3rPGUtLjv9RIIXhacmaBEzj+yZa9Pyo7y XjuTqiigmxHlzg7bTSRUQOd+sxyYtN3EiFJD4h84c/AXgnDhjNSeYynfEkGXANMqHvu2 d3kQJZ/VO7e0WQrhpYK9LOfy4VPumbAHuSVz4Xv0rZVQr78vSAhbg/tMNj31iNyTYskL mCH+gH8OrwreCHY9srPwfn0IJjdWAekPI085SOhlN3d+vQwebvOYSXeGda0XWb4VNqXs h6BraoQuth4HcBNnWZix96EYcGMDW5ZCxeXibSUB12QAwoBibwhjw55HHvvRxgZZL1i1 eLWg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a26-20020a63705a000000b005411b1a148esi120981pgn.498.2023.06.01.02.08.38; Thu, 01 Jun 2023 02:08:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232097AbjFAIwT convert rfc822-to-8bit (ORCPT + 99 others); Thu, 1 Jun 2023 04:52:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232375AbjFAIwH (ORCPT ); Thu, 1 Jun 2023 04:52:07 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4618F129; Thu, 1 Jun 2023 01:52:04 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 9CE0124E255; Thu, 1 Jun 2023 16:51:57 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 1 Jun 2023 16:51:57 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 1 Jun 2023 16:51:56 +0800 From: William Qiu To: , , , CC: Thierry Reding , Philipp Zabel , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Emil Renner Berthing , Hal Feng , William Qiu Subject: [PATCH v4 2/4] pwm: starfive: Add PWM driver support Date: Thu, 1 Jun 2023 16:51:52 +0800 Message-ID: <20230601085154.36938-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230601085154.36938-1-william.qiu@starfivetech.com> References: <20230601085154.36938-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767490751166234987?= X-GMAIL-MSGID: =?utf-8?q?1767490751166234987?= Add Pulse Width Modulation driver support for StarFive JH7100 and JH7110 SoC. Co-developed-by: Hal Feng Signed-off-by: Hal Feng Signed-off-by: William Qiu --- MAINTAINERS | 7 ++ drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-starfive-ptc.c | 192 +++++++++++++++++++++++++++++++++ 4 files changed, 209 insertions(+) create mode 100644 drivers/pwm/pwm-starfive-ptc.c diff --git a/MAINTAINERS b/MAINTAINERS index 27ef11624748..34d69e9ce444 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20112,6 +20112,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71* F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h +STARFIVE JH71X0 PWM DRIVERS +M: William Qiu +M: Hal Feng +S: Supported +F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml +F: drivers/pwm/pwm-starfive-ptc.c + STARFIVE JH71X0 RESET CONTROLLER DRIVERS M: Emil Renner Berthing M: Hal Feng diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8df861b1f4a3..df2bc4ce3f1f 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -548,6 +548,15 @@ config PWM_SPRD To compile this driver as a module, choose M here: the module will be called pwm-sprd. +config PWM_STARFIVE_PTC + tristate "StarFive PWM PTC support" + depends on ARCH_STARFIVE || COMPILE_TEST + help + Generic PWM framework driver for StarFive SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-starfive-ptc. + config PWM_STI tristate "STiH4xx PWM support" depends on ARCH_STI || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 19899b912e00..994104aaa9b4 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o +obj-$(CONFIG_PWM_STARFIVE_PTC) += pwm-starfive-ptc.o obj-$(CONFIG_PWM_STI) += pwm-sti.o obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o diff --git a/drivers/pwm/pwm-starfive-ptc.c b/drivers/pwm/pwm-starfive-ptc.c new file mode 100644 index 000000000000..57b5736f6732 --- /dev/null +++ b/drivers/pwm/pwm-starfive-ptc.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PWM driver for the StarFive JH71x0 SoC + * + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Access PTC register (CNTR, HRC, LRC and CTRL) */ +#define REG_PTC_BASE_ADDR_SUB(base, N) \ +((base) + (((N) > 3) ? (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10))) +#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N)) +#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4) +#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8) +#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC) + +/* PTC_RPTC_CTRL register bits*/ +#define PTC_EN BIT(0) +#define PTC_ECLK BIT(1) +#define PTC_NEC BIT(2) +#define PTC_OE BIT(3) +#define PTC_SIGNLE BIT(4) +#define PTC_INTE BIT(5) +#define PTC_INT BIT(6) +#define PTC_CNTRRST BIT(7) +#define PTC_CAPTE BIT(8) + +struct starfive_pwm_ptc_device { + struct pwm_chip chip; + struct clk *clk; + struct reset_control *rst; + void __iomem *regs; + u32 clk_rate; /* PWM APB clock frequency */ +}; + +static inline +struct starfive_pwm_ptc_device *chip_to_starfive_ptc(struct pwm_chip *c) +{ + return container_of(c, struct starfive_pwm_ptc_device, chip); +} + +static int starfive_pwm_ptc_get_state(struct pwm_chip *chip, + struct pwm_device *dev, + struct pwm_state *state) +{ + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip); + u32 period_data, duty_data, ctrl_data; + + period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm)); + duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm)); + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); + + state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate); + state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate); + state->polarity = PWM_POLARITY_INVERSED; + state->enabled = (ctrl_data & PTC_EN) ? true : false; + + return 0; +} + +static int starfive_pwm_ptc_apply(struct pwm_chip *chip, + struct pwm_device *dev, + const struct pwm_state *state) +{ + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip); + u32 period_data, duty_data, ctrl_data = 0; + + if (state->polarity != PWM_POLARITY_INVERSED) + return -EINVAL; + + period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate, + NSEC_PER_SEC); + duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate, + NSEC_PER_SEC); + + writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm)); + writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm)); + writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm)); + + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); + if (state->enabled) + writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); + else + writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); + + return 0; +} + +static const struct pwm_ops starfive_pwm_ptc_ops = { + .get_state = starfive_pwm_ptc_get_state, + .apply = starfive_pwm_ptc_apply, + .owner = THIS_MODULE, +}; + +static int starfive_pwm_ptc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct starfive_pwm_ptc_device *pwm; + struct pwm_chip *chip; + int ret; + + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + chip = &pwm->chip; + chip->dev = dev; + chip->ops = &starfive_pwm_ptc_ops; + chip->npwm = 8; + chip->of_pwm_n_cells = 3; + + pwm->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->regs)) + return dev_err_probe(dev, PTR_ERR(pwm->regs), + "Unable to map IO resources\n"); + + pwm->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), + "Unable to get pwm's clock\n"); + + pwm->rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(pwm->rst)) + return dev_err_probe(dev, PTR_ERR(pwm->rst), + "Unable to get pwm's reset\n"); + + ret = clk_prepare_enable(pwm->clk); + if (ret) { + dev_err(dev, + "Failed to enable clock for pwm: %d\n", ret); + return ret; + } + + reset_control_deassert(pwm->rst); + + pwm->clk_rate = clk_get_rate(pwm->clk); + if (pwm->clk_rate <= 0) { + dev_warn(dev, "Failed to get APB clock rate\n"); + return -EINVAL; + } + + ret = devm_pwmchip_add(dev, chip); + if (ret < 0) { + dev_err(dev, "Cannot register PTC: %d\n", ret); + clk_disable_unprepare(pwm->clk); + reset_control_assert(pwm->rst); + return ret; + } + + platform_set_drvdata(pdev, pwm); + + return 0; +} + +static int starfive_pwm_ptc_remove(struct platform_device *dev) +{ + struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev); + + reset_control_assert(pwm->rst); + clk_disable_unprepare(pwm->clk); + + return 0; +} + +static const struct of_device_id starfive_pwm_ptc_of_match[] = { + { .compatible = "starfive,jh7100-pwm" }, + { .compatible = "starfive,jh7110-pwm" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match); + +static struct platform_driver starfive_pwm_ptc_driver = { + .probe = starfive_pwm_ptc_probe, + .remove = starfive_pwm_ptc_remove, + .driver = { + .name = "pwm-starfive-ptc", + .of_match_table = starfive_pwm_ptc_of_match, + }, +}; +module_platform_driver(starfive_pwm_ptc_driver); + +MODULE_AUTHOR("Jieqin Chen"); +MODULE_AUTHOR("Hal Feng "); +MODULE_DESCRIPTION("StarFive PWM PTC driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Jun 1 08:51:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 101824 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp159217vqr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j4-20020a170902c3c400b001b06f8ce437si2421527plj.70.2023.06.01.02.15.48; Thu, 01 Jun 2023 02:16:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232396AbjFAIwJ convert rfc822-to-8bit (ORCPT + 99 others); Thu, 1 Jun 2023 04:52:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231667AbjFAIwE (ORCPT ); Thu, 1 Jun 2023 04:52:04 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 153B713D; Thu, 1 Jun 2023 01:52:00 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 712BC7FD6; Thu, 1 Jun 2023 16:51:58 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 1 Jun 2023 16:51:58 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 1 Jun 2023 16:51:57 +0800 From: William Qiu To: , , , CC: Thierry Reding , Philipp Zabel , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Emil Renner Berthing , Hal Feng , William Qiu Subject: [PATCH v4 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration Date: Thu, 1 Jun 2023 16:51:53 +0800 Message-ID: <20230601085154.36938-4-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230601085154.36938-1-william.qiu@starfivetech.com> References: <20230601085154.36938-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767491198080104241?= X-GMAIL-MSGID: =?utf-8?q?1767491198080104241?= Add StarFive JH7110 PWM controller node and add PWM pins configuration on VisionFive 2 board. Reviewed-by: Hal Feng Signed-off-by: William Qiu --- .../jh7110-starfive-visionfive-2.dtsi | 22 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 2a6d81609284..bbc2531999bc 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -126,6 +126,12 @@ &i2c6 { status = "okay"; }; +&ptc { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins { @@ -183,6 +189,22 @@ GPOEN_SYS_I2C6_DATA, }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = , + ; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pinmux = ; + clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; + resets = <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + syscrg: clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x0 0x13020000 0x0 0x10000>; From patchwork Thu Jun 1 08:51:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 101821 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp158366vqr; Thu, 1 Jun 2023 02:14:27 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7IT7a9WwZ3xzLIPxMxAttukMxgPKXisX0OMqQjc5p1Y+E0CQPrLpu0Cv7bSaPVr9HCpf/A X-Received: by 2002:a54:4d84:0:b0:398:29bb:dd4a with SMTP id y4-20020a544d84000000b0039829bbdd4amr6194676oix.54.1685610867187; Thu, 01 Jun 2023 02:14:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685610867; cv=none; d=google.com; s=arc-20160816; b=Zkq/OvOWV8ujTY7fRmFm4lW5QIAcM/eXQSdVRHOW7Ef9gIbJVAWqCGELAJ8fYBvYPZ 4i/KdVfkuSSrSONxTX5a9kPnvy/x01w2z4WvisuV173gOb5cLkYfhnd7YOou2s4Gx3v7 6g+D9GEhA/f5fopzCRo/YHbXaQeG4cYBtZ6JEv95sf+9UCLe6Kne0xt/jYVBif71FfDp GN0eQ6KpSyWB9+XA5WUrO1X8+emK4c2N4Lj72cUgk1CrM+LtSdUnjINSemEcPMHFG7fl fZxNJnpjEgQrWgmpO/xeJ+UjmLfizE8eGktFNPAjRAyG+pGpqigXFq7SiWcA5O1QbLfI zedw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=pT/FBlP/klXQ3r3R9dePUEUhL6+9nhwI1UuKdOBA7Bg=; b=Z/DVYSFCEoflDXgXGCVcfAX+sQSGb91steqJKMsOtTbG36I6TLx5xPZ428Qv9hty1Y kouWWtYqJ8D0Vt2dRY6ay+KwO3wQxajcvNe7PUynVVNSF+wIFvnf4HvHcLT3tnYe5qSz ZubYVUrvGrVVsRT4sIC6V3I12/2Zg04W8iFztelteA4sDAjrdNyxjOn8me3CBTyUzzVf lXKGLO5/uIvXf4pBfAvflYh4GLRysFh/Xv2a/UaxoKkZxBg0WMiCpw4pMEDi8Ubod64b turUzeybvzErAU8S2/+UqgznO+Mw8skfTTS23MTGME35lyJNuWN8UqF0O8IaFUx99qxY XDfg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Hal Feng Signed-off-by: William Qiu --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++ 2 files changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..746867b882b0 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN, }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = , + ; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + uart3_pins: uart3-0 { rx-pins { pinmux = ; }; +&ptc { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 000447482aca..977a509ffbdd 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -238,5 +238,14 @@ i2c3: i2c@12460000 { #size-cells = <0>; status = "disabled"; }; + + ptc: pwm@12490000 { + compatible = "starfive,jh7100-pwm"; + reg = <0x0 0x12490000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_PWM_APB>; + resets = <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; }; };