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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id v25-20020a197419000000b004f019d3eab4sm756325lfe.23.2023.05.31.08.04.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 May 2023 08:04:30 -0700 (PDT) From: Konrad Dybcio Date: Wed, 31 May 2023 17:04:23 +0200 Subject: [PATCH 1/2] dt-bindings: arm-smmu: Add SM6375 GPU SMMU MIME-Version: 1.0 Message-Id: <20230531-topic-sm6375_gpusmmu-v1-1-860943894c71@linaro.org> References: <20230531-topic-sm6375_gpusmmu-v1-0-860943894c71@linaro.org> In-Reply-To: <20230531-topic-sm6375_gpusmmu-v1-0-860943894c71@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685545468; l=1196; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gJOlh+EMoLh8KOQ53iJ7hyFLc362lflmhqV5kwupSas=; b=XwOLMmcbcNw6AK7Mgvhj4n75W9cOGfnCWczMCWaASiSS8xGuTRrID/XD8y6uvnCtSaElXVUmf 0Guxw3Bd1nKAZP1Fh2z0QLkXI0IovjimDCL6++lgmi08X6H+GDD2kU7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767422742851400512?= X-GMAIL-MSGID: =?utf-8?q?1767422742851400512?= SM6375 has a "Qualcomm SMMU V2" implementation for its GPU SMMU. It does not however qualify for the qcom,adreno-smmu compatible, as it can not do split pagetables. It consumes a single clock and a single genpd. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index ba677d401e24..aec9137713c9 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -29,6 +29,7 @@ properties: - qcom,msm8996-smmu-v2 - qcom,msm8998-smmu-v2 - qcom,sdm630-smmu-v2 + - qcom,sm6375-smmu-v2 - const: qcom,smmu-v2 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" @@ -267,6 +268,7 @@ allOf: enum: - qcom,msm8998-smmu-v2 - qcom,sdm630-smmu-v2 + - qcom,sm6375-smmu-v2 then: anyOf: - properties: From patchwork Wed May 31 15:04:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 101510 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2956846vqr; Wed, 31 May 2023 08:16:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ50dexKTIlawVNvR7XzcZ/VoK/63hmJRHe7k3+QZjAeUjlRMPzaIZsjDV8/lp7jxvtXn9VX X-Received: by 2002:a17:902:e80f:b0:1b0:5e97:ee2c with SMTP id u15-20020a170902e80f00b001b05e97ee2cmr4960822plg.11.1685546209520; Wed, 31 May 2023 08:16:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685546209; cv=none; d=google.com; s=arc-20160816; b=Nt85dEXYnSwd57UtW5XRYPqYboRwGp6MGvnEPN6+dI1xAuPRKvOIBzu+rViX0rGXGy RXo5JqfRYz6950sv1dWRDOH2J39RtZUNIOE/9n5BWRLZyxfrzQ7+s5sq+ZinpGfbOP4E HUEZGn/3j8KzErL3yxPHLtM/la57QXHMhHhIKffCXFzw1e0ZY762y36fxZGaBjdfbled MD5/67VZSNiLK8zWslqinrPYw610Ao8yrDZmRmc52omI/PUZ42lViE+15IYxtlVt+/vb lU6txU/QGGuLzxeI0h586qcHW60nbxnV94xrfSAk+d3SZ/9LlBoShzTNfzxpxJHY4lxo pQEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=vBciu8IUz0vdlWcni9FF4uUhO0LU6XOb9eyf9C827Ho=; b=J0YHrvC0tPgDmvM86cgRa0KxdKO7u1yhzF7CuwL578WTq1zfpxcCgmSMZyQjZvt7Ct vJpeHflfn843j7ZfSiFb6TPL9eVhjpc6C4Jr/zmn1hlHkMiZz8kHJlP6bb/BNBou/HFq OZSLLmXliuwyMC2MGlAxLnDD93Ud5qaJy7hU6rX6VPkeGyvMp0mMlJOUMdqnaON2CVnE 12vJUw+6FuYMEh18xGjQbEfjEz1omupgWEghIsBnWVMK+GezfnNJBEU0LCwzkoFK4AYw F0Ep/tKyzOOVktbOLPBi4yu1xc7+DhTOrtp68UsjcrfAAXwg1FVM4Bt5omXRyUVwYTkS rn/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="F3/9fdJo"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id v25-20020a197419000000b004f019d3eab4sm756325lfe.23.2023.05.31.08.04.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 May 2023 08:04:31 -0700 (PDT) From: Konrad Dybcio Date: Wed, 31 May 2023 17:04:24 +0200 Subject: [PATCH 2/2] arm64: dts: qcom: sm6375: Add GPUCC and Adreno SMMU MIME-Version: 1.0 Message-Id: <20230531-topic-sm6375_gpusmmu-v1-2-860943894c71@linaro.org> References: <20230531-topic-sm6375_gpusmmu-v1-0-860943894c71@linaro.org> In-Reply-To: <20230531-topic-sm6375_gpusmmu-v1-0-860943894c71@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685545468; l=2217; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=0qRthIuQ5GXryV4KqwemAc1v1T13tS3GmpDq4wc4d9Q=; b=LQedeCbvmtolR0nCDOCffZcsRKQtljPkZB5M7fCUYyluIH+p/GHigxqARJSVI+tDv6kCeipth 0qk8Eb5tkoFA2Y3hkDRi5NZRoFvnNhwpNnUsNouaeXPj509BhPZnoES X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767423302199758379?= X-GMAIL-MSGID: =?utf-8?q?1767423302199758379?= Add GPUCC and Adreno SMMU nodes in preparation for adding the GPU itself. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index f8d9c34d3b2f..3dba34210a6d 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -1276,6 +1277,42 @@ usb_1_dwc3: usb@4e00000 { }; }; + adreno_smmu: iommu@5940000 { + compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x05940000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "bus"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gpucc: clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + power-domains = <&rpmpd SM6375_VDDGX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + remoteproc_mss: remoteproc@6000000 { compatible = "qcom,sm6375-mpss-pas"; reg = <0 0x06000000 0 0x4040>;