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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id t1-20020aa7d701000000b0050cff329d75si7315293edq.288.2023.05.30.23.58.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 23:58:58 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=uFfGdQjv; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2681E3858C5E for ; Wed, 31 May 2023 06:58:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2681E3858C5E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685516337; bh=5lMfi3w2WdvaJhGKeZlCp8shgF33jp3VsU02Pvuh/TU=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=uFfGdQjv3Uuj3O4sZihKOQdMBPDKY4MhRFoXFuns9inhP+x0m/k4EubRzdaHyPuFy C4v/x76zOF6sqqMIrPH3lqY8Y2RiLLx68fhKgI4qxygwGEFczsU9Hb07p7gmMZ0zH/ uhXzjQLrNykaTB1MaWH0IQYxV+qXVITonfz9zuq0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 8A4033858D37 for ; Wed, 31 May 2023 06:58:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8A4033858D37 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="420922226" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="420922226" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2023 23:58:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="771890261" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="771890261" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga008.fm.intel.com with ESMTP; 30 May 2023 23:58:08 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id BA46E1005622; Wed, 31 May 2023 14:58:07 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: Add ZVFH extension to the -march= option Date: Wed, 31 May 2023 14:58:06 +0800 Message-Id: <20230531065806.1822850-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767391980048621461?= X-GMAIL-MSGID: =?utf-8?q?1767391980048621461?= From: Pan Li This patch would like to add new sub extension (aka ZVFH) to the -march= option. To make it simple, only the sub extension itself is involved in this patch, and the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFH. The Zvfh extension depends on the Zve32f and Zfhmin extensions. You can locate more information about ZVFH from below spec doc. https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#185-zvfh-vector-extension-for-half-precision-floating-point Signed-off-by: Pan Li gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zvfh item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_ZVFH): New macro. (TARGET_ZVFH): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-21.c: New test. * gcc.target/riscv/predef-27.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 4 ++ gcc/config/riscv/riscv-opts.h | 2 + gcc/testsuite/gcc.target/riscv/arch-21.c | 5 ++ gcc/testsuite/gcc.target/riscv/predef-27.c | 55 ++++++++++++++++++++++ 4 files changed, 66 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-27.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 92edafb516d..e6ed3df9ea6 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -105,6 +105,8 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zfh", "zfhmin"}, {"zfhmin", "f"}, {"zvfhmin", "zve32f"}, + {"zvfh", "zve32f"}, + {"zvfh", "zfhmin"}, {"zhinx", "zhinxmin"}, {"zhinxmin", "zfinx"}, @@ -218,6 +220,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvfh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1262,6 +1265,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN}, {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH}, {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN}, + {"zvfh", &gcc_options::x_riscv_zf_subext, MASK_ZVFH}, {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index f34ca993689..5f387d0e393 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -201,10 +201,12 @@ enum riscv_entity #define MASK_ZFHMIN (1 << 0) #define MASK_ZFH (1 << 1) #define MASK_ZVFHMIN (1 << 2) +#define MASK_ZVFH (1 << 3) #define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0) #define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0) #define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0) +#define TARGET_ZVFH ((riscv_zf_subext & MASK_ZVFH) != 0) #define MASK_ZMMUL (1 << 0) #define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0) diff --git a/gcc/testsuite/gcc.target/riscv/arch-21.c b/gcc/testsuite/gcc.target/riscv/arch-21.c new file mode 100644 index 00000000000..8a239a9255c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-21.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gcv_zvfh -mabi=ilp32 -mcmodel=medlow" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-27.c b/gcc/testsuite/gcc.target/riscv/predef-27.c new file mode 100644 index 00000000000..0f9ab4417a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-27.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64i_zvfh -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_zvfh) +#error "__riscv_zvfh" +#endif + +#if !defined(__riscv_zfhmin) +#error "__riscv_zfhmin" +#endif + +#if defined(__riscv_zvfhmin) +#error "__riscv_zvfhmin" +#endif + +#if defined(__riscv_v) +#error "__riscv_v" +#endif + +#if defined(__riscv_d) +#error "__riscv_d" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + +#if defined(__riscv_zfh) +#error "__riscv_zfh" +#endif + + return 0; +}