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Wed, 31 May 2023 11:55:04 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 6F3C013EDD5; Wed, 31 May 2023 11:55:04 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 6DF1D280AFE; Wed, 31 May 2023 11:55:04 +1200 (NZST) From: Chris Packham To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, enachman@marvell.com, Vadym Kochan , Chris Packham Subject: [PATCH v7 1/4] arm64: dts: marvell: cp11x: Fix nand_controller node name according to YAML Date: Wed, 31 May 2023 11:54:53 +1200 Message-Id: <20230530235456.1009082-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530235456.1009082-1-chris.packham@alliedtelesis.co.nz> References: <20230530235456.1009082-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=cLieTWWN c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=P0xRbXHiH_UA:10 a=g8kJ_gb0AAAA:8 a=GKaKEI1dGHIjLaXU8GMA:9 a=ecSNLfPMzbq-p5zXJZOg:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767365479646063578?= X-GMAIL-MSGID: =?utf-8?q?1767365479646063578?= From: Vadym Kochan Marvell NAND controller has now YAML to validate it's DT bindings, so change the node name of cp11x DTSI as it is required by nand-controller.yaml Signed-off-by: Vadym Kochan Signed-off-by: Chris Packham Reviewed-by: Miquel Raynal --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 0cc9ee9871e7..4ec1aae0a3a9 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -468,7 +468,7 @@ CP11X_LABEL(uart3): serial@702300 { status = "disabled"; }; - CP11X_LABEL(nand_controller): nand@720000 { + CP11X_LABEL(nand_controller): nand-controller@720000 { /* * Due to the limitation of the pins available * this controller is only usable on the CPM From patchwork Tue May 30 23:54:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 101159 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2536608vqr; Tue, 30 May 2023 16:57:07 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6/2zLp3zsP89xlvjOGQ8Fx80fZ2JBFuOMzluhvsnLD3JioCJyjzgHaf3RNuOAC+RZGw+iS X-Received: by 2002:a17:90b:d0b:b0:250:2384:120d with SMTP id n11-20020a17090b0d0b00b002502384120dmr4082897pjz.19.1685491027608; Tue, 30 May 2023 16:57:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685491027; cv=none; d=google.com; s=arc-20160816; b=iQViqLvYZHMIJgYdbPbvRa65NCJZplEmi7QY0U2svIPLEMjlHi9fzdDXCBS2ckcQKP kb510Y8EFMzIUH21ArcW8gB/6Ne+i/oeMLwaiBv2UtH0BDPCLDO3Q+qTWdjX8fhlhwiB GfdVK3w1eGNMMuy3R+tx7AlWeKyPxM9UksF9jhFN6G+HAvKvtlJvO90hEtBDXtKvm1cc tnrBIgwCd7bcB5Y6K69yUI0HWvK9FvbS2DCKLe4x7bev/p3kbFA1q5H+kIoOBZgwNHb+ nLqwAaAlqQEkMOC+jOXCaQtJ1Gxbiu2/uT8zjZNxpeKk+0WOsKKe7sVTQz+UFQQlgExY 01Rg== ARC-Message-Signature: i=1; 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Signed-off-by: Chris Packham Reviewed-by: Miquel Raynal --- arch/arm/boot/dts/armada-385-atl-x530.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/armada-385-atl-x530.dts b/arch/arm/boot/dts/armada-385-atl-x530.dts index 241f5d7c80e9..5a9ab8410b7b 100644 --- a/arch/arm/boot/dts/armada-385-atl-x530.dts +++ b/arch/arm/boot/dts/armada-385-atl-x530.dts @@ -179,19 +179,19 @@ partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - partition@u-boot { + partition@0 { reg = <0x00000000 0x00100000>; label = "u-boot"; }; - partition@u-boot-env { + partition@100000 { reg = <0x00100000 0x00040000>; label = "u-boot-env"; }; - partition@unused { + partition@140000 { reg = <0x00140000 0x00e80000>; label = "unused"; }; - partition@idprom { + partition@fc0000 { reg = <0x00fc0000 0x00040000>; label = "idprom"; }; @@ -216,16 +216,16 @@ partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - partition@user { + partition@0 { reg = <0x00000000 0x0f000000>; label = "user"; }; - partition@errlog { + partition@f000000 { /* Maximum mtdoops size is 8MB, so set to that. */ reg = <0x0f000000 0x00800000>; label = "errlog"; }; - partition@nand-bbt { + partition@f800000 { reg = <0x0f800000 0x00800000>; label = "nand-bbt"; }; From patchwork Tue May 30 23:54:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 101162 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2536813vqr; Tue, 30 May 2023 16:57:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7yrWzw/vgX1DlMM4JhKCZ4XvT4c37Tuq+CvrHfSHBA4d+5n5ypWIzUcni8HaGJO2aTTPAb X-Received: by 2002:a05:6a20:d90b:b0:10c:89cc:bc5f with SMTP id jd11-20020a056a20d90b00b0010c89ccbc5fmr3854415pzb.20.1685491067132; Tue, 30 May 2023 16:57:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685491067; cv=none; d=google.com; s=arc-20160816; b=fWKodWDJDet5ZhQqH24/fgyGWf1dJIW7t49GX5icepez8SXXhlFmzVnM4BDnYFdFpA LIgJ1KCx9Au6pUFHYOIJBk89RN41vvgjivYgs4qbL7eHpOXdhhKu0V+2WYhwtQgrd0F8 IWnP8j7mdkX6IFjU/nL4nb1lXQYEzsMWb02DpyDIAI7zorhErFtMmlR0kAiEYZ1+UYcp OSx2epP/hSjNZQN0q7hJ+IShxwE6hs71k7jcoZhstYkoAGdy6/CSibfQZ+zfpbDfWIx4 21q1uZb/ERBVqdODNcdiJliB/hf1+gXhKSERWhwP/UeyxWpBu2qre8ZDaHE4zVSCMvJU 9NFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7vBmgdR5voSnV2P0MRjeixi9D7VeJEp5H1wolcRRnZg=; b=QW4zKlGhO3NZ8hOtbtSg3bGKcPlEpx3o+Ot2Lgwb1dCW5IzzzQxgCU5ptF9WjeRLpg rcgXA67BPk+SrhYQYOg2Bj6fBoz3oi9l1XzDenFFrCNev5f6RnuY7xUwcf6J2XRFrkHc FkZ1OKiIUvD06XqjrcGzIu9mzYYqi9X3k0+K66Xpl9J6IlVfr2CeXSCEB+x8KQli2ImF Q7udqmAG5OchEPspzBHbVUFp/c9J59NgF9hfZd2SchwEGuxyKw9baOMB4VMH1iSXsLvu 3GsNAyTmJIpxq102btlMqhf40M7cKcKV3sHA33Z+Dzta4FNSD2yVA0csSgszd2v52dBp pO0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@alliedtelesis.co.nz header.s=mail181024 header.b="PCeX/DzI"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=alliedtelesis.co.nz Received: from out1.vger.email (out1.vger.email. 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Dropped deprecated compatibles and properties described in txt file. Signed-off-by: Vadym Kochan Signed-off-by: Chris Packham --- Notes: Changes in v7: - Restore "label" and "partitions" properties (should be picked up via nand-controller.yaml but aren't) - Add/restore nand-on-flash-bbt and nand-ecc-mode which aren't covered by nand-controller.yaml. - Use "unevalautedProperties: false" - Corrections for clock-names, dma-names, nand-rb and nand-ecc-strength - Add pxa3xx-nand-controller example Changes in v6: - remove properties covered by nand-controller.yaml - add example using armada-8k compatible earlier changes: v5: 1) Get back "label" and "partitions" properties but without ref to the "partition.yaml" which was wrongly used. 2) Add "additionalProperties: false" for nand@ because all possible properties are described. v4: 1) Remove "label" and "partitions" properties 2) Use 2 clocks for A7K/8K platform which is a requirement v3: 1) Remove txt version from the MAINTAINERS list 2) Use enum for some of compatible strings 3) Drop: #address-cells #size-cells: as they are inherited from the nand-controller.yaml 4) Add restriction to use 2 clocks for A8K SoC 5) Dropped description for clock-names and extend it with minItems: 1 6) Drop description for "dmas" 7) Use "unevalautedProperties: false" 8) Drop quites from yaml refs. 9) Use 4-space indentation for the example section v2: 1) Fixed warning by yamllint with incorrect indentation for compatible list .../bindings/mtd/marvell,nand-controller.yaml | 221 ++++++++++++++++++ .../devicetree/bindings/mtd/marvell-nand.txt | 126 ---------- MAINTAINERS | 1 - 3 files changed, 221 insertions(+), 127 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/marvell-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml new file mode 100644 index 000000000000..7cd4a2e99343 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell NAND Flash Controller (NFC) + +maintainers: + - Miquel Raynal + +properties: + compatible: + oneOf: + - items: + - const: marvell,armada-8k-nand-controller + - const: marvell,armada370-nand-controller + - enum: + - marvell,armada370-nand-controller + - marvell,pxa3xx-nand-controller + - marvell,armada-8k-nand + - marvell,armada370-nand + - marvell,pxa3xx-nand + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: + Shall reference the NAND controller clocks, the second one is + is only needed for the Armada 7K/8K SoCs + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: core + - const: reg + + dmas: + maxItems: 1 + + dma-names: + items: + - enum: + - rxtx + - data + + marvell,system-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: Syscon node that handles NAND controller related registers + +patternProperties: + "^nand@[0-3]$": + type: object + unevaluatedProperties: false + properties: + reg: + minimum: 0 + maximum: 3 + + nand-rb: + minItems: 1 + maxItems: 1 + + nand-ecc-step-size: + const: 512 + + nand-ecc-strength: + enum: [1, 4, 8, 12, 16] + + nand-on-flash-bbt: + $ref: /schemas/types.yaml#/definitions/flag + + nand-ecc-mode: + const: hw + + label: + $ref: /schemas/types.yaml#/definitions/string + + partitions: + type: object + + marvell,nand-keep-config: + description: | + Orders the driver not to take the timings from the core and + leaving them completely untouched. Bootloader timings will then + be used. + $ref: /schemas/types.yaml#/definitions/flag + + marvell,nand-enable-arbiter: + description: | + To enable the arbiter, all boards blindly used it, + this bit was set by the bootloader for many boards and even if + it is marked reserved in several datasheets, it might be needed to set + it (otherwise it is harmless). + $ref: /schemas/types.yaml#/definitions/flag + deprecated: true + + additionalProperties: false + + required: + - reg + - nand-rb + +allOf: + - $ref: nand-controller.yaml + + - if: + properties: + compatible: + contains: + const: marvell,pxa3xx-nand-controller + then: + required: + - dmas + - dma-names + + - if: + properties: + compatible: + contains: + const: marvell,armada-8k-nand-controller + then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + required: + - marvell,system-controller + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include + nand_controller: nand-controller@d0000 { + compatible = "marvell,armada370-nand-controller"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coredivclk 0>; + + nand@0 { + reg = <0>; + label = "main-storage"; + nand-rb = <0>; + nand-ecc-mode = "hw"; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Rootfs"; + reg = <0x00000000 0x40000000>; + }; + }; + }; + }; + + - | + cp0_nand_controller: nand-controller@720000 { + compatible = "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg = <0x720000 0x54>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "core", "reg"; + clocks = <&cp0_clk 1 2>, + <&cp0_clk 1 17>; + marvell,system-controller = <&cp0_syscon0>; + + nand@0 { + reg = <0>; + label = "main-storage"; + nand-rb = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + }; + }; + + - | + nand-controller@43100000 { + compatible = "marvell,pxa3xx-nand-controller"; + reg = <0x43100000 90>; + interrupts = <45>; + clocks = <&clks 1>; + clock-names = "core"; + dmas = <&pdma 97 3>; + dma-names = "data"; + #address-cells = <1>; + #size-cells = <0>; + nand@0 { + reg = <0>; + nand-rb = <0>; + nand-ecc-mode = "hw"; + marvell,nand-keep-config; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/marvell-nand.txt b/Documentation/devicetree/bindings/mtd/marvell-nand.txt deleted file mode 100644 index a2d9a0f2b683..000000000000 --- a/Documentation/devicetree/bindings/mtd/marvell-nand.txt +++ /dev/null @@ -1,126 +0,0 @@ -Marvell NAND Flash Controller (NFC) - -Required properties: -- compatible: can be one of the following: - * "marvell,armada-8k-nand-controller" - * "marvell,armada370-nand-controller" - * "marvell,pxa3xx-nand-controller" - * "marvell,armada-8k-nand" (deprecated) - * "marvell,armada370-nand" (deprecated) - * "marvell,pxa3xx-nand" (deprecated) - Compatibles marked deprecated support only the old bindings described - at the bottom. -- reg: NAND flash controller memory area. -- #address-cells: shall be set to 1. Encode the NAND CS. -- #size-cells: shall be set to 0. -- interrupts: shall define the NAND controller interrupt. -- clocks: shall reference the NAND controller clocks, the second one is - is only needed for the Armada 7K/8K SoCs -- clock-names: mandatory if there is a second clock, in this case there - should be one clock named "core" and another one named "reg" -- marvell,system-controller: Set to retrieve the syscon node that handles - NAND controller related registers (only required with the - "marvell,armada-8k-nand[-controller]" compatibles). - -Optional properties: -- label: see partition.txt. New platforms shall omit this property. -- dmas: shall reference DMA channel associated to the NAND controller. - This property is only used with "marvell,pxa3xx-nand[-controller]" - compatible strings. -- dma-names: shall be "rxtx". - This property is only used with "marvell,pxa3xx-nand[-controller]" - compatible strings. - -Optional children nodes: -Children nodes represent the available NAND chips. - -Required properties: -- reg: shall contain the native Chip Select ids (0-3). -- nand-rb: see nand-controller.yaml (0-1). - -Optional properties: -- marvell,nand-keep-config: orders the driver not to take the timings - from the core and leaving them completely untouched. Bootloader - timings will then be used. -- label: MTD name. -- nand-on-flash-bbt: see nand-controller.yaml. -- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified. -- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when - not using hardware ECC. Howerver, it may be added when using hardware - ECC for clarification but will be ignored by the driver because ECC - mode is chosen depending on the page size and the strength required by - the NAND chip. This value may be overwritten with nand-ecc-strength - property. -- nand-ecc-strength: see nand-controller.yaml. -- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does - use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual - step size will shrink or grow in order to fit the required strength. - Step sizes are not completely random for all and follow certain - patterns described in AN-379, "Marvell SoC NFC ECC". - -See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on -generic bindings. - - -Example: -nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coredivclk 0>; - - nand@0 { - reg = <0>; - label = "main-storage"; - nand-rb = <0>; - nand-ecc-mode = "hw"; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Rootfs"; - reg = <0x00000000 0x40000000>; - }; - }; - }; -}; - - -Note on legacy bindings: One can find, in not-updated device trees, -bindings slightly different than described above with other properties -described below as well as the partitions node at the root of a so -called "nand" node (without clear controller/chip separation). - -Legacy properties: -- marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly - used it, this bit was set by the bootloader for many boards and even if - it is marked reserved in several datasheets, it might be needed to set - it (otherwise it is harmless) so whether or not this property is set, - the bit is selected by the driver. -- num-cs: Number of chip-select lines to use, all boards blindly set 1 - to this and for a reason, other values would have failed. The value of - this property is ignored. - -Example: - - nand0: nand@43100000 { - compatible = "marvell,pxa3xx-nand"; - reg = <0x43100000 90>; - interrupts = <45>; - dmas = <&pdma 97 0>; - dma-names = "rxtx"; - #address-cells = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - num-cs = <1>; - /* Partitions (optional) */ - }; diff --git a/MAINTAINERS b/MAINTAINERS index 250518fc70ff..e70dbc50a74e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12534,7 +12534,6 @@ MARVELL NAND CONTROLLER DRIVER M: Miquel Raynal L: linux-mtd@lists.infradead.org S: Maintained -F: Documentation/devicetree/bindings/mtd/marvell-nand.txt F: drivers/mtd/nand/raw/marvell_nand.c MARVELL OCTEON ENDPOINT DRIVER From patchwork Tue May 30 23:54:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 101160 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2536761vqr; Tue, 30 May 2023 16:57:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ45DoqnvnSVSm7BI9LWuW/RRwJUGKmSZBq74HJCF6S60QsJ1RrbwL0B4lCEEfiqn8yp4f++ X-Received: by 2002:a05:6a00:1903:b0:646:b165:1b29 with SMTP id y3-20020a056a00190300b00646b1651b29mr4461534pfi.23.1685491059104; Tue, 30 May 2023 16:57:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685491059; cv=none; d=google.com; s=arc-20160816; b=AJ4wzLBW8JpuJQUodVJ6ZXaUAsbGS8aiyDnvJBFw9jMGdnlVdo6IT2v9sHemI+7xiX eBZpfj49BrADXlMzzL6YeN0bKkZK0a+VqpxB1wmpxn1WupQbC54Gk6jvwuAspPz11B2K bYfPFlbVlm5+my/16JBUsJHuffSqkuTTezHyWf2hofp4qnNXl6UG9/rT0fB8sAF3zWje yqkrdIGgPbrZpglDCCDK3PJj77yjEUZX2ZyWcJAcL6zWLfdAnveGW5ot0QF07y0DxSBL wDQgfk+VANeCHujcZ+YsaLkqnRvk4PixCLaKDPYJqdwwO+qsnl0bwVQSIj6mi0cOFULO yIgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CR/D4HszLFw7g5PkmVVQf15ez0ihtAw6SzCP2pi70Bw=; b=QDKADglD3dhSo1iEwXIqTK6ImKj3ovu8ysqGMpdjwoN+OR2xN0B6/1eqIanG1xcyhv XCGPLWvN31XPxe0QE1o0MMbbhVqHPJD3xq0h2yDEnxpeora+xVOt2kiH0gG866Ozwg3P AJ0w/akM5dvhUAF16WOqOCb88EiBCV8aEGznTHNtTY2S3a8oRCoCD1K9Z5IsSC0qZAym iWh6o9YEkSBcms4GKCZJp+HSwgt1IJ/3e9Dvw9UFe1Htv/zOiPqDjuGnV2ufagI7+EAU sTJXIW94Mb8YabW27tBzKtXGH+rY1lxzJgBKYMigwvLQQoEvebfUpNobAe8cD8XMeRP7 cVEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@alliedtelesis.co.nz header.s=mail181024 header.b=VWOIvWVJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=alliedtelesis.co.nz Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Chris Packham --- .../devicetree/bindings/mtd/marvell,nand-controller.yaml | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml index 7cd4a2e99343..80ce854291cb 100644 --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml @@ -18,9 +18,6 @@ properties: - enum: - marvell,armada370-nand-controller - marvell,pxa3xx-nand-controller - - marvell,armada-8k-nand - - marvell,armada370-nand - - marvell,pxa3xx-nand reg: maxItems: 1