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The watermark implementation and maximum size is dependent on the device where Cadence MACB/GEM is used. Signed-off-by: Pranavi Somisetty --- Changes v2: None (patch added in v2) Changes v3: 1. Fixed DT schema error: "scalar properties shouldn't have array keywords". 2. Modified description of rx-watermark to include units of the watermark value. 3. Modified the DT property name corresponding to rx_watermark in pbuf_rxcutthru to "cdns,rx-watermark". 4. Modified commit description to remove references to Xilinx platforms, since the changes aren't platform specific. --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index bef5e0f895be..2c733c061dce 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -109,6 +109,14 @@ properties: power-domains: maxItems: 1 + cdns,rx-watermark: + $ref: /schemas/types.yaml#/definitions/uint16 + description: + Set watermark value for pbuf_rxcutthru reg and enable + rx partial store and forward. Watermark value here + corresponds to number of SRAM locations. The width of SRAM is + system dependent and can be 4,8 or 16 bytes. + '#address-cells': const: 1 @@ -166,6 +174,7 @@ examples: compatible = "cdns,macb"; reg = <0xfffc4000 0x4000>; interrupts = <21>; + cdns,rx-watermark = /bits/ 16 <0x44>; phy-mode = "rmii"; local-mac-address = [3a 0e 03 04 05 06]; clock-names = "pclk", "hclk", "tx_clk"; From patchwork Tue May 30 09:51:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Somisetty, Pranavi" X-Patchwork-Id: 100717 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2069205vqr; Tue, 30 May 2023 03:13:45 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ72Td/RlzU+MFcX9E0OCTSR8ninIwpNMHN+wKNqV6m5DpXCHhdcwujWTtiVDOSgIZqmTM5o X-Received: by 2002:a05:6a00:2d84:b0:62d:d045:392 with SMTP id fb4-20020a056a002d8400b0062dd0450392mr2082480pfb.32.1685441625285; Tue, 30 May 2023 03:13:45 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1685441625; cv=pass; d=google.com; s=arc-20160816; b=Oerbx16BqxKrAHu89HZA2f7ju5F3OX5n3fC5x+kDsVsTzpSXPNFNAr7drOBKzH0Xfl a1IFIe7x2vm9x+SyZbSNyk9SAZcxjQrjK+hkckCpaB7PetJlG/ewBTqMcTGROXBI4iHo 3nta7hVBl8QabUlXbwCo+aS6o3QLUFuPKb3zyrGPwBpPrJQVHuf/EzUVwuPwctw51FG4 oO+7JJz6780I4OLb3m4EDKp6bak+0GFQaWfJiJde4dFLUcfvdUs8bkLunzYggoFr20NB GCvw/RVAJpl3dvWnm0H3D7tquhTNX+o9crYkmuBsedrOy8uFHiWU+JGjdXZBV5MGYw/z 9BtQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=p1V+lpaqJfJFGwoO20hO4ITpBohCtCyShhCMpAHJZWY=; b=oUxmyveBvlJzSKAlxRHky6wQfKp0bzwzgm4Y4DcdcZiLS4UrpRERJ+lBfxA/nrVwpH d2Ej0NN0fPIynoCX2lRE3JrZwr5su9s/aXG+cD4/YSw13ir1horKpxHBZhayPiO/lQ5m IV8S987HWcDNKXm2k/+M0sKZ6P1dMu8xs04K17ZXEJnAJMrDwpNFhtmFgJmGuXJdgVc0 GAPojYin9ApAVSEah9e8CHXY/2aAdy0nxOG6x75gtw/shHF3q2GZzdPsaDHwE4jCzcNF HoJya06PpCpdPNwI9U0Gw1ZnSyd/vMa+FAR9Kw72KoCjn5v5RJS5Ad7xAKMzTEUgHD8g dqLw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="SW4J/Y1d"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 May 2023 09:51:53.7020 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17da194a-b848-40f9-2a26-08db60f37fa1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT092.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7795 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767313637863094495?= X-GMAIL-MSGID: =?utf-8?q?1767313637863094495?= From: Maulik Jodhani When the receive partial store and forward mode is activated, the receiver will only begin to forward the packet to the external AHB or AXI slave when enough packet data is stored in the packet buffer. The amount of packet data required to activate the forwarding process is programmable via watermark registers which are located at the same address as the partial store and forward enable bits. Adding support to read this rx-watermark value from device-tree, to program the watermark registers and enable partial store and forwarding. Signed-off-by: Maulik Jodhani Signed-off-by: Pranavi Somisetty --- Changes v2: 1. Removed all the changes related to validating FCS when Rx checksum offload is disabled. 2. Instead of using a platform dependent number (0xFFF) for the reset value of rx watermark, derive it from designcfg_debug2 register. 3. Added a check to see if partial s/f is supported, by reading the designcfg_debug6 register. Changes v3: 1. Followed reverse christmas tree pattern in declaring variables. 2. Return -EINVAL when an invalid watermark value is set. 3. Removed netdev_info when partial store and forward is not enabled. 4. Validating the rx-watermark value in probe itself and only write to the register in init. 5. Writing a reset value to the pbuf_cuthru register before disabing partial store and forward is redundant. So removing it. 6. Removed the platform caps flag. 7. Instead of reading rx-watermark from DT in macb_configure_caps, reading it in probe. 8. Changed Signed-Off-By and author names on this patch. --- drivers/net/ethernet/cadence/macb.h | 14 ++++++++++++ drivers/net/ethernet/cadence/macb_main.c | 29 ++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 14dfec4db8f9..416e6070e4ec 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -82,6 +82,7 @@ #define GEM_NCFGR 0x0004 /* Network Config */ #define GEM_USRIO 0x000c /* User IO */ #define GEM_DMACFG 0x0010 /* DMA Configuration */ +#define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */ #define GEM_JML 0x0048 /* Jumbo Max Length */ #define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */ #define GEM_HRB 0x0080 /* Hash Bottom */ @@ -343,6 +344,11 @@ #define GEM_ADDR64_SIZE 1 +/* Bitfields in PBUFRXCUT */ +#define GEM_WTRMRK_OFFSET 0 /* Watermark value offset */ +#define GEM_ENCUTTHRU_OFFSET 31 /* Enable RX partial store and forward */ +#define GEM_ENCUTTHRU_SIZE 1 + /* Bitfields in NSR */ #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ #define MACB_NSR_LINK_SIZE 1 @@ -509,6 +515,8 @@ #define GEM_TX_PKT_BUFF_OFFSET 21 #define GEM_TX_PKT_BUFF_SIZE 1 +#define GEM_RX_PBUF_ADDR_OFFSET 22 +#define GEM_RX_PBUF_ADDR_SIZE 4 /* Bitfields in DCFG5. */ #define GEM_TSU_OFFSET 8 @@ -517,6 +525,8 @@ /* Bitfields in DCFG6. */ #define GEM_PBUF_LSO_OFFSET 27 #define GEM_PBUF_LSO_SIZE 1 +#define GEM_PBUF_CUTTHRU_OFFSET 25 +#define GEM_PBUF_CUTTHRU_SIZE 1 #define GEM_DAW64_OFFSET 23 #define GEM_DAW64_SIZE 1 @@ -718,6 +728,7 @@ #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 #define MACB_CAPS_MIIONRGMII 0x00000200 #define MACB_CAPS_NEED_TSUCLK 0x00000400 +#define MACB_CAPS_PARTIAL_STORE_FORWARD 0x00000800 #define MACB_CAPS_PCS 0x01000000 #define MACB_CAPS_HIGH_SPEED 0x02000000 #define MACB_CAPS_CLK_HW_CHG 0x04000000 @@ -1283,6 +1294,9 @@ struct macb { u32 wol; + /* holds value of rx watermark value for pbuf_rxcutthru register */ + u16 rx_watermark; + struct macb_ptp_info *ptp_info; /* macb-ptp interface */ struct phy *sgmii_phy; /* for ZynqMP SGMII mode */ diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 41964fd02452..7a31e6673e15 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -2617,6 +2617,9 @@ static void macb_reset_hw(struct macb *bp) macb_writel(bp, TSR, -1); macb_writel(bp, RSR, -1); + /* Disable RX partial store and forward and reset watermark value */ + gem_writel(bp, PBUFRXCUT, 0); + /* Disable all interrupts */ for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { queue_writel(queue, IDR, -1); @@ -2770,6 +2773,10 @@ static void macb_init_hw(struct macb *bp) bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; macb_configure_dma(bp); + + /* Enable RX partial store and forward and set watermark */ + if (bp->rx_watermark) + gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU))); } /* The hash address register is 64 bits long and takes up two @@ -4923,6 +4930,7 @@ static int macb_probe(struct platform_device *pdev) phy_interface_t interface; struct net_device *dev; struct resource *regs; + u32 wtrmrk_rst_val; void __iomem *mem; struct macb *bp; int err, val; @@ -4995,6 +5003,27 @@ static int macb_probe(struct platform_device *pdev) bp->usrio = macb_config->usrio; + /* By default we set to partial store and forward mode for zynqmp. + * Disable if not set in devicetree. + */ + if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) { + err = of_property_read_u16(bp->pdev->dev.of_node, + "cdns,rx-watermark", + &bp->rx_watermark); + + if (!err) { + /* Disable partial store and forward in case of error or + * invalid watermark value + */ + wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1; + if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) { + dev_info(&bp->pdev->dev, "Invalid watermark value\n"); + bp->rx_watermark = 0; + return -EINVAL; + } + bp->rx_watermark &= wtrmrk_rst_val; + } + } spin_lock_init(&bp->lock); /* setup capabilities */