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No functional change intended. Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/pmu.h | 12 ++++++++++++ arch/x86/kvm/vmx/pmu_intel.c | 12 ------------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 5c7bbf03b599..986563aeeef8 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -201,6 +201,18 @@ static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc) kvm_make_request(KVM_REQ_PMU, pmc->vcpu); } +static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff) +{ + int bit; + + if (!diff) + return; + + for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) + set_bit(bit, pmu->reprogram_pmi); + kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 741efe2c497b..1f9c3e916a21 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -73,18 +73,6 @@ static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx) } } -static void reprogram_counters(struct kvm_pmu *pmu, u64 diff) -{ - int bit; - - if (!diff) - return; - - for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) - set_bit(bit, pmu->reprogram_pmi); - kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); -} - static bool intel_hw_event_available(struct kvm_pmc *pmc) { struct kvm_pmu *pmu = pmc_to_pmu(pmc); From patchwork Tue May 30 06:04:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 100554 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1962891vqr; Mon, 29 May 2023 23:06:13 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6VsIKt6vByTTHd1WL9mKkADWEG/MIbo5R9fIwlSCFSaHrCw+5mdnE2674M1l3wY9JOlUe8 X-Received: by 2002:a05:6a00:134e:b0:64f:49ee:1a61 with SMTP id k14-20020a056a00134e00b0064f49ee1a61mr1409522pfu.34.1685426773603; Mon, 29 May 2023 23:06:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685426773; cv=none; d=google.com; s=arc-20160816; b=CrtzDB3Bbcz8Vv4g5U1ajsvBk8Kaqvt+oS2BG5Ptvdmxd1Zi1KtWx3woC6NDlJ9ERM oKnQapQtlKna39DIBmgWiSybuLRvA+jcC9xYxmdrSEEoi9G9q6fq32p/UEsOllkrYt9b nSA9mhyV+L3A7AeyAMgJzq2HGiP+O8uND14PcYypE5JO2fF/M80nlPSDo7FS23cr5OPs NGbcouVsf5oZPOd6oD3yJ+g1rg40aTLnlyNtZHAVOUzxPYt3Lo9a0mvgtC3mRPW/YDyc vg1pUYwJmyDDKGKmvI6TIhXS24Nhn/VPWCWJ41zRsXoBqYGdUm6IIRX41Pdg4+tR4Hjs NGRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PLWGy0NbpiEOq7RoGuVnbCHs52CWitnw7+cWqMmaFzU=; b=fYY13lpJX+2ViEhemFhNGN/ombdfWt+UROOdJfn6ztgggzmC3B6t9gG+6UAMoejWF5 Mp3/2UD0gVTy2IbtU2gk4rqv3SCilrMzTKoQlPwjLE8+PbVWi8YOtwAWvPRzRRFMxHzE tRgv9GoMzaNVUILuSBOrcshYZ3ggTC4UxnANliqghvIhTDnV3l55e7HO5EQIrjR4eA+X 4RJ4h8tVwQhdzuK3mHkv/6JvNLCTAUFVgGkW4RRTFxB9Mcv7WYJM82HWBDnT+JqA3BgW 8o7ob83CouTrTi8ag257eFfoHVaAePM+hfjcJ83wo3QtRkXIBOCOpqZIV2AWX4ky0wGu iKlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=cnfzWvyj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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If the user space sets reserved bits when restoring the MSR_CORE_ PERF_GLOBAL_STATUS register, these bits will be accidentally returned when the guest runs a read access to this register, and cannot be cleared up inside the guest, which makes the guest's PMI handler very confused. Note, reusing global_ovf_ctrl_mask as global_status_mask will be broken if KVM supports higher versions of Intel arch pmu. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/pmu_intel.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 1f9c3e916a21..343b3182b7f4 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -399,7 +399,11 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) reprogram_fixed_counters(pmu, data); break; case MSR_CORE_PERF_GLOBAL_STATUS: - if (!msr_info->host_initiated) + /* + * Caution, the assumption here is that some of the bits (such as + * ASCI, CTR_FREEZE, and LBR_FREEZE) are not yet supported by KVM. + */ + if (!msr_info->host_initiated || (data & pmu->global_ovf_ctrl_mask)) return 1; /* RO MSR */ pmu->global_status = data; From patchwork Tue May 30 06:04:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 100565 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1965565vqr; Mon, 29 May 2023 23:11:55 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ72S3XYRaRhsclV1iCOhnkpTlGEcd7c7DjQNHz/PSlX8XsZrTmU95cZkBS04zaKNE0d5Rp0 X-Received: by 2002:a17:90a:8c85:b0:24d:ff56:f8c1 with SMTP id b5-20020a17090a8c8500b0024dff56f8c1mr1471255pjo.13.1685427115063; Mon, 29 May 2023 23:11:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685427115; cv=none; d=google.com; s=arc-20160816; b=ll/0Vlw4fqe0BtgDVt6wO72ooMHOmU6q+hCzIX0nBA41GyxlJGPqFvxiq0Yri7p9bq js6+/AR0Dgm8Fi9lGX7YOCHAxtqhIRMGyvkGaA2pP11tYyKIaXEai8k2AjA0/W1G1Wuo Lsp37WogFvPIa4Hld2kkIEmT/Y0a4qwleOJs5NHQPlez/3wyNT3U8Vk2zpmarL25oJke TEVn9K2lFcr53P2pjcYC3VnJWanOWXIVmkJporPx3t17/gn+f+r3Tn2lFtWtZ+teXeBm 19JgNTEwhV1ZUm1wIfSzN6R0uP/qoGHa1NQIJ3Jtf1HoSuNaIy1dqnDD1MQhh2JwWBlZ p7bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=L4qxgyJAgBoUJPESWX33eEPzSbuOiRKztmB95/78wKA=; b=UXyOmIjNeTr0fVyiX8XzgFS80cnJ6+ngWjVx7pzGjoKzO1VCp61+P2NdSe10a7p9sl I547hbISui+3zBRzUGSWsaN2rOutoLRlQwY/QLRCZ5Gnur+I5q1s1gfPG6WsvMr6dLBu JTZiMMs9CT71SAw2l7ecP9yOI0dkSzs2oNEbdvkTuZII+8lJWf7TMV9FijJqj9qg7Shm gNfbLIqRZEXTyJ+a4AqMuGaIT/iLbCu3zLjmTqiH1VY6CoPbJYAK/hjaCZlD/IhVc+/C z4CfdKvrhv0ZKXX11SU+LuyPPjJmVNV/a7clVZAMPR4vcQqkxpSMrpTBfReCx9eptcl/ o2mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=HmKkrYoO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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For better code reuse, this specific part of the handling can be extracted to make it generic for X86 as a straight code movement. Specifically, the kvm_pmu_set/get_msr() handlers of GLOBAL_STATUS, GLOBAL_CTRL, GLOBAL_OVF_CTRL defined for Intel are moved to generic pmu.c and the callback function .pmc_is_globally_enabled is removed, which is very helpful to introduce the AMD PerfMonV2 code later. The new eponymous pmc_is_globally_enabled() works well as legacy AMD vPMU version is indexed as 1. Note that the specific *_is_valid_msr will continue to be used to avoid cross-vendor MSR access. Signed-off-by: Like Xu --- arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 - arch/x86/kvm/pmu.c | 61 ++++++++++++++++++++++---- arch/x86/kvm/pmu.h | 17 ++++++- arch/x86/kvm/svm/pmu.c | 9 ---- arch/x86/kvm/vmx/pmu_intel.c | 14 +----- 5 files changed, 70 insertions(+), 32 deletions(-) diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/kvm-x86-pmu-ops.h index c17e3e96fc1d..6c98f4bb4228 100644 --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h @@ -13,7 +13,6 @@ BUILD_BUG_ON(1) * at the call sites. */ KVM_X86_PMU_OP(hw_event_available) -KVM_X86_PMU_OP(pmc_is_enabled) KVM_X86_PMU_OP(pmc_idx_to_pmc) KVM_X86_PMU_OP(rdpmc_ecx_to_pmc) KVM_X86_PMU_OP(msr_idx_to_pmc) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 1690d41c1830..116bc7fe13c6 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -93,11 +93,6 @@ void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops) #undef __KVM_X86_PMU_OP } -static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc) -{ - return static_call(kvm_x86_pmu_pmc_is_enabled)(pmc); -} - static void kvm_pmi_trigger_fn(struct irq_work *irq_work) { struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work); @@ -577,13 +572,63 @@ static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr) int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { - return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info); + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + u32 msr = msr_info->index; + + switch (msr) { + case MSR_CORE_PERF_GLOBAL_STATUS: + msr_info->data = pmu->global_status; + break; + case MSR_CORE_PERF_GLOBAL_CTRL: + msr_info->data = pmu->global_ctrl; + break; + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + msr_info->data = 0; + break; + default: + return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info); + } + + return 0; } int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { - kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index); - return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info); + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + u32 msr = msr_info->index; + u64 data = msr_info->data; + u64 diff; + + switch (msr) { + case MSR_CORE_PERF_GLOBAL_STATUS: + if (!msr_info->host_initiated || (data & pmu->global_ovf_ctrl_mask)) + return 1; /* RO MSR */ + + pmu->global_status = data; + break; + case MSR_CORE_PERF_GLOBAL_CTRL: + if (!kvm_valid_perf_global_ctrl(pmu, data)) + return 1; + + if (pmu->global_ctrl != data) { + diff = pmu->global_ctrl ^ data; + pmu->global_ctrl = data; + reprogram_counters(pmu, diff); + } + break; + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + if (data & pmu->global_ovf_ctrl_mask) + return 1; + + if (!msr_info->host_initiated) + pmu->global_status &= ~data; + break; + default: + kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index); + return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info); + } + + return 0; } /* refresh PMU settings. This function generally is called when underlying diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 986563aeeef8..dd7c7d4ffe3b 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -20,7 +20,6 @@ struct kvm_pmu_ops { bool (*hw_event_available)(struct kvm_pmc *pmc); - bool (*pmc_is_enabled)(struct kvm_pmc *pmc); struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx); struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, unsigned int idx, u64 *mask); @@ -213,6 +212,22 @@ static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff) kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); } +/* + * Check if a PMC is enabled by comparing it against global_ctrl bits. + * + * If the current version of vPMU doesn't have global_ctrl MSR, + * all vPMCs are enabled (return TRUE). + */ +static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc) +{ + struct kvm_pmu *pmu = pmc_to_pmu(pmc); + + if (pmu->version < 2) + return true; + + return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 5fa939e411d8..70143275e0a7 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -78,14 +78,6 @@ static bool amd_hw_event_available(struct kvm_pmc *pmc) return true; } -/* check if a PMC is enabled by comparing it against global_ctrl bits. Because - * AMD CPU doesn't have global_ctrl MSR, all PMCs are enabled (return TRUE). - */ -static bool amd_pmc_is_enabled(struct kvm_pmc *pmc) -{ - return true; -} - static bool amd_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -220,7 +212,6 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu) struct kvm_pmu_ops amd_pmu_ops __initdata = { .hw_event_available = amd_hw_event_available, - .pmc_is_enabled = amd_pmc_is_enabled, .pmc_idx_to_pmc = amd_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc, .msr_idx_to_pmc = amd_msr_idx_to_pmc, diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 343b3182b7f4..99d07ccb1869 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -95,17 +95,6 @@ static bool intel_hw_event_available(struct kvm_pmc *pmc) return true; } -/* check if a PMC is enabled by comparing it with globl_ctrl bits. */ -static bool intel_pmc_is_enabled(struct kvm_pmc *pmc) -{ - struct kvm_pmu *pmu = pmc_to_pmu(pmc); - - if (!intel_pmu_has_perf_global_ctrl(pmu)) - return true; - - return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); -} - static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -793,7 +782,7 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) pmc = intel_pmc_idx_to_pmc(pmu, bit); if (!pmc || !pmc_speculative_in_use(pmc) || - !intel_pmc_is_enabled(pmc) || !pmc->perf_event) + !pmc_is_globally_enabled(pmc) || !pmc->perf_event) continue; /* @@ -808,7 +797,6 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) struct kvm_pmu_ops intel_pmu_ops __initdata = { .hw_event_available = intel_hw_event_available, - .pmc_is_enabled = intel_pmc_is_enabled, .pmc_idx_to_pmc = intel_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc, .msr_idx_to_pmc = intel_msr_idx_to_pmc, From patchwork Tue May 30 06:04:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 100555 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1962977vqr; Mon, 29 May 2023 23:06:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7Y/dk9uSzPTQvxspiZ8XRr3wayY1I982extyBAk91HTkvRo/owJQGGaclHgQ9OShw5mhU3 X-Received: by 2002:a05:6a00:2295:b0:64c:c5f9:1533 with SMTP id f21-20020a056a00229500b0064cc5f91533mr1201895pfe.33.1685426785589; Mon, 29 May 2023 23:06:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685426785; cv=none; d=google.com; s=arc-20160816; b=apQrOYQ4O3wCUkfP5Rdv2cKige0mfcy3YzxaWEI19bKp36X4EF6Una/AR7MVUjny48 BDQTu2RUNUY+HfbrOuJAthsZPAOWj0WRddHxZtyZHzsP7a5MDJ3BSiarJJRFOBljOTaX gVoLQrrVsMwF/QuQ5F4p+iCKsPaKsauiOKoyusldgsTcG96ziK6VWFOzsQozJ/bspqGZ qhpk8JfU0MQMMdojgfVv5kSDg9qI4zLBONLxVJOM/Drw6biweVBfbqIUVqQaIzNf1i1c BkVbC5akKdQuPnOWy4df//JTY3ig0rtR8QEpEHo7Urv5cIDVFZ56FbFD1GXM1rmDI8rU FqeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SB00GL0LbEeM0tLPl7sWR4JRmLJ9vo4/Dc9WjVfAf2U=; b=bbSF5ReZqT5k529bvJfRWGDrmMVSY/XG1tna0Dn1Xf3UokjsWeXnN8mHizUwU+xCqX GKudfmSMycnto6H3uWP/7mbSTAP80bgmUoryDRHu7TkjwXNrFVDgYhZ+NhOt4t+bow2o IwTwXnEUB5NcYRHwxybFFgUa8jXzRpqC0fwYcxi3KQQoRw+zpmX98IXkEM79nrhrd+jH cKInRydi6Twt3tRyDkplQdSHpTXAqj3CX4TCVEDD6QfEaQjtfNJQ1sk1fCcT5M4OH7ZQ bzx+wmhOjkrowsT/N2rweeTS6DXq/jm5i0E9oAWp6NUlkXOueMw2PyhLL4X+SW3M5dK4 uTQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=E7o3ljUl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Although when !enable_pmu, KVM will have zero-padded kvm_pmu_cap to do subsequent CPUID leaf assignments. Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 0c9660a07b23..61bc71882f07 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -948,7 +948,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) union cpuid10_eax eax; union cpuid10_edx edx; - if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { + if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { entry->eax = entry->ebx = entry->ecx = entry->edx = 0; break; } From patchwork Tue May 30 06:04:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 100556 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1963083vqr; Mon, 29 May 2023 23:06:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5i6rjjwCyMIZUYjSvhNdxQxuxIUj4jS0CyE6EeTp0/gdfOIcn5q+t1iWd/9HfyBlERvyxa X-Received: by 2002:a17:90a:43e2:b0:253:6b3a:ab1e with SMTP id r89-20020a17090a43e200b002536b3aab1emr10973635pjg.6.1685426798349; Mon, 29 May 2023 23:06:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685426798; cv=none; d=google.com; s=arc-20160816; b=tWZO79AYxWsk88g83CuzRmcjiJen9AgYf6IW8/V0HhR01FJ0y4hgxkYHVMHdNscG0J /AzLmKpTPiOLbexmVbaFYancxBNE18L5IvLGCkXk3VGDyv9ODjYLkFd/bekfI3cLcSwD mfR0SVPWfkQCy+hG6rlptiXtwjkEp3nz/aoxmTL+B0lAsmqYnro6czaWH0QaVBphbXEK vjywVsx2/xETD/9ZZyAE51a1aRFJov9ML4DTfy8u6hO+5kHD7LA0SBVgnG65KJbSilwT Q+8b6pOPa8Q/Iix21Kz2u5W0dSosFzzccHxvTtFTGC88K+plYEMTwcW6JK0PA3PavJXW 3fEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/xqA6m3mPbeN62DVnOEmc3GlEb3DP3v9n2buE8hSS5s=; b=udHPuGCPygTB5TDoJv7unWvSTDeSSxlGj7EZsP4as3VmK9REYHVGDFItBK5VcD5F71 r1UY2r6Y+kmzKPENkdNrkdqp0lR+lL/EXvAggoO8Mb3Yf3cWwRb8DZJncpDsTImgTYo+ DSBLWqVI8uCTcyvNuyIREPBAm7sN5lYXoXjU2Ygi+ewdk0ditAGH1+uNV8R2YyAcIKs4 ao1v2mJ3kDwkqrAqj+TAGSFBxl57AHDF43ReMgY6F6MNqyCwTfkRWf0GJ4R4AH0qcIOY f7bfvqQN4R2nZcnlgKd06QcP4WOhn1QEayOTWWUMU8ai2XLEsg+GorypbEzKNMS+YlXB zquw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=iBPgN25w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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All AMD PMUs must define at least four counters due to AMD's legacy architecture hardcoding the number of counters without providing a way to enumerate the number of counters to software, e.g. from AMD's APM: The legacy architecture defines four performance counters (PerfCtrn) and corresponding event-select registers (PerfEvtSeln). Virtualizing fewer than four counters can lead to guest instability as software expects four counters to be available. Rather than bleed AMD details into the common code, just define a const unsigned int and provide a convenient location to document why Intel and AMD have different mins (in particular, AMD's lack of any way to enumerate less than four counters to the guest). According to Intel SDM, "Intel Core Solo and Intel Core Duo processors support base level functionality identified by version ID of 1. Processors based on Intel Core microarchitecture support, at a minimum, the base level functionality of architectural performance monitoring." Those antique processors mentioned above all had at least two GP counters, subsequent processors had more and more GP counters, and given KVM's quirky handling of MSR_P6_PERFCTR0/1, the value of MIN_NR_GP_COUNTERS for the Intel Arch PMU can safely be 2. Cc: Jim Mattson Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/pmu.h | 14 ++++++++++---- arch/x86/kvm/svm/pmu.c | 1 + arch/x86/kvm/vmx/pmu_intel.c | 1 + 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index dd7c7d4ffe3b..019a8ed51b12 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -36,6 +36,7 @@ struct kvm_pmu_ops { const u64 EVENTSEL_EVENT; const int MAX_NR_GP_COUNTERS; + const int MIN_NR_GP_COUNTERS; }; void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops); @@ -160,6 +161,7 @@ extern struct x86_pmu_capability kvm_pmu_cap; static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops) { bool is_intel = boot_cpu_data.x86_vendor == X86_VENDOR_INTEL; + int min_nr_gp_ctrs = pmu_ops->MIN_NR_GP_COUNTERS; /* * Hybrid PMUs don't play nice with virtualization without careful @@ -174,11 +176,15 @@ static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops) perf_get_x86_pmu_capability(&kvm_pmu_cap); /* - * For Intel, only support guest architectural pmu - * on a host with architectural pmu. + * WARN if perf did NOT disable hardware PMU if the number of + * architecturally required GP counters aren't present, i.e. if + * there are a non-zero number of counters, but fewer than what + * is architecturally required. */ - if ((is_intel && !kvm_pmu_cap.version) || - !kvm_pmu_cap.num_counters_gp) + if (!kvm_pmu_cap.num_counters_gp || + WARN_ON_ONCE(kvm_pmu_cap.num_counters_gp < min_nr_gp_ctrs)) + enable_pmu = false; + else if (is_intel && !kvm_pmu_cap.version) enable_pmu = false; } diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 70143275e0a7..e5c69062a909 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -224,4 +224,5 @@ struct kvm_pmu_ops amd_pmu_ops __initdata = { .reset = amd_pmu_reset, .EVENTSEL_EVENT = AMD64_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS = KVM_AMD_PMC_MAX_GENERIC, + .MIN_NR_GP_COUNTERS = AMD64_NUM_COUNTERS, }; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 99d07ccb1869..08851b49e1d4 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -811,4 +811,5 @@ struct kvm_pmu_ops intel_pmu_ops __initdata = { .cleanup = intel_pmu_cleanup, .EVENTSEL_EVENT = ARCH_PERFMON_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS = KVM_INTEL_PMC_MAX_GENERIC, + .MIN_NR_GP_COUNTERS = 2, }; From patchwork Tue May 30 06:04:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 100562 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1963594vqr; Mon, 29 May 2023 23:07:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ68D9zM7fiXV68VLb1G0KrSxpX06FRmHtqi9IPUlYMUNpuieVm7K3/dcCYd3ApOV+2vYSHj X-Received: by 2002:a05:6a00:881:b0:64a:f8c9:a42c with SMTP id q1-20020a056a00088100b0064af8c9a42cmr1500879pfj.18.1685426861752; Mon, 29 May 2023 23:07:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685426861; cv=none; d=google.com; s=arc-20160816; b=cmvyRPn1SmbKi3NKEQpf1c3ZBNXy9Z9/aywSJqJF2xa2VSd0pzR6R1ul0vOHtRYK94 GwtWit2ivUu1XKn2aqRCi53+TKtXRLy6fzx4pB2PvZlbyERAa6H3YZDG0XQ6yTZmTZzh eSSHtsUI8KX50G1lGMoE0l9cU12lWxLrKObN00FptJArjvh/8KwWFvGGlGS5BaY097Ig xUy0Fdi1kHvo767j2/HgYjF0bNm31CSDEgLbO5msLCXXmJpcxXyDePtdSwZpIRB1KFFd tUrvUliDt3W1saK68xxFv1cz9qE0pYW29lElUS4ZZHf+puAh9vNQGX/Nq4J+CbSVxdST g60Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=okCUbwauqIa1DTJDmeQLbGd8OQ9Kua7tSb7xsqMZiUI=; b=ztWjUe4yl8xJTyuuWpYXc3KEYIU6a+BLkTsOCDjDS7zveV+PiIfe4L5o18SyOQm8NE B0Q/Pn+kCzAr9tOvmcGjhhX5kN29qOF3mVnT4MFILScBZPMlJwfXtsopUTP4ymkSer1I gdxeXQjvTsiBnl286+tfkrM6UL2CrCPMb5BRtN15a2LFr0vMqcD3y043Sab0khM5SGjC hyeqzi7CYMha9pc9BMiJX/MtVQ7K42eDcX32znuMnhwQQCFsGrTT3QPuYWYmibF5cokW ZEM7otwIKUlqHTxTxVF7CBZ/ybEcNY9plP9YNT6xo4kvUzBMHLJIvk7tMYck4CYui4xv U4+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=U7+mSxeC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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PERFCTR_CORE support is explicitly dropped if the min number isn't met. E.g. if KVM needs 6 counters and perf says there are 4, then something is wrong and enumerating 6 to a guest is only going to cause more issues. Opportunistically, the kvm_cpu_cap_check_and_set() is applied to simplify the host check before setting the PERFCTR_CORE flag. Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/svm/svm.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index ca32389f3c36..d9669e3cc00a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5025,9 +5025,18 @@ static __init void svm_set_cpu_caps(void) boot_cpu_has(X86_FEATURE_AMD_SSBD)) kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); - /* AMD PMU PERFCTR_CORE CPUID */ - if (enable_pmu && boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) - kvm_cpu_cap_set(X86_FEATURE_PERFCTR_CORE); + if (enable_pmu) { + /* + * Enumerate support for PERFCTR_CORE if and only if KVM has + * access to enough counters to virtualize "core" support, + * otherwise limit vPMU support to the legacy number of counters. + */ + if (kvm_pmu_cap.num_counters_gp < AMD64_NUM_COUNTERS_CORE) + kvm_pmu_cap.num_counters_gp = min(AMD64_NUM_COUNTERS, + kvm_pmu_cap.num_counters_gp); + else + kvm_cpu_cap_check_and_set(X86_FEATURE_PERFCTR_CORE); + } /* CPUID 0x8000001F (SME/SEV features) */ sev_set_cpu_caps(); From patchwork Tue May 30 06:04:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 100557 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1963184vqr; Mon, 29 May 2023 23:06:50 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5Jvu9Ij9L0ucEpZHJaQgbSPw9DPqrLKWOf58UO6qAHv3hwiKVlJDRYokilnpiUvArcnaw5 X-Received: by 2002:a17:902:ee55:b0:1ac:4d01:dfec with SMTP id 21-20020a170902ee5500b001ac4d01dfecmr1300279plo.54.1685426810140; Mon, 29 May 2023 23:06:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685426810; cv=none; d=google.com; s=arc-20160816; b=diSw6hkee3TJgvB0FqNPoHKpNGKuctCR/pdgRI4aklNmmBqUpKxuYeTdmuR1wAmnYA VOAKP3xgvlQL+R3v9Muaw1uEZyVLh3vbeKm27a2EN51cmgzfANU0ZcU4/AsEVwBjx5LZ kw36C/TI3tDD5AJ8SB9+kPmWZwhqQ/UBYCHkuuEHhBqbyKMiM623TsII1WI3isYkM5GL QjhDgLGtw5EjC1HojJcBVt/FrSm9XEAdRgFhRsemIdr5/AJSRrOG660fU4CcivsROSZS VeTx0xGSlDPBFiVBc+XB7ppyj7ULDudyEC/B0Hgw4flXAnIhyZBKllzwW/eLB5XPPV1C yKDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=suUfujzWdFjqH2s+YoUsYzVbyOY1lZZXklDFsgzM+q8=; b=A/C+MYKeJ/1mk6HbQ94CSsgUZUOHf8TbtGqPXUodAVTXYHG4Ab3uQvI1NQ2IoNtvYX OmGXS98KQAlK9XpUPvhxdS4TepWoHR2berpI3IIzcQujHLJMGLImcV1wYhuOozxcebWT jxkWji9g0YeHYgJ54qhwDNy1uiQsUTjyd9TLyXXhq1gLuRTZSGF86obTcSaQJWxUVVrW 51mIbb2s4SqQSJQ0vhmqoZOcqa1dcU/y54kh2K+5sVuCZqdyQXUNEGO0fHCTLBZ1y/gs IenCtKu068z2VYl3fwOYXN6s4sgQ6TKucCVG6iez20ey1wZB0Lg/Y5cXvPqaga2kIsqU LuoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=LVl9B75i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/svm/pmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index e5c69062a909..c03958063a76 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -170,6 +170,9 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) else pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS; + pmu->nr_arch_gp_counters = min_t(unsigned int, pmu->nr_arch_gp_counters, + kvm_pmu_cap.num_counters_gp); + pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1; pmu->reserved_bits = 0xfffffff000280000ull; pmu->raw_event_mask = AMD64_RAW_EVENT_MASK; From patchwork Tue May 30 06:04:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 100558 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1963230vqr; Mon, 29 May 2023 23:06:55 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6Hu77CSUuWE3vv8nYFQFrKUIAU8EGbKy1YWAvzLvQgt9waC5zWbfPPkm8X/J4E1LROeag1 X-Received: by 2002:a17:90a:a002:b0:24e:1b19:867f with SMTP id q2-20020a17090aa00200b0024e1b19867fmr1502442pjp.37.1685426815545; Mon, 29 May 2023 23:06:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685426815; cv=none; d=google.com; s=arc-20160816; b=PJhFOln2FU4zKlYDTGyf6xn8GwjFxFNrIWf3uQObZ6yZ6PjXaGmdFRZh0jXt4pITEy sPcEckqkhbIVRMAH8BtxBRxK8zntHLhrdGSJv3ZYwjvkFp12vWJQjLRxs2IB0RKfMERG JLlfQPa2voDEhwqwRQblfsqJ/o5OVSrvt79egBcgSRZrOguft3C3+/rv/9/LPTMyFOWq ZchKa1Z+lu/sXhpwaCCR2oJXmVAWX/DZcbLVD4UShdGgpqaM4r0e1TmhKuaNMG5wGV0X PhyG7YxaYBUrYhmyV1HndhuDAAJ4R3FRTgvsoFr3jyE7sSDVCgBBN8aF6j1Mgr78Dwry PW9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=efk2eikpj9mkGblIwh4EqJ49dRC5zifywNghQx+zwtw=; b=P3XWaBXcAtKWc6aQ6UueSbT5E6739EvfFpo13WS6+HBwXotOWJ8BvBivUGWjYgck8A sVcsQtmokEjswiip/6LH5x+YTtroGDcFqgqj1GZisfJMgTy9xi/U+sLLF5dnea2mcbzy R7HlrEvWtKLVIlVzZia4JTI3wq/pj6R4JmzwqnJ8yU8b4R7WTTK5BPvAHNJgv/CtyC6x hQvlGdQxkkzw+POlNUtArERMfeGOK9Q8hv9opLOTzC7UuZbofazKOvMnbguubOACqRBU blydBgZR79QTF4sg6Xn/zJN6xbWab9+egcJIsKTk4ydnl95No4evQhtnEsRa9qPU+xIz niPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=aFtM9vhu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/reverse_cpuid.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index a5717282bb9c..56cbdb24400a 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -15,6 +15,7 @@ enum kvm_only_cpuid_leafs { CPUID_12_EAX = NCAPINTS, CPUID_7_1_EDX, CPUID_8000_0007_EDX, + CPUID_8000_0022_EAX, NR_KVM_CPU_CAPS, NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS, @@ -47,6 +48,9 @@ enum kvm_only_cpuid_leafs { /* CPUID level 0x80000007 (EDX). */ #define KVM_X86_FEATURE_CONSTANT_TSC KVM_X86_FEATURE(CPUID_8000_0007_EDX, 8) +/* CPUID level 0x80000022 (EAX) */ +#define KVM_X86_FEATURE_PERFMON_V2 KVM_X86_FEATURE(CPUID_8000_0022_EAX, 0) + struct cpuid_reg { u32 function; u32 index; @@ -74,6 +78,7 @@ static const struct cpuid_reg reverse_cpuid[] = { [CPUID_7_1_EDX] = { 7, 1, CPUID_EDX}, [CPUID_8000_0007_EDX] = {0x80000007, 0, CPUID_EDX}, [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX}, + [CPUID_8000_0022_EAX] = {0x80000022, 0, CPUID_EAX}, }; /* @@ -108,6 +113,8 @@ static __always_inline u32 __feature_translate(int x86_feature) return KVM_X86_FEATURE_SGX_EDECCSSA; else if (x86_feature == X86_FEATURE_CONSTANT_TSC) return KVM_X86_FEATURE_CONSTANT_TSC; + else if (x86_feature == X86_FEATURE_PERFMON_V2) + return KVM_X86_FEATURE_PERFMON_V2; return x86_feature; } From patchwork Tue May 30 06:04:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 100559 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1963259vqr; Mon, 29 May 2023 23:06:59 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4Hau38ThjKwaVpE+FIJ/1lsnUFfyYACzxsP/yFnpHBgfCc9pqR9DkiGqvDC8wizlNgjL6Z X-Received: by 2002:aa7:88c5:0:b0:63f:ffd:5360 with SMTP id k5-20020aa788c5000000b0063f0ffd5360mr1542480pff.21.1685426819182; Mon, 29 May 2023 23:06:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685426819; cv=none; d=google.com; s=arc-20160816; b=ODCFuKwj1a933I9mpBoeyusaVTN+8iZ79m9hHvxDTR9YRMiVNC9D2bUq3EhsRhjdr8 aHYyG52pzvD318IlsdeU1XeWc8PNthH9A4YdPFSiPNO4WR5UT55q0sDWKqq00iIq/At8 6ta/J9y0pmVbEyyrwXmg+TMNJgU1sWjLriZQ+JSl4+wJMCcB4OQoBSxTo25D+zqZF+mx kA8olqYCEN13fjRf1MrfrJ46Kqkm/B2338xEZkypn8+AELuhZSTP4ogVRS7/rfRC7puP rrKYhZ9xaGYHu7g8Z7yo0+tm60lMt2IBvD0D577ssj0nuWzdC3W8geL+30ewy7BLGkzz rfrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=s/91HAVGLFrzFV7eZ8VaT+4YuRifj/4P8bzLl3nSCng=; b=vzU0eHjio7X6VIw3lutvqfGbkvY23RsOMvEYUfK3vsnbAt7JAZ+zUdhaM9sLvCAWnl EVGdpIkZzpAyUHs8Y0+A1PejN0YqHNkgceIv79HNhUZsJxKYWusjWEk0BkODN44QOaEy 7R0Pv5zhNbdA3qPmLBg+IZXKc+WMnfh/dLUhNHVjralVOu+J1xGaLU1Ec4eM52TV+HbF 9yS6vbPejM6/kLFmfmz9nXEa0meMunEePEr4/GA6C71HQRFMeyuJJ/sCeEeCfuq42i9J I11yKYn7ungIfOFZOiNP1Tk9uGpFyRUVv5NmVWexwkTLTScJlucNlBqFkB0iLoErOLz8 KXJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=CdXJajV2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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In addition to benefiting from the PerfMonV2 functionality in the same way as the host (higher precision), the guest also can reduce the number of vm-exits by lowering the total number of MSRs accesses. In terms of implementation details, amd_is_valid_msr() is resurrected since three newly added MSRs could not be mapped to one vPMC. The possibility of emulating PerfMonV2 on the mainframe has also been eliminated for reasons of precision. Co-developed-by: Sandipan Das Signed-off-by: Sandipan Das Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 24 +++++++++++++++++- arch/x86/kvm/svm/pmu.c | 55 ++++++++++++++++++++++++++++++++++-------- arch/x86/kvm/x86.c | 10 ++++++++ 3 files changed, 78 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 116bc7fe13c6..e17be25de6ca 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -577,11 +577,18 @@ int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) switch (msr) { case MSR_CORE_PERF_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: msr_info->data = pmu->global_status; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + /* Based on the observed HW. */ + fallthrough; case MSR_CORE_PERF_GLOBAL_CTRL: msr_info->data = pmu->global_ctrl; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: + /* Based on the observed HW. */ + fallthrough; case MSR_CORE_PERF_GLOBAL_OVF_CTRL: msr_info->data = 0; break; @@ -599,13 +606,26 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) u64 data = msr_info->data; u64 diff; + /* + * Note, AMD ignores writes to reserved bits and read-only PMU MSRs, + * whereas Intel generates #GP on attempts to write reserved/RO MSRs. + */ switch (msr) { case MSR_CORE_PERF_GLOBAL_STATUS: if (!msr_info->host_initiated || (data & pmu->global_ovf_ctrl_mask)) return 1; /* RO MSR */ + fallthrough; + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: + /* Per PPR, Read-only MSR. Writes are ignored. */ + if (!msr_info->host_initiated) + break; pmu->global_status = data; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + /* Based on the observed HW. */ + data &= ~pmu->global_ctrl_mask; + fallthrough; case MSR_CORE_PERF_GLOBAL_CTRL: if (!kvm_valid_perf_global_ctrl(pmu, data)) return 1; @@ -619,7 +639,9 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_CORE_PERF_GLOBAL_OVF_CTRL: if (data & pmu->global_ovf_ctrl_mask) return 1; - + fallthrough; + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: + /* Based on the observed HW. */ if (!msr_info->host_initiated) pmu->global_status &= ~data; break; diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index c03958063a76..9bcf1dacfd6c 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -94,12 +94,6 @@ static struct kvm_pmc *amd_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, return amd_pmc_idx_to_pmc(vcpu_to_pmu(vcpu), idx & ~(3u << 30)); } -static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) -{ - /* All MSRs refer to exactly one PMC, so msr_idx_to_pmc is enough. */ - return false; -} - static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -111,6 +105,29 @@ static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) return pmc; } +static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + + switch (msr) { + case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: + return pmu->version > 0; + case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: + return guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE); + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: + return pmu->version > 1; + default: + if (msr > MSR_F15H_PERF_CTR5 && + msr < MSR_F15H_PERF_CTL0 + 2 * pmu->nr_arch_gp_counters) + return pmu->version > 1; + break; + } + + return amd_msr_idx_to_pmc(vcpu, msr); +} + static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -164,23 +181,39 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) static void amd_pmu_refresh(struct kvm_vcpu *vcpu) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + union cpuid_0x80000022_ebx ebx; - if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) + pmu->version = 1; + if (guest_cpuid_has(vcpu, X86_FEATURE_PERFMON_V2)) { + pmu->version = 2; + /* + * Note, PERFMON_V2 is also in 0x80000022.0x0, i.e. the guest + * CPUID entry is guaranteed to be non-NULL. + */ + BUILD_BUG_ON(x86_feature_cpuid(X86_FEATURE_PERFMON_V2).function != 0x80000022 || + x86_feature_cpuid(X86_FEATURE_PERFMON_V2).index); + ebx.full = kvm_find_cpuid_entry_index(vcpu, 0x80000022, 0)->ebx; + pmu->nr_arch_gp_counters = ebx.split.num_core_pmc; + } else if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) { pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS_CORE; - else + } else { pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS; + } pmu->nr_arch_gp_counters = min_t(unsigned int, pmu->nr_arch_gp_counters, kvm_pmu_cap.num_counters_gp); + if (pmu->version > 1) { + pmu->global_ctrl_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1); + pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask; + } + pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1; pmu->reserved_bits = 0xfffffff000280000ull; pmu->raw_event_mask = AMD64_RAW_EVENT_MASK; - pmu->version = 1; /* not applicable to AMD; but clean them to prevent any fall out */ pmu->counter_bitmask[KVM_PMC_FIXED] = 0; pmu->nr_arch_fixed_counters = 0; - pmu->global_status = 0; bitmap_set(pmu->all_valid_pmc_idx, 0, pmu->nr_arch_gp_counters); } @@ -211,6 +244,8 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu) pmc_stop_counter(pmc); pmc->counter = pmc->prev_counter = pmc->eventsel = 0; } + + pmu->global_ctrl = pmu->global_status = 0; } struct kvm_pmu_ops amd_pmu_ops __initdata = { diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c0778ca39650..abfba3cae0ba 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1483,6 +1483,10 @@ static const u32 msrs_to_save_pmu[] = { MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, + + MSR_AMD64_PERF_CNTR_GLOBAL_CTL, + MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, + MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, }; static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) + @@ -7150,6 +7154,12 @@ static void kvm_probe_msr_to_save(u32 msr_index) kvm_pmu_cap.num_counters_fixed) return; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: + if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) + return; 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Bit 0 of EAX indicates support for Performance Monitoring Version 2 (PerfMonV2) features. If found to be set during PMU initialization, the EBX bits of the same CPUID function can be used to determine the number of available PMCs for different PMU types. Expose the relevant bits via KVM_GET_SUPPORTED_CPUID so that guests can make use of the PerfMonV2 features. Co-developed-by: Sandipan Das Signed-off-by: Sandipan Das Signed-off-by: Like Xu --- arch/x86/kvm/cpuid.c | 28 +++++++++++++++++++++++++++- arch/x86/kvm/svm/svm.c | 4 ++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 61bc71882f07..0e5584f4acd7 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -734,6 +734,10 @@ void kvm_set_cpu_caps(void) F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ ); + kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX, + F(PERFMON_V2) + ); + /* * Synthesize "LFENCE is serializing" into the AMD-defined entry in * KVM's supported CPUID if the feature is reported as supported by the @@ -1128,7 +1132,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) entry->edx = 0; break; case 0x80000000: - entry->eax = min(entry->eax, 0x80000021); + entry->eax = min(entry->eax, 0x80000022); /* * Serializing LFENCE is reported in a multitude of ways, and * NullSegClearsBase is not reported in CPUID on Zen2; help @@ -1233,6 +1237,28 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) entry->ebx = entry->ecx = entry->edx = 0; cpuid_entry_override(entry, CPUID_8000_0021_EAX); break; + /* AMD Extended Performance Monitoring and Debug */ + case 0x80000022: { + union cpuid_0x80000022_ebx ebx; + + entry->ecx = entry->edx = 0; + if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) { + entry->eax = entry->ebx; + break; + } + + cpuid_entry_override(entry, CPUID_8000_0022_EAX); + + if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) + ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp; + else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) + ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE; + else + ebx.split.num_core_pmc = AMD64_NUM_COUNTERS; + + entry->ebx = ebx.full; + break; + } /*Add support for Centaur's CPUID instruction*/ case 0xC0000000: /*Just support up to 0xC0000004 now*/ diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index d9669e3cc00a..ff48cdea1fbf 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5036,6 +5036,10 @@ static __init void svm_set_cpu_caps(void) kvm_pmu_cap.num_counters_gp); else kvm_cpu_cap_check_and_set(X86_FEATURE_PERFCTR_CORE); + + if (kvm_pmu_cap.version != 2 || + !kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) + kvm_cpu_cap_clear(X86_FEATURE_PERFMON_V2); } /* CPUID 0x8000001F (SME/SEV features) */