From patchwork Mon May 29 22:09:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hari Nagalla X-Patchwork-Id: 100427 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1794174vqr; Mon, 29 May 2023 15:15:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7stUhp8lVPPPYHWnkyu1jNv0hRKO3SpiXI8vFD9gKxGxLCFkM0CWEVvrqQpJKaRdE0n8B5 X-Received: by 2002:a05:6a21:6806:b0:10c:6:61d1 with SMTP id wr6-20020a056a21680600b0010c000661d1mr259013pzb.39.1685398549382; Mon, 29 May 2023 15:15:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685398549; cv=none; d=google.com; s=arc-20160816; b=kYyxM+WNh8iTHJlun3yOu9ALeSavXA64dOTheWJm9yhc0EY78/5HA0G6Ag5+nYbCen 0uBbT5d1/KDO2/WQ0coOJIwUDQYRRzc2fZyEzhWMZXDjJSVTGw8NNGBdC8EK8MYLtXrt kdPop3wKR6qKCJkn0H6icyA0vOLlDbMGGUI9serHp3UxQQh4gRskq5cINQM1YLlUmBgU hUehwAY3HuHELgZ1rcKI8XGFEi9UtZurZv+LIPbWBJILUVuSGWtmAMHoBz+63Mx1DDp4 m+oPbnepINtODG+pUdeOWDoklou2jZALBquaCTbDgtJZm7fm0/5S6HOh9LRjF6G5DJLr rXmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=4GoX22drmO73L8E/GXzSJcPn8z0nW5KE05z3F6JvHOA=; b=EDa+b9finioYqbJE14TY3HLmDu62wwAngsCWa4EjMqWoJZRHdKlBoy4EoVRcGf8gFU ylNnoLVUOmJ4PRFBQf4VQmUUNWdswqHnb/ot6LIitpgsUSZgbTyaakYQDl6ovGmtxfCj mPDjC1lBkFjUtophDNAS1+X6AFNuD3D3oboFeRfL/818qrd+msT0UJLxAf/30c39B0YG UnwQLHBIQ6w7lk6Of0QQJm75oxoUcOvbj8MYkjwIEpP30WMQq03Lj+//fDYSew6BLXUk oNSTwvGNJqodX84obY9zC1upeQXJzLv8nw1aWidDIZcNxDzNJOIathZwf7I+RtI0JG39 dLaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=H6P4SID8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a5-20020a637045000000b0053094305b52si4752803pgn.475.2023.05.29.15.15.37; Mon, 29 May 2023 15:15:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=H6P4SID8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229765AbjE2WKD (ORCPT + 99 others); Mon, 29 May 2023 18:10:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229531AbjE2WJ7 (ORCPT ); Mon, 29 May 2023 18:09:59 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56EF6D9; Mon, 29 May 2023 15:09:57 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 34TM9g9J083735; Mon, 29 May 2023 17:09:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685398182; bh=4GoX22drmO73L8E/GXzSJcPn8z0nW5KE05z3F6JvHOA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=H6P4SID8SFe1P4qEuT7B6oBwWms+C4SrQHEWRwZ8iVGFtutRvWco0pUzhZqE3yWGX eVmkzWHWWJlFb6t9DATLVIN8w62gykXaRc057fuMBKrLhyJCEndo1TlXu+RezaHyfC 8oVnOc43ccEwnoWda2TlvtZJK4PjderynTTyopgM= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 34TM9gYD000485 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 May 2023 17:09:42 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 May 2023 17:09:42 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 May 2023 17:09:42 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 34TM9fep022028; Mon, 29 May 2023 17:09:42 -0500 From: Hari Nagalla To: , CC: , , , , , , Subject: [PATCH 1/3] arm64: dts: ti: k3-j721s2-main: Add R5F and C7x remote processsor nodes Date: Mon, 29 May 2023 17:09:39 -0500 Message-ID: <20230529220941.10801-2-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230529220941.10801-1-hnagalla@ti.com> References: <20230529220941.10801-1-hnagalla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767268469109936271?= X-GMAIL-MSGID: =?utf-8?q?1767268469109936271?= The J721S2 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters in MAIN voltage domain. Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory, but otherwise are functionally similar to those on J721E SoCs. Add the DT nodes for the MAIN domain R5F cluster/subsystems, the two R5F cores are added as child nodes to each of the R5F cluster nodes. The clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if desired: MAIN R5FSS0 Core0: j721s2-main-r5f0_0-fw (both in LockStep & Split modes) MAIN R5FSS0 Core1: j721s2-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j721s2-main-r5f1_0-fw (both in LockStep & Split modes) MAIN R5FSS1 Core1: j721s2-main-r5f1_1-fw (needed only in Split mode) The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain. The C71x DSPs are 64 bit machine with fixed and floating point DSP operations. Similar to the R5F remote cores, the inter-processor communication between the main A72 cores and these DSP cores is achieved through shared memory and Mailboxes. The following firmware names are used by default for these DSP cores, and can be overridden in a board dts file if desired: MAIN C71_0 : j721s2-c71_0-fw MAIN C71_1 : j721s2-c71_1-fw Signed-off-by: Hari Nagalla --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 128 +++++++++++++++++---- 1 file changed, 104 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 2dd7865f7654..361aa6b24b22 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -463,7 +463,6 @@ mailbox0_cluster0: mailbox@31f80000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -473,7 +472,6 @@ mailbox0_cluster1: mailbox@31f81000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -483,7 +481,6 @@ mailbox0_cluster2: mailbox@31f82000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -493,7 +490,6 @@ mailbox0_cluster3: mailbox@31f83000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -503,7 +499,6 @@ mailbox0_cluster4: mailbox@31f84000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -513,7 +508,6 @@ mailbox0_cluster5: mailbox@31f85000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -523,7 +517,6 @@ mailbox0_cluster6: mailbox@31f86000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -533,7 +526,6 @@ mailbox0_cluster7: mailbox@31f87000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -543,7 +535,6 @@ mailbox0_cluster8: mailbox@31f88000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -553,7 +544,6 @@ mailbox0_cluster9: mailbox@31f89000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -563,7 +553,6 @@ mailbox0_cluster10: mailbox@31f8a000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -573,7 +562,6 @@ mailbox0_cluster11: mailbox@31f8b000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster0: mailbox@31f90000 { @@ -583,7 +571,6 @@ mailbox1_cluster0: mailbox@31f90000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster1: mailbox@31f91000 { @@ -593,7 +580,6 @@ mailbox1_cluster1: mailbox@31f91000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster2: mailbox@31f92000 { @@ -603,7 +589,6 @@ mailbox1_cluster2: mailbox@31f92000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster3: mailbox@31f93000 { @@ -613,7 +598,6 @@ mailbox1_cluster3: mailbox@31f93000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster4: mailbox@31f94000 { @@ -623,7 +607,6 @@ mailbox1_cluster4: mailbox@31f94000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster5: mailbox@31f95000 { @@ -633,7 +616,6 @@ mailbox1_cluster5: mailbox@31f95000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster6: mailbox@31f96000 { @@ -643,7 +625,6 @@ mailbox1_cluster6: mailbox@31f96000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster7: mailbox@31f97000 { @@ -653,7 +634,6 @@ mailbox1_cluster7: mailbox@31f97000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster8: mailbox@31f98000 { @@ -663,7 +643,6 @@ mailbox1_cluster8: mailbox@31f98000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster9: mailbox@31f99000 { @@ -673,7 +652,6 @@ mailbox1_cluster9: mailbox@31f99000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster10: mailbox@31f9a000 { @@ -683,7 +661,6 @@ mailbox1_cluster10: mailbox@31f9a000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; mailbox1_cluster11: mailbox@31f9b000 { @@ -693,7 +670,6 @@ mailbox1_cluster11: mailbox@31f9b000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; - status = "disabled"; }; main_ringacc: ringacc@3c000000 { @@ -1102,4 +1078,108 @@ main_spi7: spi@2170000 { clocks = <&k3_clks 346 1>; status = "disabled"; }; + + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5c00000 0x00010000>, + <0x5c10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <279>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 279 1>; + firmware-name = "j721s2-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5d00000 0x00010000>, + <0x5d10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <280>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 280 1>; + firmware-name = "j721s2-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5e00000 0x00010000>, + <0x5e10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <281>; + ti,sci-proc-ids = <0x08 0xff>; + resets = <&k3_reset 281 1>; + firmware-name = "j721s2-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5f00000 0x00010000>, + <0x5f10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <282>; + ti,sci-proc-ids = <0x09 0xff>; + resets = <&k3_reset 282 1>; + firmware-name = "j721s2-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + c71_0: dsp@64800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <8>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 8 1>; + firmware-name = "j721s2-c71_0-fw"; + }; + + c71_1: dsp@65800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x65800000 0x00 0x00080000>, + <0x00 0x65e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <11>; + ti,sci-proc-ids = <0x31 0xff>; + resets = <&k3_reset 11 1>; + firmware-name = "j721s2-c71_1-fw"; + }; }; From patchwork Mon May 29 22:09:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hari Nagalla X-Patchwork-Id: 100434 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1795069vqr; Mon, 29 May 2023 15:18:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4DKvYdY7R6s2phHxilq5M9e6NSE++Gtlt9mJdkL3f0yaO6j6wQRcANYoqHi4LGFuWDPYcX X-Received: by 2002:a05:6a20:3c91:b0:103:8c8b:c689 with SMTP id b17-20020a056a203c9100b001038c8bc689mr377574pzj.51.1685398703295; Mon, 29 May 2023 15:18:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685398703; cv=none; d=google.com; s=arc-20160816; b=m819pbLd3lNIrU+FT6mbQnFn93QMRD2i+x+W9NHhGt5XQ9YG/bi7FKS9B++KA1fGH2 jfi93x904Wplhe+gVjAuDNDBoe2cyqPY43oJWcSBic58bUOtIYX9dkgVpTqumXUxNFkY UHirFwOGjm2rGj/kylHmPVGCOqQx/m6kHTD980ZsvIPbEVEzQfYavfzzCWqGK/NMjVfS ge+XgP1Xic6a7scc85nAUSGMyuFUrxr/pV8vKo0t2qXiwrF6HAJ/TSiDw+ojW7PCdpLK zEc7ODsuLiPdAyZp3s3sslrwhzNQcuQZs8sm3UyGKCpWXojt5ZgZotgB6R22f1jT5udz +Abg== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d190-20020a621dc7000000b0064f3917aed4si572267pfd.93.2023.05.29.15.18.09; Mon, 29 May 2023 15:18:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vCTER+yw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229736AbjE2WKA (ORCPT + 99 others); Mon, 29 May 2023 18:10:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229453AbjE2WJ6 (ORCPT ); Mon, 29 May 2023 18:09:58 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE44CCD; Mon, 29 May 2023 15:09:56 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 34TM9gsk003201; Mon, 29 May 2023 17:09:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685398182; bh=Run12w0sl7uLPkhoC8xjqaVEeCThtmawJaTZRM6Qils=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vCTER+ywSTC3+le2dJOHDE16wtbg25iarJRErJ+gp3YcyyizhtA90g6Q5+VRR8deL MMaOwckNWSwlc9/d0zWTW43RBmiLUVQ7W/BjI86tOQaqOn1IlHcTEypybNXpzPtro/ AjClVmywbyJwUK53qvkdt3zV6vNGk0wkMtgaInsk= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 34TM9gjD011322 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 May 2023 17:09:42 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 May 2023 17:09:42 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 May 2023 17:09:42 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 34TM9gmE026454; Mon, 29 May 2023 17:09:42 -0500 From: Hari Nagalla To: , CC: , , , , , , Subject: [PATCH 2/3] arm64: dts: ti: k3-j721s2-mcu: Add R5F cluster nodes Date: Mon, 29 May 2023 17:09:40 -0500 Message-ID: <20230529220941.10801-3-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230529220941.10801-1-hnagalla@ti.com> References: <20230529220941.10801-1-hnagalla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767268631012141208?= X-GMAIL-MSGID: =?utf-8?q?1767268631012141208?= The J721S2 SoCs have a dual-core Arm Cortex-R5F processor (R5FSS) subsystems/cluster in MCU voltage domain. It can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory, but otherwise are functionally similar to those on J721E SoCs. Add the DT nodes for the MCU domain R5F cluster/subsystem, the two R5F cores are added as child nodes to each of the R5F cluster nodes. The clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if desired: MCU R5FSS0 Core0: j721s2-mcu-r5f0_0-fw (both in LockStep and Split modes) MCU R5FSS0 Core1: j721s2-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by: Hari Nagalla --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index a353705a7463..601570f12812 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -379,4 +379,44 @@ adc { compatible = "ti,am3359-adc"; }; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <284>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 284 1>; + firmware-name = "j721s2-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41400000 0x00010000>, + <0x41410000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <285>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 285 1>; + firmware-name = "j721s2-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; From patchwork Mon May 29 22:09:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hari Nagalla X-Patchwork-Id: 100431 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1794577vqr; Mon, 29 May 2023 15:16:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5XgJJgQuFgGsxU2TjUBzpRAeXus2TOwM1p38hZB8XeVsSKhgs31pgmjlGwehNt0LTof6sj X-Received: by 2002:a17:90a:3802:b0:24d:ebf8:b228 with SMTP id w2-20020a17090a380200b0024debf8b228mr495639pjb.19.1685398612871; Mon, 29 May 2023 15:16:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685398612; cv=none; d=google.com; s=arc-20160816; b=YEyHosaJfa+5fzrjFpKu7eP5dFnaNUh2Y9PHD1PqWA8dZYNEgLh28eiLKirCMNoTOY eCGVndnxgp8rA1U4vaZsuXRxa1J/+Z/lZvR0BUzYM1n31fL4zxdopODOWv8l17V4j3uX OZ3Rc2DlPcjDEv8dgx6IAGKyX59y9vWJeEG0sTAepDjuuY6JATyIAYs+8bULHVlNerpX whaK+b/Br2rttYXr5RWZg/rAv8xYnqdZlvhTZl/GzbBd99uVJeH14O/ibK1IuU8yLAO3 YYPH6Vn8h61ngub6cvAFZfEPQecge+oS6mzqUjJBWZu+DUV4R74Gbo+5x0UDreQpD/d+ Wxhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=TzQousu8w/ZA1lVLtffFeUE4xt9hfCQllOX0gho+6b8=; b=rtGFb6OzL5eUrM3jxC+bUkuGY41r++l4wLFLAszF3BPeNWQaRdfXaIK1E5fFRms2ej xJBnPcj1AZzfutHCWXziytAnR7Ap31QzTJIifad9N+Rl9NKi86mszMmHiw72zqchYE5C ikD3esBuOLvB6Oz0ApMLRKCl59uXA/xuF1xnKxz1kq6X+PuoIbsqSCH/B9Uk8MRMNFvV EsiXQ7kJKVzI4RXKiE9y/1xDT4uN9IZF7b2yaVkk6x1U69BAHymFCndTt9qbYly49v9D 0bPmeAjIC1TMzHDMmOmrDVQRUSZlvRUcX/fOcAcuiwhcnoMTGGmHpBvobp92yJfe/D7a HJtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BdadC2q8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p5-20020a637f45000000b00534882d5329si9432730pgn.762.2023.05.29.15.16.38; Mon, 29 May 2023 15:16:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BdadC2q8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229593AbjE2WKM (ORCPT + 99 others); Mon, 29 May 2023 18:10:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229744AbjE2WKA (ORCPT ); Mon, 29 May 2023 18:10:00 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A99DCDC; Mon, 29 May 2023 15:09:58 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 34TM9hn5111607; Mon, 29 May 2023 17:09:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685398183; bh=TzQousu8w/ZA1lVLtffFeUE4xt9hfCQllOX0gho+6b8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BdadC2q8aFcd1WD6JsmVtoIZr/xGrfjApkpTc01DN2fkw/ykJaou//AT3prHLQgQ+ NyEpXnTnFRzOc3EV5V9hlVlYi/iteYB6jUAoxBbphvUNNOdFTVBWFz3GGM2BOUnf0O 6fHMnlL3i+omxEcV9yvqLjcHe6GgnGLV36SxkdWk= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 34TM9hbU072153 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 May 2023 17:09:43 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 May 2023 17:09:42 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 May 2023 17:09:42 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 34TM9gEr036626; Mon, 29 May 2023 17:09:42 -0500 From: Hari Nagalla To: , CC: , , , , , , Subject: [PATCH 3/3] arm64: dts : ti: k3-j721s2-som-p0: Add DDR carveout memory nodes for R5F and C71x DSPs Date: Mon, 29 May 2023 17:09:41 -0500 Message-ID: <20230529220941.10801-4-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230529220941.10801-1-hnagalla@ti.com> References: <20230529220941.10801-1-hnagalla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767268535757730890?= X-GMAIL-MSGID: =?utf-8?q?1767268535757730890?= Two carveout reserved memory nodes each have been added for each of the R5F and C71x remote processor devices/DSP/DSPs within both the MCU and MAIN domains for the TI J721S2 EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables either to allocate the memory for firmware memory segments. The C71x DSP processor does support a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. Note that the R5F1 carveouts are needed only if the R5F cluster is running in Split (non-LockStep) mode. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Hari Nagalla --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 286 +++++++++++++++++++ 1 file changed, 286 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 6930efff8a5a..d1ca00c83d1c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -29,6 +29,108 @@ secure_ddr: optee@9e800000 { alignment = <0x1000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; }; transceiver0: can-phy0 { @@ -79,3 +181,187 @@ &main_mcan16 { pinctrl-names = "default"; phys = <&transceiver0>; }; + +&mailbox0_cluster0 { + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; + +&mailbox1_cluster0 { + status = "disabled"; +}; + +&mailbox1_cluster1 { + status = "disabled"; +}; + +&mailbox1_cluster2 { + status = "disabled"; +}; + +&mailbox1_cluster3 { + status = "disabled"; +}; + +&mailbox1_cluster4 { + status = "disabled"; +}; + +&mailbox1_cluster5 { + status = "disabled"; +}; + +&mailbox1_cluster6 { + status = "disabled"; +}; + +&mailbox1_cluster7 { + status = "disabled"; +}; + +&mailbox1_cluster8 { + status = "disabled"; +}; + +&mailbox1_cluster9 { + status = "disabled"; +}; + +&mailbox1_cluster10 { + status = "disabled"; +}; + +&mailbox1_cluster11 { + status = "disabled"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&c71_0 { + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +};