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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DB9PR04MB9820.eurprd04.prod.outlook.com (2603:10a6:10:4c3::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.22; Mon, 29 May 2023 20:05:14 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c%7]) with mapi id 15.20.6433.022; Mon, 29 May 2023 20:05:14 +0000 From: Frank Li To: frank.li@nxp.com, krzysztof.kozlowski+dt@linaro.org, peng.fan@nxp.com, vkoul@kernel.org Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, imx@lists.linux.dev, joy.zou@nxp.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, shenwei.wang@nxp.com Subject: [PATCH v2 01/12] dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c Date: Mon, 29 May 2023 16:04:42 -0400 Message-Id: <20230529200453.1423796-2-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529200453.1423796-1-Frank.Li@nxp.com> References: <20230529200453.1423796-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0161.namprd03.prod.outlook.com (2603:10b6:a03:338::16) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB9PR04MB9820:EE_ X-MS-Office365-Filtering-Correlation-Id: df4ce555-58e9-4535-977f-08db6080043c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Global export is unnecessary. This commit removes all EXPORT_SYMBOL_GPL in fsl-edma-common.c, and renames fsl-edma.c and mcf-edma.c to maintain the same final module names as before, thereby simplifying the codebase. Signed-off-by: Frank Li Reviewed-by: Peng Fan --- drivers/dma/Makefile | 6 ++++-- drivers/dma/fsl-edma-common.c | 18 ------------------ drivers/dma/{fsl-edma.c => fsl-edma-main.c} | 0 drivers/dma/{mcf-edma.c => mcf-edma-main.c} | 0 4 files changed, 4 insertions(+), 20 deletions(-) rename drivers/dma/{fsl-edma.c => fsl-edma-main.c} (100%) rename drivers/dma/{mcf-edma.c => mcf-edma-main.c} (100%) diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index a4fd1ce29510..7f3d62c9dee2 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -32,8 +32,10 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_DW_EDMA) += dw-edma/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o -obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o -obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o +fsl-edma-objs := fsl-edma-main.o fsl-edma-common.o +obj-$(CONFIG_FSL_EDMA) += fsl-edma.o +mcf-edma-objs := mcf-edma-main.o fsl-edma-common.o +obj-$(CONFIG_MCF_EDMA) += mcf-edma.o obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o obj-$(CONFIG_HISI_DMA) += hisi_dma.o diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index a06a1575a2a5..ce8d7c9eaf77 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -75,7 +75,6 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); } } -EXPORT_SYMBOL_GPL(fsl_edma_disable_request); static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr, u32 off, u32 slot, bool enable) @@ -126,7 +125,6 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, else mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable); } -EXPORT_SYMBOL_GPL(fsl_edma_chan_mux); static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) { @@ -155,7 +153,6 @@ void fsl_edma_free_desc(struct virt_dma_desc *vdesc) fsl_desc->tcd[i].ptcd); kfree(fsl_desc); } -EXPORT_SYMBOL_GPL(fsl_edma_free_desc); int fsl_edma_terminate_all(struct dma_chan *chan) { @@ -172,7 +169,6 @@ int fsl_edma_terminate_all(struct dma_chan *chan) vchan_dma_desc_free_list(&fsl_chan->vchan, &head); return 0; } -EXPORT_SYMBOL_GPL(fsl_edma_terminate_all); int fsl_edma_pause(struct dma_chan *chan) { @@ -188,7 +184,6 @@ int fsl_edma_pause(struct dma_chan *chan) spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); return 0; } -EXPORT_SYMBOL_GPL(fsl_edma_pause); int fsl_edma_resume(struct dma_chan *chan) { @@ -204,7 +199,6 @@ int fsl_edma_resume(struct dma_chan *chan) spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); return 0; } -EXPORT_SYMBOL_GPL(fsl_edma_resume); static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan) { @@ -265,7 +259,6 @@ int fsl_edma_slave_config(struct dma_chan *chan, return 0; } -EXPORT_SYMBOL_GPL(fsl_edma_slave_config); static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, struct virt_dma_desc *vdesc, bool in_progress) @@ -340,7 +333,6 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan, return fsl_chan->status; } -EXPORT_SYMBOL_GPL(fsl_edma_tx_status); static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, struct fsl_edma_hw_tcd *tcd) @@ -520,7 +512,6 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } -EXPORT_SYMBOL_GPL(fsl_edma_prep_dma_cyclic); struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, @@ -589,7 +580,6 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } -EXPORT_SYMBOL_GPL(fsl_edma_prep_slave_sg); struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src, @@ -612,7 +602,6 @@ struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan, return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } -EXPORT_SYMBOL_GPL(fsl_edma_prep_memcpy); void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) { @@ -629,7 +618,6 @@ void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) fsl_chan->status = DMA_IN_PROGRESS; fsl_chan->idle = false; } -EXPORT_SYMBOL_GPL(fsl_edma_xfer_desc); void fsl_edma_issue_pending(struct dma_chan *chan) { @@ -649,7 +637,6 @@ void fsl_edma_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); } -EXPORT_SYMBOL_GPL(fsl_edma_issue_pending); int fsl_edma_alloc_chan_resources(struct dma_chan *chan) { @@ -660,7 +647,6 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan) 32, 0); return 0; } -EXPORT_SYMBOL_GPL(fsl_edma_alloc_chan_resources); void fsl_edma_free_chan_resources(struct dma_chan *chan) { @@ -683,7 +669,6 @@ void fsl_edma_free_chan_resources(struct dma_chan *chan) fsl_chan->tcd_pool = NULL; fsl_chan->is_sw = false; } -EXPORT_SYMBOL_GPL(fsl_edma_free_chan_resources); void fsl_edma_cleanup_vchan(struct dma_device *dmadev) { @@ -695,7 +680,6 @@ void fsl_edma_cleanup_vchan(struct dma_device *dmadev) tasklet_kill(&chan->vchan.task); } } -EXPORT_SYMBOL_GPL(fsl_edma_cleanup_vchan); /* * On the 32 channels Vybrid/mpc577x edma version (here called "v1"), @@ -743,6 +727,4 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma) edma->regs.tcd = edma->membase + EDMA_TCD; } -EXPORT_SYMBOL_GPL(fsl_edma_setup_regs); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma-main.c similarity index 100% rename from drivers/dma/fsl-edma.c rename to drivers/dma/fsl-edma-main.c diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma-main.c similarity index 100% rename from drivers/dma/mcf-edma.c rename to drivers/dma/mcf-edma-main.c From patchwork Mon May 29 20:04:43 2023 Content-Type: text/plain; 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It eliminates the need for manual IRQ freeing during removal. Signed-off-by: Frank Li Reviewed-by: Peng Fan --- drivers/dma/fsl-edma-main.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index e40769666e39..16305bb9a2ef 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -216,17 +216,6 @@ fsl_edma2_irq_init(struct platform_device *pdev, return 0; } -static void fsl_edma_irq_exit( - struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) -{ - if (fsl_edma->txirq == fsl_edma->errirq) { - devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); - } else { - devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); - devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); - } -} - static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) { int i; @@ -427,7 +416,6 @@ static int fsl_edma_remove(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); - fsl_edma_irq_exit(pdev, fsl_edma); fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); of_dma_controller_free(np); dma_async_device_unregister(&fsl_edma->dma_dev); From patchwork Mon May 29 20:04:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 100410 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1742380vqr; Mon, 29 May 2023 13:08:08 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7ByDIFf63wmVBt1mqE2cccol7biLvukrywDvWNfrmNf1n4CZBL0fsAWs3I6dh1T7GqJYYt X-Received: by 2002:a17:90a:d681:b0:255:7cb3:cdc5 with SMTP id x1-20020a17090ad68100b002557cb3cdc5mr228890pju.14.1685390888495; Mon, 29 May 2023 13:08:08 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1685390888; cv=pass; d=google.com; s=arc-20160816; b=Ca1e19zfZPTuQhe25HEIQkAZ9s/CXpJnuAka3Y7MpqDxEmmy7z3jY2VN1Rh6Nt8hnc boYwWKQeh7Ib90d0W0uJ9aQN5MxaW7UroBtBjqgLWbWe53he6WWwtNr936hgyTfvUcFS m0IWGac53Fg/RB4l7tYtuegmJcvKdvxISM27Gxhxv9h3rdYQhpZ0hxtecrO3s/Nf50d/ GTwH1pfkQZykfuRz3L02AlKRd1w4R0N0KtDGNpUJloXkZACKxAg2n1vUOrdQz0JtFl1Z /HudHZF756QpHNzoDeADeMcpt/FC4x7pWee8B5X6SuoTZGarVls460EOa/mqTMzCDbYF uAHQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Z5IwFxfjsLIuwWG9lLuAPQ9Ft0G9NDt16kTGP8ogl6Y=; b=HNN99/u2IS7GjeImEum08uw5GRLUalX7RSrZXgE2Nhs/ZABcf7UPgkmNhNlzNDrFQa YtN3DRWmoPDwYaNkrAzy37NgGQ/J4lAuVxqAXBf747J3hOPp8zvG5GFpWyCWSynd14wu 7Ig49KTjEvMSa4y99U8tsNrpggrU0kOavxzlR8gtMi8Jnako1lZHQvKUDWx+SZKBP29Q kYk8LzQB5VYRunEx4cLWRNU6c7o7cpuTvCXFLyYRkGu0U8oYk7MdnEPOFZeHRAKuxL4M NiZPGfQqljSHSb0tKMYLAgwls2Vasa0nBpxJeiYU7eAwATeLpu22exdRZZDihj0KluGw zs8g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=E2Xz48k0; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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This will facilitate future extensions, making it easier to add more flags to accommodate new versions of the edma IP. Signed-off-by: Frank Li Reviewed-by: Peng Fan --- drivers/dma/fsl-edma-common.c | 2 +- drivers/dma/fsl-edma-common.h | 5 +++-- drivers/dma/fsl-edma-main.c | 6 +++--- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index ce8d7c9eaf77..10dcc1435d37 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -114,7 +114,7 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr; ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; - if (fsl_chan->edma->drvdata->mux_swap) + if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_MUX_SWAP) ch_off += endian_diff[ch_off % 4]; muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 004ec4a6bc86..db137a8c558d 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -144,11 +144,12 @@ enum edma_version { v3, /* 32ch, i.mx7ulp */ }; +#define FSL_EDMA_DRV_HAS_DMACLK BIT(0) +#define FSL_EDMA_DRV_MUX_SWAP BIT(1) struct fsl_edma_drvdata { enum edma_version version; u32 dmamuxs; - bool has_dmaclk; - bool mux_swap; + u32 flags; int (*setup_irq)(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma); }; diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 16305bb9a2ef..f5cf95d185f8 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -233,14 +233,14 @@ static struct fsl_edma_drvdata vf610_data = { static struct fsl_edma_drvdata ls1028a_data = { .version = v1, .dmamuxs = DMAMUX_NR, - .mux_swap = true, + .flags = FSL_EDMA_DRV_MUX_SWAP, .setup_irq = fsl_edma_irq_init, }; static struct fsl_edma_drvdata imx7ulp_data = { .version = v3, .dmamuxs = 1, - .has_dmaclk = true, + .flags = FSL_EDMA_DRV_HAS_DMACLK, .setup_irq = fsl_edma2_irq_init, }; @@ -293,7 +293,7 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_edma_setup_regs(fsl_edma); regs = &fsl_edma->regs; - if (drvdata->has_dmaclk) { + if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma"); if (IS_ERR(fsl_edma->dmaclk)) { dev_err(&pdev->dev, "Missing DMA block clock.\n"); From patchwork Mon May 29 20:04:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 100411 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1742417vqr; Mon, 29 May 2023 13:08:14 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5mx3m2EqmjwQV/AV6axnEddQs/xB9cLfejIc4PsdotdQZMFdxRkoekVTuShe36MYbv+yWs X-Received: by 2002:a17:90b:4a05:b0:256:544a:74c9 with SMTP id kk5-20020a17090b4a0500b00256544a74c9mr180405pjb.25.1685390893793; Mon, 29 May 2023 13:08:13 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1685390893; cv=pass; d=google.com; s=arc-20160816; b=V+K63DJuIPuTkv9+yOBiysYTsZavl3OLSpLScRY3WGQ4gaNeZUACGp9x47VOB+yMxT rP8rkCTBSuNwOL8lNSJPkKjm8CkFlrklB+WLQOE+o7BA6+zjr+DX5uq/z7MgCYZISaDY UwB2ZK11GtklbyxOfPyBZHxj6Su9HiX3yKxxDLAfvDQZ2dLygq9onsiZE4opOQ40VDko NQsrqZaQiZKYiGmpr4ufpyH7I9w6uMK4/lBWoyRRT/zQ/sLy1JcHJZLd3/1MF2jDzmYT euL83uZiPXOQ/B/CD18fz1/HX2Q7ZjWq+tOrEsQDY2G0bgkmTXRtatzjNq0rl5Cd+Ty3 1Yvg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ouCBlwm7fIzHEcTW7UBupyDePR7cnWUmtikSOmu98+k=; b=UFeBuBV4HseoS6y1Fb/CI7TSgNwt/znqkaUhpeHTYeZSohYTa/xwS2jGbrUVcK7Wto k27N27Le0muofCWIMJjTgFAmH+LpxrAAFvnDHnp9e/JC5cIWSDBMEav0YRo/aGrz36Gj e6raC3Jszgr0RAT9EKxVBhzkRhQyg9Xbdo2Gc7AhxiKL8v0tTUJ6p8KZzV0PxZ2PNOvj cTDJ+/86ayPz2ADssG8rJf2Dj5o+yc4Jsva+MF4KEnMP0VH3rd3agS9J3FKmq6yNnxq5 M8gPvn/tjHw5rG9CbYi0BqLZSFwX8QvFTjj7hFP3qjmm3CgnUr1IhK2OxkTzq1S8n48m 7s5w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=SQ+0zEXi; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DB9PR04MB9820.eurprd04.prod.outlook.com (2603:10a6:10:4c3::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.22; Mon, 29 May 2023 20:05:24 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c%7]) with mapi id 15.20.6433.022; Mon, 29 May 2023 20:05:24 +0000 From: Frank Li To: frank.li@nxp.com, krzysztof.kozlowski+dt@linaro.org, peng.fan@nxp.com, vkoul@kernel.org Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, imx@lists.linux.dev, joy.zou@nxp.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, shenwei.wang@nxp.com Subject: [PATCH v2 04/12] dmaengine: fsl-edma: remove v3 from enum edma_version Date: Mon, 29 May 2023 16:04:45 -0400 Message-Id: <20230529200453.1423796-5-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529200453.1423796-1-Frank.Li@nxp.com> References: <20230529200453.1423796-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0161.namprd03.prod.outlook.com (2603:10b6:a03:338::16) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB9PR04MB9820:EE_ X-MS-Office365-Filtering-Correlation-Id: 784fbf76-cff2-4e75-9f5f-08db608009b1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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However, the presence of "v3" in the code is merely a software indication to differentiate between certain chips. To prevent confusion in the future, this commit removes "v3" from the enum edma_version. Signed-off-by: Frank Li --- drivers/dma/fsl-edma-common.c | 2 +- drivers/dma/fsl-edma-common.h | 2 +- drivers/dma/fsl-edma-main.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 10dcc1435d37..e5c7497c1ff3 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -120,7 +120,7 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; slot = EDMAMUX_CHCFG_SOURCE(slot); - if (fsl_chan->edma->drvdata->version == v3) + if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_CONFIG32) mux_configure32(fsl_chan, muxaddr, ch_off, slot, enable); else mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable); diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index db137a8c558d..2f13e687a721 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -141,11 +141,11 @@ struct fsl_edma_desc { enum edma_version { v1, /* 32ch, Vybrid, mpc57x, etc */ v2, /* 64ch Coldfire */ - v3, /* 32ch, i.mx7ulp */ }; #define FSL_EDMA_DRV_HAS_DMACLK BIT(0) #define FSL_EDMA_DRV_MUX_SWAP BIT(1) +#define FSL_EDMA_DRV_CONFIG32 BIT(2) struct fsl_edma_drvdata { enum edma_version version; u32 dmamuxs; diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index f5cf95d185f8..31531b8bde78 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -238,9 +238,9 @@ static struct fsl_edma_drvdata ls1028a_data = { }; static struct fsl_edma_drvdata imx7ulp_data = { - .version = v3, + .version = v1, .dmamuxs = 1, - .flags = FSL_EDMA_DRV_HAS_DMACLK, + .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, .setup_irq = fsl_edma2_irq_init, }; From patchwork Mon May 29 20:04:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 100415 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1748698vqr; Mon, 29 May 2023 13:22:34 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6y4/XREze0P+uIT4jST4CTpJQHpb3d/OorwKvTY/Nu/Vd2T7wovSNBWx9lJidMjSkGYu3n X-Received: by 2002:a17:902:be13:b0:1aa:f78d:97b7 with SMTP id r19-20020a170902be1300b001aaf78d97b7mr189358pls.46.1685391754485; Mon, 29 May 2023 13:22:34 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1685391754; cv=pass; d=google.com; s=arc-20160816; b=fvNzrl8E/xdpgLM6GcOrmWiqnmQSLKOIpNUCwWC3Sp+EGozk5x1w17km9jOY1GuyB6 U+SZdqmKs1AhhI+dpRAcFCQF4/nTaU7RlTAewYyBAn2iw7e4Z/CHqclO6dVEbkWHwqFH E2kTil3MFKq4QH4A0+O6q645kO+/gstCj36Xclu2+L8BVl2oYeLoRmaWa8NZ3EkKOvWv /vZzjjHg1xLC6Oyfq6M0Uj3/fG34AtYHOW1zRXVWM58yXDUJox99ycMVE+gfqKioHvXk eCRUMAhhZQvmbcRLY8/c0cq/Yu6VLo8zdYUN1t4LQidxQ+fuQpMc22hlOFRHBw6WORrk QoXQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=msrt5RHHs6IHX/f7JbgffOTIryNu0J13mXMJS9oOE4A=; b=ioan/liW+ufIovP++DHbJM0jB+Na7Q4y+xH9TIXY7ky/VDNbO5cwJMATOW6DfmBMcY AZdd+U77U0whXmWtn2BQFAmAqmA7h4qqAnGyvKx72SpDZio6AWNM3J5uiEqsUTPcs0I1 hi0xV/iibl3qewBnts4MazZlr0aRAktHb9zMhYAIX45g4d2OGCLEJ6mEjT2sEtj/q4Sg o+MmkkJmzNjIV9ZMtIys1PpccSJSBvRgWyUhdqviW1ozxaycGalFlLP61MCxKfhG9X2f g1+wY5H5Nt1QVJ+ca2jnl2mhwHH1amfcW/rE7HB6DZgDBNfSCUjd6KathMzOBma/sAfI dVIw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=NuEoz7GO; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DB9PR04MB9820.eurprd04.prod.outlook.com (2603:10a6:10:4c3::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.22; Mon, 29 May 2023 20:05:27 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c%7]) with mapi id 15.20.6433.022; Mon, 29 May 2023 20:05:27 +0000 From: Frank Li To: frank.li@nxp.com, krzysztof.kozlowski+dt@linaro.org, peng.fan@nxp.com, vkoul@kernel.org Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, imx@lists.linux.dev, joy.zou@nxp.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, shenwei.wang@nxp.com Subject: [PATCH v2 05/12] dmaengine: fsl-edma: move common IRQ handler to common.c Date: Mon, 29 May 2023 16:04:46 -0400 Message-Id: <20230529200453.1423796-6-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529200453.1423796-1-Frank.Li@nxp.com> References: <20230529200453.1423796-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0161.namprd03.prod.outlook.com (2603:10b6:a03:338::16) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB9PR04MB9820:EE_ X-MS-Office365-Filtering-Correlation-Id: 0567357e-1c7c-4131-e38c-08db60800b84 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This eliminates redundant code, as the both files contains mostly identical code. Signed-off-by: Frank Li --- drivers/dma/fsl-edma-common.c | 26 ++++++++++++++++++++++++++ drivers/dma/fsl-edma-common.h | 7 +++++++ drivers/dma/fsl-edma-main.c | 30 ++---------------------------- drivers/dma/mcf-edma-main.c | 30 ++---------------------------- 4 files changed, 37 insertions(+), 56 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index e5c7497c1ff3..839471c42758 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -42,6 +42,32 @@ #define EDMA_TCD 0x1000 +void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan) +{ + spin_lock(&fsl_chan->vchan.lock); + + if (!fsl_chan->edesc) { + /* terminate_all called before */ + spin_unlock(&fsl_chan->vchan.lock); + return; + } + + if (!fsl_chan->edesc->iscyclic) { + list_del(&fsl_chan->edesc->vdesc.node); + vchan_cookie_complete(&fsl_chan->edesc->vdesc); + fsl_chan->edesc = NULL; + fsl_chan->status = DMA_COMPLETE; + fsl_chan->idle = true; + } else { + vchan_cyclic_callback(&fsl_chan->edesc->vdesc); + } + + if (!fsl_chan->edesc) + fsl_edma_xfer_desc(fsl_chan); + + spin_unlock(&fsl_chan->vchan.lock); +} + static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) { struct edma_regs *regs = &fsl_chan->edma->regs; diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 2f13e687a721..71e19e20f1cb 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -223,6 +223,13 @@ static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd) return container_of(vd, struct fsl_edma_desc, vdesc); } +static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan) +{ + fsl_chan->status = DMA_ERROR; + fsl_chan->idle = true; +} + +void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan); void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan); void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, unsigned int slot, bool enable); diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 31531b8bde78..9c0b6fb4cb8f 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -33,7 +33,6 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) struct fsl_edma_engine *fsl_edma = dev_id; unsigned int intr, ch; struct edma_regs *regs = &fsl_edma->regs; - struct fsl_edma_chan *fsl_chan; intr = edma_readl(fsl_edma, regs->intl); if (!intr) @@ -42,31 +41,7 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) for (ch = 0; ch < fsl_edma->n_chans; ch++) { if (intr & (0x1 << ch)) { edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); - - fsl_chan = &fsl_edma->chans[ch]; - - spin_lock(&fsl_chan->vchan.lock); - - if (!fsl_chan->edesc) { - /* terminate_all called before */ - spin_unlock(&fsl_chan->vchan.lock); - continue; - } - - if (!fsl_chan->edesc->iscyclic) { - list_del(&fsl_chan->edesc->vdesc.node); - vchan_cookie_complete(&fsl_chan->edesc->vdesc); - fsl_chan->edesc = NULL; - fsl_chan->status = DMA_COMPLETE; - fsl_chan->idle = true; - } else { - vchan_cyclic_callback(&fsl_chan->edesc->vdesc); - } - - if (!fsl_chan->edesc) - fsl_edma_xfer_desc(fsl_chan); - - spin_unlock(&fsl_chan->vchan.lock); + fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); } } return IRQ_HANDLED; @@ -86,8 +61,7 @@ static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) if (err & (0x1 << ch)) { fsl_edma_disable_request(&fsl_edma->chans[ch]); edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); - fsl_edma->chans[ch].status = DMA_ERROR; - fsl_edma->chans[ch].idle = true; + fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); } } return IRQ_HANDLED; diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c index ebd8733f72ad..af1b0e8a3021 100644 --- a/drivers/dma/mcf-edma-main.c +++ b/drivers/dma/mcf-edma-main.c @@ -19,7 +19,6 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id) struct fsl_edma_engine *mcf_edma = dev_id; struct edma_regs *regs = &mcf_edma->regs; unsigned int ch; - struct fsl_edma_chan *mcf_chan; u64 intmap; intmap = ioread32(regs->inth); @@ -31,31 +30,7 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id) for (ch = 0; ch < mcf_edma->n_chans; ch++) { if (intmap & BIT(ch)) { iowrite8(EDMA_MASK_CH(ch), regs->cint); - - mcf_chan = &mcf_edma->chans[ch]; - - spin_lock(&mcf_chan->vchan.lock); - - if (!mcf_chan->edesc) { - /* terminate_all called before */ - spin_unlock(&mcf_chan->vchan.lock); - continue; - } - - if (!mcf_chan->edesc->iscyclic) { - list_del(&mcf_chan->edesc->vdesc.node); - vchan_cookie_complete(&mcf_chan->edesc->vdesc); - mcf_chan->edesc = NULL; - mcf_chan->status = DMA_COMPLETE; - mcf_chan->idle = true; - } else { - vchan_cyclic_callback(&mcf_chan->edesc->vdesc); - } - - if (!mcf_chan->edesc) - fsl_edma_xfer_desc(mcf_chan); - - spin_unlock(&mcf_chan->vchan.lock); + fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]); } } @@ -76,8 +51,7 @@ static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id) if (err & BIT(ch)) { fsl_edma_disable_request(&mcf_edma->chans[ch]); iowrite8(EDMA_CERR_CERR(ch), regs->cerr); - mcf_edma->chans[ch].status = DMA_ERROR; - mcf_edma->chans[ch].idle = true; + fsl_edma_err_chan_handler(&mcf_edma->chans[ch]); } } From patchwork Mon May 29 20:04:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 100422 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1749912vqr; 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DB9PR04MB9820.eurprd04.prod.outlook.com (2603:10a6:10:4c3::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.22; Mon, 29 May 2023 20:05:30 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c%7]) with mapi id 15.20.6433.022; Mon, 29 May 2023 20:05:30 +0000 From: Frank Li To: frank.li@nxp.com, krzysztof.kozlowski+dt@linaro.org, peng.fan@nxp.com, vkoul@kernel.org Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, imx@lists.linux.dev, joy.zou@nxp.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, shenwei.wang@nxp.com Subject: [PATCH v2 06/12] dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs() Date: Mon, 29 May 2023 16:04:47 -0400 Message-Id: <20230529200453.1423796-7-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529200453.1423796-1-Frank.Li@nxp.com> References: <20230529200453.1423796-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0161.namprd03.prod.outlook.com (2603:10b6:a03:338::16) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB9PR04MB9820:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d09193a-8fd0-48b9-c565-08db60800d55 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Uses ffs() instead, as it gives identical results. This simplifies the code and avoids adding more similar definitions in future V3 version. Signed-off-by: Frank Li --- drivers/dma/fsl-edma-common.c | 21 ++++++++------------- drivers/dma/fsl-edma-common.h | 10 ---------- 2 files changed, 8 insertions(+), 23 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 839471c42758..659bef4a3b23 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -154,18 +154,13 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) { - switch (addr_width) { - case 1: - return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; - case 2: - return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; - case 4: - return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; - case 8: - return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; - default: - return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; - } + u32 val; + + if (addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) + addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + + val = ffs(addr_width) - 1; + return val | (val << 8); } void fsl_edma_free_desc(struct virt_dma_desc *vdesc) @@ -623,7 +618,7 @@ struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan, /* To match with copy_align and max_seg_size so 1 tcd is enough */ fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst, - EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE, + fsl_edma_get_tcd_attr(DMA_SLAVE_BUSWIDTH_32_BYTES), 32, len, 0, 1, 1, 32, 0, true, true, false); return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 71e19e20f1cb..3991956dbc11 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -29,16 +29,6 @@ #define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3) #define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8) #define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11) -#define EDMA_TCD_ATTR_DSIZE_8BIT 0 -#define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0) -#define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1) -#define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1)) -#define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(2) | BIT(0)) -#define EDMA_TCD_ATTR_SSIZE_8BIT 0 -#define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8) -#define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8) -#define EDMA_TCD_ATTR_SSIZE_64BIT (EDMA_TCD_ATTR_DSIZE_64BIT << 8) -#define EDMA_TCD_ATTR_SSIZE_32BYTE (EDMA_TCD_ATTR_DSIZE_32BYTE << 8) #define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0)) #define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0)) From patchwork Mon May 29 20:04:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 100418 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1749020vqr; Mon, 29 May 2023 13:23:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ55nQA0H0754S3jMNFe34paqEiUrn9wCZohRTpNw0uWbj5qvMK6ORMKQ3Av4t7kDpIDgK6n X-Received: by 2002:a17:902:e74c:b0:1b0:3df1:c293 with SMTP id p12-20020a170902e74c00b001b03df1c293mr319181plf.45.1685391802315; Mon, 29 May 2023 13:23:22 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1685391802; cv=pass; d=google.com; s=arc-20160816; b=fLGUjq9pN8UYp5UCDlF4+M9rJdl0DfoCYmgVaglgRRtUtxLi70E8czvSC9GReq7L8R 5IKdpPYzsa6H+cIWdKLyNEZMOYFcOP/fw/pHfNVA2HeAjJ0wq7Hqw6ZVNo9P3ZxHJ/st FYo6GpsPixZZVqIv7yaRCClXdc1v6Iv0zYIVZ9cN3rubuy4n/Y/LxFhNFk7BkJ4mBv8l OUTTtiT+nAK5bVNYVjSAZ73NOCbI0mhqjZqTVz86oUcjY1s//FQtv8O8ph5O+NX1TH9R lVkcOdujbmis4dAzcn+qbodJPP3H+zB3XstUXHyRgeF4MNidNxQauFqLT1XKvLQvTIhf CsQw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=v3P8AoOS+eHwcaqc5bUfUnf+Uxj1PFHD3YCKbldbyag=; b=gfkbCOVMg5fT+dKDnK1bTr81jiHz7tzasdexZK1+Wwh/snRis8wGJcaLgKoymntqLs 8sxuK1EASTHL2N205Dvk1aXNE2sqtvhw60XnIcIDB2jIlmfhlcIS/KY/Xd8KVckx+whN /Te9BdkicO6W+w9gPQ5PPGo/mMwcCaF/1YQ2m9u0N/QcMi1vy2KBjjFi9HMxkz9HWIkw xPq+C4KiTrGB5a/qw5aMHLtVJt19GNL+39yXCO+NsQCwYcTSr1nJvnvFYkA5Ecazh9w+ GyXl0w5uNsSjXtq3v9a+sLovEup9Ix1y25mF3Mv0EcT0CDq60MTA424eukf15x8QvMiz CA0g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b="oYFWP/zO"; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DB9PR04MB9820.eurprd04.prod.outlook.com (2603:10a6:10:4c3::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.22; Mon, 29 May 2023 20:05:33 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c%7]) with mapi id 15.20.6433.022; Mon, 29 May 2023 20:05:33 +0000 From: Frank Li To: frank.li@nxp.com, krzysztof.kozlowski+dt@linaro.org, peng.fan@nxp.com, vkoul@kernel.org Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, imx@lists.linux.dev, joy.zou@nxp.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, shenwei.wang@nxp.com Subject: [PATCH v2 07/12] dmaengine: fsl-edma: refactor using devm_clk_get_enabled Date: Mon, 29 May 2023 16:04:48 -0400 Message-Id: <20230529200453.1423796-8-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529200453.1423796-1-Frank.Li@nxp.com> References: <20230529200453.1423796-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0161.namprd03.prod.outlook.com (2603:10b6:a03:338::16) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB9PR04MB9820:EE_ X-MS-Office365-Filtering-Correlation-Id: ca88c6b1-5c4b-43b0-5967-08db60800f18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { - fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma"); + fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); if (IS_ERR(fsl_edma->dmaclk)) { dev_err(&pdev->dev, "Missing DMA block clock.\n"); return PTR_ERR(fsl_edma->dmaclk); } - - ret = clk_prepare_enable(fsl_edma->dmaclk); - if (ret) { - dev_err(&pdev->dev, "DMA clk block failed.\n"); - return ret; - } } for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { @@ -293,19 +287,12 @@ static int fsl_edma_probe(struct platform_device *pdev) } sprintf(clkname, "dmamux%d", i); - fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname); + fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); if (IS_ERR(fsl_edma->muxclk[i])) { dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); /* on error: disable all previously enabled clks */ - fsl_disable_clocks(fsl_edma, i); return PTR_ERR(fsl_edma->muxclk[i]); } - - ret = clk_prepare_enable(fsl_edma->muxclk[i]); - if (ret) - /* on error: disable all previously enabled clks */ - fsl_disable_clocks(fsl_edma, i); - } fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); @@ -366,7 +353,6 @@ static int fsl_edma_probe(struct platform_device *pdev) if (ret) { dev_err(&pdev->dev, "Can't register Freescale eDMA engine. (%d)\n", ret); - fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); return ret; } @@ -375,7 +361,6 @@ static int fsl_edma_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma. (%d)\n", ret); dma_async_device_unregister(&fsl_edma->dma_dev); - fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); return ret; } From patchwork Mon May 29 20:04:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 100416 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1748782vqr; Mon, 29 May 2023 13:22:45 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ653aeUgerjX6gusmRfqzPDsvXNNPkqYXPBslgaLiB6PWuPR2RUGltA7MzpGjLYxabOGxZS X-Received: by 2002:a17:90b:4a09:b0:24b:c580:1ab8 with SMTP id kk9-20020a17090b4a0900b0024bc5801ab8mr175200pjb.40.1685391765022; Mon, 29 May 2023 13:22:45 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1685391765; cv=pass; d=google.com; s=arc-20160816; b=TEbIbHMJLq4PQhaA9Rf0yYbMkzaKnHAg7NHu2jny/eAYhZP9NjDhm6pUFKU+zYSh4J HZVpilC30gy4WO2rTIwvS+Vv7iQ1iBnCQy+aslsnnwuVjAlFwjRxMpSg143pXMebZmx/ zBOb+m7h2dGHfzsqiYbIWsAyPJOZRIRq4nltE28pFk7PAD4wm49qHRbGagLSpZJ84sxl Vb9PGJACnwsDExXTOcmxEaKtCBDKnJCIOOMKVEWjWWlvVix1yGCK2ZyhPlH5hBpYjlvC nN0o6nUevEgHjCnETu4n9a+u0hbP2nZaBibROmd716AEZTnCTtm7UkzUJHFH/A+92X4i psQA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZX5uQiZbWlSQBsI7bxXuEwcbNQRhGGX00lAlSQPYFEQ=; b=OYAJfCuuEU13iXGGjtaUcvhVhr/LNuJAQq/lSM/9G9eaVPyPIaNymehKdGYB3ZJX1G wd5J8OHEFEqV5THxdLwzb7cn0kD00McGZZrcL9PjCzuBRlt7jGHjBcGF/CbssIxY3uUU FEIIdAd83s+XJMHWKBCwDQ6ckyjsAMTJAvtSjIwrkZD+Xi4DUj6vuOkJwR0FZnk9Qsyl 9QLAhEnhhUwZOAUbxbU8jFtbFVJe0vcJGfye6+RqgoGeyqRANVG7DkLJfjTEkxnPh5vB sx3S3FgKFRkU82ejoayTqxri6oh303G1yTJ5gEaz69mUswlzTm6wS1PBVMTNeM0m+tG5 6oqQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=oNwp+4s+; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DB9PR04MB9820.eurprd04.prod.outlook.com (2603:10a6:10:4c3::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.22; Mon, 29 May 2023 20:05:36 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c%7]) with mapi id 15.20.6433.022; Mon, 29 May 2023 20:05:36 +0000 From: Frank Li To: frank.li@nxp.com, krzysztof.kozlowski+dt@linaro.org, peng.fan@nxp.com, vkoul@kernel.org Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, imx@lists.linux.dev, joy.zou@nxp.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, shenwei.wang@nxp.com Subject: [PATCH v2 08/12] dmaengine: fsl-edma: move clearing of register interrupt into setup_irq function Date: Mon, 29 May 2023 16:04:49 -0400 Message-Id: <20230529200453.1423796-9-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529200453.1423796-1-Frank.Li@nxp.com> References: <20230529200453.1423796-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0161.namprd03.prod.outlook.com (2603:10b6:a03:338::16) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB9PR04MB9820:EE_ X-MS-Office365-Filtering-Correlation-Id: 82effa4b-9143-4981-ed6b-08db608010da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This should ensure better compatibility with EDMA v3. Signed-off-by: Frank Li --- drivers/dma/fsl-edma-main.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 6126717fc87e..cd734779f2eb 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -113,6 +113,8 @@ fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma { int ret; + edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); + fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); if (fsl_edma->txirq < 0) return fsl_edma->txirq; @@ -154,6 +156,8 @@ fsl_edma2_irq_init(struct platform_device *pdev, int i, ret, irq; int count; + edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); + count = platform_irq_count(pdev); dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); if (count <= 2) { @@ -313,7 +317,6 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_edma_chan_mux(fsl_chan, 0, false); } - edma_writel(fsl_edma, ~0, regs->intl); ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); if (ret) return ret; From patchwork Mon May 29 20:04:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 100421 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1749617vqr; Mon, 29 May 2023 13:24:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4/e82r22SyI674w+QhA9+3N8uhXr7qGnFUzF5tbZMnQh4iDDZcYKIvKaLyPktxc13LsVgm X-Received: by 2002:a05:6a20:1583:b0:10b:71c:20c5 with SMTP id h3-20020a056a20158300b0010b071c20c5mr53803pzj.51.1685391892653; Mon, 29 May 2023 13:24:52 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1685391892; cv=pass; d=google.com; s=arc-20160816; b=zQiXG/MXbNY2R0UcJdbZXxTgmZ5trPBijDOwAM/neZBFsXVosW2N+EwI+BdCJphF8s 6CyrqCfSkmNwXo+MtRHIk/GEsi0qYJsfX/HArQr7QHUVEYzGWMzrPiSvZK0JLASo/48L uy/6u13cfAw7kXXj/rIlmeitmkKZsZ+uk2jp1z6zHo4U/wDEzwQT0LceZcIUwFC7X9JM besYuhny1Ms5881lyPCxvkqsxjr2PoINaWix+XdNC8RyEM9/+kMq5RqPC1cPQWOKHH4s esYkqU5gFiZyrJPGoqhbX0opB3k+qPG8oX1n8opp952M6G8buGIk4i2eB5wTFTNxvaIs zyWw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ISKgrdPrxzKwoDu3CGTHqw8SLWtu6pWcUHBCYREGJL4=; b=AwCr8d/18C5Xnb5uoCsvj60oMc7idbSW5zfl+s3ezhvFU0yo4gOdFfIYkyWHFXBX0N TatLL8Yw3d5JHwlKCQnA7Mm2m3GlB1GL6MeH5aEDL8j1re0ESIS5GZ1OPv/6nOd8uEg8 16CXvKMBz9192FA7fgE4GPqqc0Kb/yybM60o6yc9mPkpykxhOrTQ76pqQx+R495Lasvb 2MYvdogCklAmbL3PRAR8yXLV7BULAqfn5irypsiW2s+RBCKD1h3L5ex+1s2LmBXjNKAS SZtyXi9Unc2KKg1kZBe0GzXqMmXNhhif1kbfLWFx92y3RsosJETuMyF5+OG11IhXVQs/ 9o9Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=CDzKy6qK; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DB9PR04MB9820.eurprd04.prod.outlook.com (2603:10a6:10:4c3::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.22; Mon, 29 May 2023 20:05:39 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c%7]) with mapi id 15.20.6433.022; Mon, 29 May 2023 20:05:39 +0000 From: Frank Li To: frank.li@nxp.com, krzysztof.kozlowski+dt@linaro.org, peng.fan@nxp.com, vkoul@kernel.org Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, imx@lists.linux.dev, joy.zou@nxp.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, shenwei.wang@nxp.com Subject: [PATCH v2 09/12] dmaengine: fsl-edma: refactor chan_name setup and safety Date: Mon, 29 May 2023 16:04:50 -0400 Message-Id: <20230529200453.1423796-10-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529200453.1423796-1-Frank.Li@nxp.com> References: <20230529200453.1423796-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0161.namprd03.prod.outlook.com (2603:10b6:a03:338::16) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB9PR04MB9820:EE_ X-MS-Office365-Filtering-Correlation-Id: 24561677-2850-4824-8fe6-08db608012ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This change anticipates its future use in various locations. For increased safety, sprintf has been replaced with snprintf. In addition, The size of the fsl_chan->name[] array was expanded from 16 to 32. Signed-off-by: Frank Li --- drivers/dma/fsl-edma-common.h | 2 +- drivers/dma/fsl-edma-main.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 3991956dbc11..39b5f903ba87 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -116,7 +116,7 @@ struct fsl_edma_chan { dma_addr_t dma_dev_addr; u32 dma_dev_size; enum dma_data_direction dma_dir; - char chan_name[16]; + char chan_name[32]; }; struct fsl_edma_desc { diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index cd734779f2eb..722ebecdc894 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -175,8 +175,6 @@ fsl_edma2_irq_init(struct platform_device *pdev, if (irq < 0) return -ENXIO; - sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i); - /* The last IRQ is for eDMA err */ if (i == count - 1) ret = devm_request_irq(&pdev->dev, irq, @@ -305,6 +303,9 @@ static int fsl_edma_probe(struct platform_device *pdev) for (i = 0; i < fsl_edma->n_chans; i++) { struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; + snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", + dev_name(&pdev->dev), i); + fsl_chan->edma = fsl_edma; fsl_chan->pm_state = RUNNING; fsl_chan->slave_id = 0; From patchwork Mon May 29 20:04:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 100414 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1748622vqr; Mon, 29 May 2023 13:22:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6/Xwlg+pWVuMJ2T6hNvuvitvDDrB43TblD+8m0fLXjlaPw8r04uUZmFpmzlmALIjbqiOBu X-Received: by 2002:a17:903:1110:b0:1ac:528c:e71 with SMTP id n16-20020a170903111000b001ac528c0e71mr297782plh.18.1685391742707; Mon, 29 May 2023 13:22:22 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1685391742; cv=pass; d=google.com; s=arc-20160816; b=sxKbQ3aHDof75PG0B6VQNMMZyqj3Kd1hwQ1OZOp8sWB/dLiXTNiVPRHTAg9wiLUdSS JnnHJpaunFOCDGKJdBAOJdr7wBJZcuTyLmnPEY+FGZCVMMFYrcQnDiqrbaVil7Ocor6P nDoUIOuBDasKjfLc3PtqsmdKSVRWSHI0zWUeFaAYyaxFLHFccCTLL9lRiwl9TyNZtKUY RMTbMw6DtyNUqUApM1tGiq2T9pFUvl6qrGdxBXqq4g8F9P0kkyMBIpu1aegYc0ptvqD6 LAlrSazVhKm1RB0tPVJKAHIcmEcq05JvYVL5rcOOfBNjhso8FtmbDYVeJxFpxvQgcO13 4DhA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eZQBBtSk4cUImx65qukNzrsozHrl9czSuN5Y3QoTWkY=; b=Hb1v6ZjvVqgJfN1HDDwuBsbl7Rp0imyQCIYVznTDmXFSDWxqM17CCiLvS4uam3a4+t dTgpRR6Ie/2bQxgtewr/OkT9SwT+YqKjJWIO3ZAUBHN6zalsfIt2ARsfeOStmMlUCQhE phLYRAJW5e1vw+JBJ2N5NrxpY8wyhISGJr3usC7Xs5tVaxk5DEYngXrASM+XYWdppKgt x3MK2l5H6B1ZbQRY8NX9FhpWtSFIl0CJRuI48Q0AXZvT7B1ngMAhR3t5vZLrzIvOAC+a +o6hgNj1iqixNuJa94ClmLyRcLv0asW6DXobzICyKnkLqWlqkmPcSnTm51iIvs7sM8AP jLXw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=RC5Cdqja; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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This adjustment reduces the need to reference back to fsl_edma_engine, paving the way for EDMA V3 support. Unified the edma_writel and edma_writew functions for accessing TCD (Transfer Control Descriptor) registers. A new macro is added that can automatically detect whether a 32-bit or 16-bit access should be used based on the structure field definition. This provide better support 64-bit TCD with future v5 version. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202305271951.gmRobs3a-lkp@intel.com/ Signed-off-by: Frank Li --- drivers/dma/fsl-edma-common.c | 38 +++++++++++++---------------------- drivers/dma/fsl-edma-common.h | 22 +++++++++++++++++++- drivers/dma/fsl-edma-main.c | 6 ++++-- drivers/dma/mcf-edma-main.c | 4 +++- 4 files changed, 42 insertions(+), 28 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 659bef4a3b23..d56b100a8358 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -40,8 +40,6 @@ #define EDMA64_ERRH 0x28 #define EDMA64_ERRL 0x2c -#define EDMA_TCD 0x1000 - void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan) { spin_lock(&fsl_chan->vchan.lock); @@ -285,8 +283,6 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, struct virt_dma_desc *vdesc, bool in_progress) { struct fsl_edma_desc *edesc = fsl_chan->edesc; - struct edma_regs *regs = &fsl_chan->edma->regs; - u32 ch = fsl_chan->vchan.chan.chan_id; enum dma_transfer_direction dir = edesc->dirn; dma_addr_t cur_addr, dma_addr; size_t len, size; @@ -301,9 +297,9 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, return len; if (dir == DMA_MEM_TO_DEV) - cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].saddr); + cur_addr = edma_read_tcdreg(fsl_chan, saddr); else - cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].daddr); + cur_addr = edma_read_tcdreg(fsl_chan, daddr); /* figure out the finished and calculate the residue */ for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { @@ -358,9 +354,6 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan, static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, struct fsl_edma_hw_tcd *tcd) { - struct fsl_edma_engine *edma = fsl_chan->edma; - struct edma_regs *regs = &fsl_chan->edma->regs; - u32 ch = fsl_chan->vchan.chan.chan_id; u16 csr = 0; /* @@ -369,23 +362,22 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, * big- or little-endian obeying the eDMA engine model endian, * and this is performed from specific edma_write functions */ - edma_writew(edma, 0, ®s->tcd[ch].csr); + edma_write_tcdreg(fsl_chan, 0, csr); - edma_writel(edma, (s32)tcd->saddr, ®s->tcd[ch].saddr); - edma_writel(edma, (s32)tcd->daddr, ®s->tcd[ch].daddr); + edma_write_tcdreg(fsl_chan, tcd->saddr, saddr); + edma_write_tcdreg(fsl_chan, tcd->daddr, daddr); - edma_writew(edma, (s16)tcd->attr, ®s->tcd[ch].attr); - edma_writew(edma, tcd->soff, ®s->tcd[ch].soff); + edma_write_tcdreg(fsl_chan, tcd->attr, attr); + edma_write_tcdreg(fsl_chan, tcd->soff, soff); - edma_writel(edma, (s32)tcd->nbytes, ®s->tcd[ch].nbytes); - edma_writel(edma, (s32)tcd->slast, ®s->tcd[ch].slast); + edma_write_tcdreg(fsl_chan, tcd->nbytes, nbytes); + edma_write_tcdreg(fsl_chan, tcd->slast, slast); - edma_writew(edma, (s16)tcd->citer, ®s->tcd[ch].citer); - edma_writew(edma, (s16)tcd->biter, ®s->tcd[ch].biter); - edma_writew(edma, (s16)tcd->doff, ®s->tcd[ch].doff); + edma_write_tcdreg(fsl_chan, tcd->citer, citer); + edma_write_tcdreg(fsl_chan, tcd->biter, biter); + edma_write_tcdreg(fsl_chan, tcd->doff, doff); - edma_writel(edma, (s32)tcd->dlast_sga, - ®s->tcd[ch].dlast_sga); + edma_write_tcdreg(fsl_chan, tcd->dlast_sga, dlast_sga); if (fsl_chan->is_sw) { csr = le16_to_cpu(tcd->csr); @@ -393,7 +385,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, tcd->csr = cpu_to_le16(csr); } - edma_writew(edma, (s16)tcd->csr, ®s->tcd[ch].csr); + edma_write_tcdreg(fsl_chan, tcd->csr, csr); } static inline @@ -745,7 +737,5 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma) edma->regs.errh = edma->membase + EDMA64_ERRH; edma->regs.inth = edma->membase + EDMA64_INTH; } - - edma->regs.tcd = edma->membase + EDMA_TCD; } diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 39b5f903ba87..991408d59e3e 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -48,6 +48,8 @@ #define DMAMUX_NR 2 +#define EDMA_TCD 0x1000 + #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ @@ -93,7 +95,6 @@ struct edma_regs { void __iomem *intl; void __iomem *errh; void __iomem *errl; - struct fsl_edma_hw_tcd __iomem *tcd; }; struct fsl_edma_sw_tcd { @@ -117,6 +118,7 @@ struct fsl_edma_chan { u32 dma_dev_size; enum dma_data_direction dma_dir; char chan_name[32]; + struct fsl_edma_hw_tcd __iomem *tcd; }; struct fsl_edma_desc { @@ -160,6 +162,16 @@ struct fsl_edma_engine { struct fsl_edma_chan chans[]; }; +#define edma_read_tcdreg(chan, __name) \ +(sizeof(chan->tcd->__name) == sizeof(u32) ? \ + edma_readl(chan->edma, &chan->tcd->__name) : \ + edma_readw(chan->edma, &chan->tcd->__name)) + +#define edma_write_tcdreg(chan, val, __name) \ +(sizeof(chan->tcd->__name) == sizeof(u32) ? \ + edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) : \ + edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name)) + /* * R/W functions for big- or little-endian registers: * The eDMA controller's endian is independent of the CPU core's endian. @@ -174,6 +186,14 @@ static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr) return ioread32(addr); } +static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr) +{ + if (edma->big_endian) + return ioread16be(addr); + else + return ioread16(addr); +} + static inline void edma_writeb(struct fsl_edma_engine *edma, u8 val, void __iomem *addr) { diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 722ebecdc894..8d1d0100f6e6 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -312,9 +312,11 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_chan->idle = true; fsl_chan->dma_dir = DMA_NONE; fsl_chan->vchan.desc_free = fsl_edma_free_desc; + fsl_chan->tcd = fsl_edma->membase + EDMA_TCD + + i * sizeof(struct fsl_edma_hw_tcd); vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); - edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr); + edma_write_tcdreg(fsl_chan, 0, csr); fsl_edma_chan_mux(fsl_chan, 0, false); } @@ -421,7 +423,7 @@ static int fsl_edma_resume_early(struct device *dev) for (i = 0; i < fsl_edma->n_chans; i++) { fsl_chan = &fsl_edma->chans[i]; fsl_chan->pm_state = RUNNING; - edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr); + edma_write_tcdreg(fsl_chan, 0, csr); if (fsl_chan->slave_id != 0) fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true); } diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c index af1b0e8a3021..d79a04a03fda 100644 --- a/drivers/dma/mcf-edma-main.c +++ b/drivers/dma/mcf-edma-main.c @@ -200,7 +200,9 @@ static int mcf_edma_probe(struct platform_device *pdev) mcf_chan->dma_dir = DMA_NONE; mcf_chan->vchan.desc_free = fsl_edma_free_desc; vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev); - iowrite32(0x0, ®s->tcd[i].csr); + mcf_chan->tcd = mcf_edma->membase + EDMA_TCD + + i * sizeof(struct fsl_edma_hw_tcd); + iowrite32(0x0, &mcf_chan->tcd->csr); } iowrite32(~0, regs->inth); From patchwork Mon May 29 20:04:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 100412 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1742807vqr; Mon, 29 May 2023 13:09:00 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5cB3g3yT9guTNIS5dYFjpOm8MSNUGWQVxh5uS4+MIa5GHfcSzsDnQNwzWJgv66KWS7DKfx X-Received: by 2002:a05:6a00:2451:b0:64b:50:2410 with SMTP id d17-20020a056a00245100b0064b00502410mr633222pfj.19.1685390939821; Mon, 29 May 2023 13:08:59 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1685390939; cv=pass; d=google.com; s=arc-20160816; b=eFiD2vPCdnpghWMiyov+fI+tjUhRP4qeru/xAh91xFimRMRdmki8i3D5jFeCHDMxc4 31/35L0qFUXv0SUvoXjlpb1vKB52Ywxb5yM04ZQyrLxTu900GaVAZt0nG5SQ+Nzw1TVf IsyFSmo7Z3T5MEevlOMfLoB8bEapUAZLVdmLr8CIO24l9/plnKHWpTNT6jBHF5w4O1tD QD+qc5DkHohfEKI6OUEQloc6Fae2Guj0lEsO5oNrJyP8GjcSdaUszF7MAlu85oOuX/Mo JbMk959sneoEgF+92g/mZF+Mj7xq1tRiIFatcMcpJDejT1G8rgXRjftYHxDGDqRIjwgA fohA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6TzhP4HvOLM74JF/VlOrG0EepN1fANdJoX2tycKt5t4=; b=pk5u6Ex5JzhFUuukZHI+C6FzPjtkk9BHDhEOmxksmbldAJ3A0Ovmj9tKMWA7jcb9zR OXSoDCEC3J7TNaQbPfiodFtepn4LGOTyG5Sza+hn3G/D7SjhovsDjtaX4cptX6XHpBbM 18WR2uO8NVN21gCezo0G31pD8bfwSFFJ3+vSD0Doc49qnRQm4PaO7oh1NbpZhIYa7rUZ JaMXNSwK8vrk/u7QL56TxK3BCLBtut5evMMhRixnstfaWs4mqQOZLDAF1CVGy4JHP/Y6 a6iBhZsfVB++qgOyJ7L0KHBPfmRoxOWrtBdDXp/XDIkT2pZg7GQ0lAHPXTdd6r9j+Glg cvZA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=Kf3ra9E4; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DB9PR04MB9820.eurprd04.prod.outlook.com (2603:10a6:10:4c3::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.22; Mon, 29 May 2023 20:05:45 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::4a2a:262e:415f:e41c%7]) with mapi id 15.20.6433.022; Mon, 29 May 2023 20:05:45 +0000 From: Frank Li To: frank.li@nxp.com, krzysztof.kozlowski+dt@linaro.org, peng.fan@nxp.com, vkoul@kernel.org Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, imx@lists.linux.dev, joy.zou@nxp.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, shenwei.wang@nxp.com Subject: [PATCH v2 11/12] dmaengine: fsl-edma: integrate v3 support Date: Mon, 29 May 2023 16:04:52 -0400 Message-Id: <20230529200453.1423796-12-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529200453.1423796-1-Frank.Li@nxp.com> References: <20230529200453.1423796-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0161.namprd03.prod.outlook.com (2603:10b6:a03:338::16) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB9PR04MB9820:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b9a2e5d-33e6-41e5-ca64-08db60801686 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Now, each channel possesses a separate address space, encapsulating all channel-related controls and statuses, including IRQs. There are changes in bit position definitions as well. However, the fundamental control flow remains analogous to the previous versions. EDMA v3 was utilized in imx8qm, imx93, and will be in forthcoming chips. Signed-off-by: Frank Li --- drivers/dma/fsl-edma-common.c | 162 +++++++++++++++++++--- drivers/dma/fsl-edma-common.h | 71 +++++++++- drivers/dma/fsl-edma-main.c | 247 ++++++++++++++++++++++++++++++++-- 3 files changed, 452 insertions(+), 28 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index d56b100a8358..66aa1f54204e 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include "fsl-edma-common.h" @@ -66,12 +68,48 @@ void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan) spin_unlock(&fsl_chan->vchan.lock); } +static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan) +{ + u32 val, flags; + + flags = fsl_edma_drvflags(fsl_chan); + val = edma_readl_chreg(fsl_chan, ch_sbr); + /* Remote/local swapped wrongly on iMX8 QM Audio edma */ + if (flags & FSL_EDMA_DRV_QUIRK_SWAPPED) { + if (!fsl_chan->is_rxchan) + val |= EDMA_V3_CH_SBR_RD; + else + val |= EDMA_V3_CH_SBR_WR; + } else { + if (fsl_chan->is_rxchan) + val |= EDMA_V3_CH_SBR_RD; + else + val |= EDMA_V3_CH_SBR_WR; + } + + if (fsl_chan->is_remote) + val &= ~(EDMA_V3_CH_SBR_RD | EDMA_V3_CH_SBR_WR); + + edma_writel_chreg(fsl_chan, val, ch_sbr); + + if ((flags & (FSL_EDMA_DRV_AXI | FSL_EDMA_DRV_HAS_CHMUX)) && + fsl_chan->srcid && !edma_readl_chreg(fsl_chan, ch_mux)) + edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux); + + val = edma_readl_chreg(fsl_chan, ch_csr); + val |= EDMA_V3_CH_CSR_ERQ; + edma_writel_chreg(fsl_chan, val, ch_csr); +} + static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) { struct edma_regs *regs = &fsl_chan->edma->regs; u32 ch = fsl_chan->vchan.chan.chan_id; - if (fsl_chan->edma->drvdata->version == v1) { + if (fsl_edma_ver(fsl_chan) >= v3) + return fsl_edma3_enable_request(fsl_chan); + + if (fsl_edma_ver(fsl_chan) == v1) { edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); edma_writeb(fsl_chan->edma, ch, regs->serq); } else { @@ -83,12 +121,30 @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) } } +static void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan) +{ + u32 val = edma_readl_chreg(fsl_chan, ch_csr); + u32 flags; + + flags = fsl_edma_drvflags(fsl_chan); + + if ((flags & (FSL_EDMA_DRV_AXI | FSL_EDMA_DRV_HAS_CHMUX)) && + fsl_chan->srcid) + edma_writel_chreg(fsl_chan, 0, ch_mux); + + val &= ~EDMA_V3_CH_CSR_ERQ; + edma_writel_chreg(fsl_chan, val, ch_csr); +} + void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) { struct edma_regs *regs = &fsl_chan->edma->regs; u32 ch = fsl_chan->vchan.chan.chan_id; - if (fsl_chan->edma->drvdata->version == v1) { + if (fsl_edma_ver(fsl_chan) >= v3) + return fsl_edma3_disable_request(fsl_chan); + + if (fsl_edma_ver(fsl_chan) == v1) { edma_writeb(fsl_chan->edma, ch, regs->cerq); edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); } else { @@ -186,6 +242,10 @@ int fsl_edma_terminate_all(struct dma_chan *chan) vchan_get_all_descriptors(&fsl_chan->vchan, &head); spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); vchan_dma_desc_free_list(&fsl_chan->vchan, &head); + + if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_PD) + pm_runtime_allow(fsl_chan->pd_dev); + return 0; } @@ -286,12 +346,16 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, enum dma_transfer_direction dir = edesc->dirn; dma_addr_t cur_addr, dma_addr; size_t len, size; + u32 nbytes = 0; int i; /* calculate the total size in this desc */ - for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) - len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes) - * le16_to_cpu(edesc->tcd[i].vtcd->biter); + for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) { + nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes); + if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE)) + nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes); + len += nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter); + } if (!in_progress) return len; @@ -303,8 +367,12 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, /* figure out the finished and calculate the residue */ for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { - size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes) - * le16_to_cpu(edesc->tcd[i].vtcd->biter); + nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes); + if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE)) + nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes); + + size = nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter); + if (dir == DMA_MEM_TO_DEV) dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); else @@ -389,13 +457,15 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, } static inline -void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, +void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan, + struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, u16 biter, u16 doff, u32 dlast_sga, bool major_int, bool disable_req, bool enable_sg) { + struct dma_slave_config *cfg = &fsl_chan->cfg; u16 csr = 0; - + u32 burst; /* * eDMA hardware SGs require the TCDs to be stored in little * endian format irrespective of the register endian model. @@ -409,6 +479,21 @@ void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, tcd->soff = cpu_to_le16(soff); + if (fsl_chan->is_multi_fifo) { + /* set mloff to support multiple fifo */ + burst = cfg->direction == DMA_DEV_TO_MEM ? + cfg->src_addr_width : cfg->dst_addr_width; + nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-(burst * 4)); + /* enable DMLOE/SMLOE */ + if (cfg->direction == DMA_MEM_TO_DEV) { + nbytes |= EDMA_V3_TCD_NBYTES_DMLOE; + nbytes &= ~EDMA_V3_TCD_NBYTES_SMLOE; + } else { + nbytes |= EDMA_V3_TCD_NBYTES_SMLOE; + nbytes &= ~EDMA_V3_TCD_NBYTES_DMLOE; + } + } + tcd->nbytes = cpu_to_le32(nbytes); tcd->slast = cpu_to_le32(slast); @@ -427,6 +512,12 @@ void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, if (enable_sg) csr |= EDMA_TCD_CSR_E_SG; + if (fsl_chan->is_rxchan) + csr |= EDMA_TCD_CSR_ACTIVE; + + if (fsl_chan->is_sw) + csr |= EDMA_TCD_CSR_START; + tcd->csr = cpu_to_le16(csr); } @@ -466,6 +557,7 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); struct fsl_edma_desc *fsl_desc; dma_addr_t dma_buf_next; + bool major_int = true; int sg_len, i; u32 src_addr, dst_addr, last_sg, nbytes; u16 soff, doff, iter; @@ -509,17 +601,23 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( src_addr = dma_buf_next; dst_addr = fsl_chan->dma_dev_addr; soff = fsl_chan->cfg.dst_addr_width; - doff = 0; - } else { + doff = fsl_chan->is_multi_fifo ? 4 : 0; + } else if (direction == DMA_DEV_TO_MEM) { src_addr = fsl_chan->dma_dev_addr; dst_addr = dma_buf_next; - soff = 0; + soff = fsl_chan->is_multi_fifo ? 4 : 0; doff = fsl_chan->cfg.src_addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr = fsl_chan->cfg.src_addr; + dst_addr = fsl_chan->cfg.dst_addr; + soff = doff = 0; + major_int = false; } - fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr, + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, dst_addr, fsl_chan->attr, soff, nbytes, 0, iter, - iter, doff, last_sg, true, false, true); + iter, doff, last_sg, major_int, false, true); dma_buf_next += period_len; } @@ -568,23 +666,51 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( dst_addr = fsl_chan->dma_dev_addr; soff = fsl_chan->cfg.dst_addr_width; doff = 0; - } else { + } else if (direction == DMA_DEV_TO_MEM) { src_addr = fsl_chan->dma_dev_addr; dst_addr = sg_dma_address(sg); soff = 0; doff = fsl_chan->cfg.src_addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr = fsl_chan->cfg.src_addr; + dst_addr = fsl_chan->cfg.dst_addr; + soff = 0; + doff = 0; } + /* + * Choose the suitable burst length if sg_dma_len is not + * multiple of burst length so that the whole transfer length is + * multiple of minor loop(burst length). + */ + if (sg_dma_len(sg) % nbytes) { + u32 width = (direction == DMA_DEV_TO_MEM) ? doff : soff; + u32 burst = (direction == DMA_DEV_TO_MEM) ? + fsl_chan->cfg.src_maxburst : + fsl_chan->cfg.dst_maxburst; + int j; + + for (j = burst; j > 1; j--) { + if (!(sg_dma_len(sg) % (j * width))) { + nbytes = j * width; + break; + } + } + /* Set burst size as 1 if there's no suitable one */ + if (j == 1) + nbytes = width; + } iter = sg_dma_len(sg) / nbytes; if (i < sg_len - 1) { last_sg = fsl_desc->tcd[(i + 1)].ptcd; - fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, dst_addr, fsl_chan->attr, soff, nbytes, 0, iter, iter, doff, last_sg, false, false, true); } else { last_sg = 0; - fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, dst_addr, fsl_chan->attr, soff, nbytes, 0, iter, iter, doff, last_sg, true, true, false); @@ -609,7 +735,7 @@ struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan, fsl_chan->is_sw = true; /* To match with copy_align and max_seg_size so 1 tcd is enough */ - fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst, + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst, fsl_edma_get_tcd_attr(DMA_SLAVE_BUSWIDTH_32_BYTES), 32, len, 0, 1, 1, 32, 0, true, true, false); diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 991408d59e3e..656ba3591898 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -42,6 +42,11 @@ #define EDMA_TCD_CSR_ACTIVE BIT(6) #define EDMA_TCD_CSR_DONE BIT(7) +#define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0)) +#define EDMA_V3_TCD_NBYTES_MLOFF(x) (x << 10) +#define EDMA_V3_TCD_NBYTES_DMLOE (1 << 30) +#define EDMA_V3_TCD_NBYTES_SMLOE (1 << 31) + #define EDMAMUX_CHCFG_DIS 0x0 #define EDMAMUX_CHCFG_ENBL 0x80 #define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F) @@ -54,6 +59,15 @@ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) + +#define EDMA_V3_CH_SBR_RD BIT(22) +#define EDMA_V3_CH_SBR_WR BIT(21) +#define EDMA_V3_CH_CSR_ERQ BIT(0) +#define EDMA_V3_CH_CSR_EARQ BIT(1) +#define EDMA_V3_CH_CSR_EEI BIT(2) +#define EDMA_V3_CH_CSR_DONE BIT(30) +#define EDMA_V3_CH_CSR_ACTIVE BIT(31) + enum fsl_edma_pm_state { RUNNING = 0, SUSPENDED, @@ -73,6 +87,18 @@ struct fsl_edma_hw_tcd { __le16 biter; }; +struct fsl_edma3_ch_reg { + __le32 ch_csr; + __le32 ch_es; + __le32 ch_int; + __le32 ch_sbr; + __le32 ch_pri; + __le32 ch_mux; + __le32 ch_mattr; /* edma4, reserved for edma3 */ + __le32 ch_reserved; + struct fsl_edma_hw_tcd tcd; +} __packed; + /* * These are iomem pointers, for both v32 and v64. */ @@ -119,6 +145,18 @@ struct fsl_edma_chan { enum dma_data_direction dma_dir; char chan_name[32]; struct fsl_edma_hw_tcd __iomem *tcd; + u32 real_count; + struct work_struct issue_worker; + struct platform_device *pdev; + struct device *pd_dev; + u32 srcid; + struct clk *clk; + int priority; + int hw_chanid; + int txirq; + bool is_rxchan; + bool is_remote; + bool is_multi_fifo; }; struct fsl_edma_desc { @@ -131,16 +169,27 @@ struct fsl_edma_desc { }; enum edma_version { - v1, /* 32ch, Vybrid, mpc57x, etc */ + v1, /* 32ch, Vybrid, mpc57x, imx7ulp etc */ v2, /* 64ch Coldfire */ + v3, /* imx8qm, imx8qxp, imx93 edma3 */ + v4, /* imx93 edma4 */ }; #define FSL_EDMA_DRV_HAS_DMACLK BIT(0) #define FSL_EDMA_DRV_MUX_SWAP BIT(1) #define FSL_EDMA_DRV_CONFIG32 BIT(2) +#define FSL_EDMA_DRV_HAS_PD BIT(3) +#define FSL_EDMA_DRV_HAS_CHCLK BIT(4) +#define FSL_EDMA_DRV_HAS_CHMUX BIT(5) +/* imx8 QM audio edma remote local swapped */ +#define FSL_EDMA_DRV_QUIRK_SWAPPED BIT(6) +#define FSL_EDMA_DRV_AXI BIT(7) + struct fsl_edma_drvdata { enum edma_version version; u32 dmamuxs; + u32 chreg_off; + u32 chreg_space_sz; u32 flags; int (*setup_irq)(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma); @@ -152,6 +201,7 @@ struct fsl_edma_engine { void __iomem *muxbase[DMAMUX_NR]; struct clk *muxclk[DMAMUX_NR]; struct clk *dmaclk; + struct clk *chclk; struct mutex fsl_edma_mutex; const struct fsl_edma_drvdata *drvdata; u32 n_chans; @@ -159,6 +209,7 @@ struct fsl_edma_engine { int errirq; bool big_endian; struct edma_regs regs; + u64 chan_masked; struct fsl_edma_chan chans[]; }; @@ -172,6 +223,14 @@ struct fsl_edma_engine { edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) : \ edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name)) +#define edma_readl_chreg(chan, __name) \ + edma_readl(chan->edma, \ + (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name)) + +#define edma_writel_chreg(chan, val, __name) \ + edma_writel(chan->edma, val, \ + (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name)) + /* * R/W functions for big- or little-endian registers: * The eDMA controller's endian is independent of the CPU core's endian. @@ -228,6 +287,16 @@ static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan) return container_of(chan, struct fsl_edma_chan, vchan.chan); } +static inline int fsl_edma_ver(struct fsl_edma_chan *fsl_chan) +{ + return fsl_chan->edma->drvdata->version; +} + +static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan) +{ + return fsl_chan->edma->drvdata->flags; +} + static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd) { return container_of(vd, struct fsl_edma_desc, vdesc); diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 8d1d0100f6e6..db50d2fadb0f 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -18,9 +18,15 @@ #include #include #include +#include +#include #include "fsl-edma-common.h" +#define ARGS_RX BIT(0) +#define ARGS_REMOTE BIT(1) +#define ARGS_MULTI_FIFO BIT(2) + static void fsl_edma_synchronize(struct dma_chan *chan) { struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); @@ -47,6 +53,22 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) return IRQ_HANDLED; } +static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) +{ + struct fsl_edma_chan *fsl_chan = dev_id; + unsigned int intr; + + intr = edma_readl_chreg(fsl_chan, ch_int); + if (!intr) + return IRQ_HANDLED; + + edma_writel_chreg(fsl_chan, 1, ch_int); + + fsl_edma_tx_chan_handler(fsl_chan); + + return IRQ_HANDLED; +} + static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) { struct fsl_edma_engine *fsl_edma = dev_id; @@ -108,6 +130,52 @@ static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, return NULL; } +static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; + struct dma_chan *chan, *_chan; + struct fsl_edma_chan *fsl_chan; + int i; + + if (dma_spec->args_count != 3) + return NULL; + + mutex_lock(&fsl_edma->fsl_edma_mutex); + list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, + device_node) { + + if (chan->client_count) + continue; + + fsl_chan = to_fsl_edma_chan(chan); + i = fsl_chan - fsl_edma->chans; + if (fsl_edma->drvdata->dmamuxs == 0 && i == dma_spec->args[0]) { + chan = dma_get_slave_channel(chan); + chan->device->privatecnt++; + fsl_chan->priority = dma_spec->args[1]; + fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; + fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; + fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO; + mutex_unlock(&fsl_edma->fsl_edma_mutex); + return chan; + } else if ((fsl_edma->drvdata->dmamuxs || + (fsl_edma->drvdata->flags & FSL_EDMA_DRV_AXI)) && !fsl_chan->srcid) { + chan = dma_get_slave_channel(chan); + chan->device->privatecnt++; + fsl_chan->priority = dma_spec->args[1]; + fsl_chan->srcid = dma_spec->args[0]; + fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; + fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; + fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO; + mutex_unlock(&fsl_edma->fsl_edma_mutex); + return chan; + } + } + mutex_unlock(&fsl_edma->fsl_edma_mutex); + return NULL; +} + static int fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) { @@ -149,6 +217,37 @@ fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma return 0; } +static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) +{ + int ret; + int i; + + for (i = 0; i < fsl_edma->n_chans; i++) { + + struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; + + if (fsl_edma->chan_masked & BIT(i)) + continue; + + /* request channel irq */ + fsl_chan->txirq = platform_get_irq(pdev, i); + if (fsl_chan->txirq < 0) { + dev_err(&pdev->dev, "Can't get chan %d's irq.\n", i); + return -EINVAL; + } + + ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, + fsl_edma3_tx_handler, IRQF_SHARED, + fsl_chan->chan_name, fsl_chan); + if (ret) { + dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i); + return -EINVAL; + } + } + + return 0; +} + static int fsl_edma2_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) @@ -203,12 +302,16 @@ static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) static struct fsl_edma_drvdata vf610_data = { .version = v1, .dmamuxs = DMAMUX_NR, + .chreg_off = EDMA_TCD, + .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), .setup_irq = fsl_edma_irq_init, }; static struct fsl_edma_drvdata ls1028a_data = { .version = v1, .dmamuxs = DMAMUX_NR, + .chreg_off = EDMA_TCD, + .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), .flags = FSL_EDMA_DRV_MUX_SWAP, .setup_irq = fsl_edma_irq_init, }; @@ -216,18 +319,100 @@ static struct fsl_edma_drvdata ls1028a_data = { static struct fsl_edma_drvdata imx7ulp_data = { .version = v1, .dmamuxs = 1, + .chreg_off = EDMA_TCD, + .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, .setup_irq = fsl_edma2_irq_init, }; +static struct fsl_edma_drvdata imx8qm_data = { + .version = v3, + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_PD, + .chreg_space_sz = 0x10000, + .chreg_off = 0x10000, + .setup_irq = fsl_edma3_irq_init, +}; + +static struct fsl_edma_drvdata imx8qm_audio_data = { + .version = v3, + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_QUIRK_SWAPPED | + FSL_EDMA_DRV_HAS_PD, + .chreg_space_sz = 0x10000, + .chreg_off = 0x10000, + .setup_irq = fsl_edma3_irq_init, +}; + +static struct fsl_edma_drvdata imx93_data3 = { + .version = v3, + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK, + .chreg_space_sz = 0x10000, + .chreg_off = 0x10000, + .setup_irq = fsl_edma3_irq_init, +}; + +static struct fsl_edma_drvdata imx93_data4 = { + .version = v4, + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK, + .chreg_space_sz = 0x8000, + .chreg_off = 0x10000, + .setup_irq = fsl_edma3_irq_init, +}; + static const struct of_device_id fsl_edma_dt_ids[] = { { .compatible = "fsl,vf610-edma", .data = &vf610_data}, { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, + { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, + { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data}, + { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, + { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, { /* sentinel */ } }; + MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); +static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) +{ + struct fsl_edma_chan *fsl_chan; + struct device_link *link; + struct device *pd_chan; + struct device *dev; + int i; + + dev = &pdev->dev; + + for (i = 0; i < fsl_edma->n_chans; i++) { + if (fsl_edma->chan_masked & BIT(i)) + continue; + + fsl_chan = &fsl_edma->chans[i]; + + pd_chan = dev_pm_domain_attach_by_id(dev, i); + if (IS_ERR_OR_NULL(pd_chan)) { + dev_err(dev, "Failed attach pd %d\n", i); + return -EINVAL; + } + + link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (IS_ERR(link)) { + dev_err(dev, "Failed to add device_link to %d: %ld\n", i, + PTR_ERR(link)); + return -EINVAL; + } + + fsl_chan->pd_dev = pd_chan; + + pm_runtime_use_autosuspend(fsl_chan->pd_dev); + pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); + pm_runtime_set_active(fsl_chan->pd_dev); + //pm_runtime_put_sync_suspend(fsl_chan->pd_dev); + } + + return 0; +} + static int fsl_edma_probe(struct platform_device *pdev) { const struct of_device_id *of_id = @@ -266,8 +451,10 @@ static int fsl_edma_probe(struct platform_device *pdev) if (IS_ERR(fsl_edma->membase)) return PTR_ERR(fsl_edma->membase); - fsl_edma_setup_regs(fsl_edma); - regs = &fsl_edma->regs; + if (drvdata->version < v3) { + fsl_edma_setup_regs(fsl_edma); + regs = &fsl_edma->regs; + } if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); @@ -277,6 +464,17 @@ static int fsl_edma_probe(struct platform_device *pdev) } } + if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { + fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp"); + if (IS_ERR(fsl_edma->chclk)) { + dev_err(&pdev->dev, "Missing MP block clock.\n"); + return PTR_ERR(fsl_edma->chclk); + } + } + + if (of_property_read_u64(np, "fsl,channel-mask", &fsl_edma->chan_masked)) + fsl_edma->chan_masked = 0; + for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { char clkname[32]; @@ -299,9 +497,18 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); + if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { + ret = fsl_edma3_attach_pd(pdev, fsl_edma); + if (ret) + return ret; + } + INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); for (i = 0; i < fsl_edma->n_chans; i++) { - struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; + fsl_chan = &fsl_edma->chans[i]; + + if (fsl_edma->chan_masked & BIT(i)) + continue; snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", dev_name(&pdev->dev), i); @@ -312,12 +519,18 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_chan->idle = true; fsl_chan->dma_dir = DMA_NONE; fsl_chan->vchan.desc_free = fsl_edma_free_desc; - fsl_chan->tcd = fsl_edma->membase + EDMA_TCD - + i * sizeof(struct fsl_edma_hw_tcd); + + len = (fsl_edma_ver(fsl_chan) >= v3) ? offsetof(struct fsl_edma3_ch_reg, tcd) : 0; + fsl_chan->tcd = fsl_edma->membase + + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; + + fsl_chan->pdev = pdev; vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); edma_write_tcdreg(fsl_chan, 0, csr); - fsl_edma_chan_mux(fsl_chan, 0, false); + + if (drvdata->dmamuxs) + fsl_edma_chan_mux(fsl_chan, 0, false); } ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); @@ -347,12 +560,25 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; + + if (drvdata->version >= v3) { + fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); + fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); + } + fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + if (drvdata->version >= v3) + fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); + + fsl_edma->dma_dev.copy_align = drvdata->version >= v3 ? + DMAENGINE_ALIGN_64_BYTES : + DMAENGINE_ALIGN_32_BYTES; - fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES; /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff); + fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; + platform_set_drvdata(pdev, fsl_edma); ret = dma_async_device_register(&fsl_edma->dma_dev); @@ -362,7 +588,9 @@ static int fsl_edma_probe(struct platform_device *pdev) return ret; } - ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma); + ret = of_dma_controller_register(np, + drvdata->version < v3 ? fsl_edma_xlate : fsl_edma3_xlate, + fsl_edma); if (ret) { dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma. (%d)\n", ret); @@ -371,7 +599,8 @@ static int fsl_edma_probe(struct platform_device *pdev) } /* enable round robin arbitration */ - edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); + if (drvdata->version < v3) + edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); return 0; } From patchwork Mon May 29 20:04:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 100413 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1748539vqr; Mon, 29 May 2023 13:22:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5btNNquUxBw4WYzHfOULDLgd5nRHicDK3azzF3Jb1M8qXmgH2msVqx5sXLWZiFBROC0ytk X-Received: by 2002:a17:902:ba84:b0:1a9:b8c3:c2c2 with SMTP id k4-20020a170902ba8400b001a9b8c3c2c2mr222103pls.37.1685391730918; Mon, 29 May 2023 13:22:10 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1685391730; cv=pass; d=google.com; s=arc-20160816; b=t5fTaQwqbxd4pq4zTvRRdfJf/KnjclKXn2dJddfKzaFCEJyqAhQ1j07AvuEJ8wQ3R+ zpye+ok8IHgRoFeCQ81Ko/l8E0xIcnPkAM9HfzZDmRW6Uvvun35Hmlx1ydj8Usl9Cmyp oI6w4eWDI26Eb8EwCa+tr4IT+IUJGKVTUWCSks41PRBw5ESreJIBUYbMQf+uEbae7V1F kn/n6pfm46yw0bMPLb37mWY1wBLjzhMshxikYytBmwbCAN+jQ4Rhx3Mb2cMj5og1U90C 7yR2JFRn+mAM9APn8WDe7PaAhjn8NOmlWXuUP5EFaMJ8rfu1qgaCrixslcnRUWcgWeZp j5qQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dgetTr4ykw1iDiXNNcefnB4/26WvmVRYD6yME8KkHrA=; b=RB5KJQf8ho4wmzxFAB86Gk05iBCq6MhX3mSxI/6s2OP+YO7b9/AODGfKZeropyqjGK ISqlhZyxWel84WXDZ4lM5Pd0qaYQMYwZQy9/UFvwCvpMTdFFGYeGQKe5d8+mDc2+HOff DDvJGxkMvtraC37BB0yxQnP54I8S4+AepzF9or8h3AVxCGYw6bIzxICmNQUiFgPvx7xU 5XKyav8gL8ivdBcMIISVyIMyOsi0aFlyQAJ2oNhTXLglJ41ISsv4wB5YvGZ6KCwtHAQB MSXNL1SkhEXun5hggf6s8gnCBid4SXVkgDKLYMpvXztbrSXferJB1oWNyRKC9akwEKWL twAg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=i7SabrIN; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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In i.MX93, both eDMA3 and eDMA4 are now. Signed-off-by: Frank Li --- .../devicetree/bindings/dma/fsl,edma.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index 5fd8fc604261..eed12687b0c9 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -21,6 +21,10 @@ properties: - enum: - fsl,vf610-edma - fsl,imx7ulp-edma + - fsl,imx8qm-edma + - fsl,imx8qm-adma + - fsl,imx93-edma3 + - fsl,imx93-edma4 - items: - const: fsl,ls1028a-edma - const: fsl,vf610-edma @@ -101,6 +105,22 @@ allOf: reg: maxItems: 2 + - if: + properties: + compatible: + contains: + anyOf: + - const: fsl,imx8qm-edma + - const: fsl,imx8qm-adma + - const: fsl,imx93-edma3 + - const: fsl,imx93-edma4 + then: + properties: + reg: + maxItems: 1 + interrupts: + maxItems: 64 + unevaluatedProperties: false examples: