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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id b30-20020ac25e9e000000b004eff4f67f1csm1966375lfq.304.2023.05.29.06.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 06:14:26 -0700 (PDT) From: Konrad Dybcio Date: Mon, 29 May 2023 15:14:23 +0200 Subject: [PATCH 1/2] dt-bindings: clock: sm6375-gpucc: Add VDD_GX MIME-Version: 1.0 Message-Id: <20230529-topic-sm6375gpuccpd-v1-1-8d57c41a6066@linaro.org> References: <20230529-topic-sm6375gpuccpd-v1-0-8d57c41a6066@linaro.org> In-Reply-To: <20230529-topic-sm6375gpuccpd-v1-0-8d57c41a6066@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685366063; l=1827; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WQWF4JJc7yA9tWZ94p0YCyHtEC0Bk5E4nV1ZHYYfpQM=; b=zZUIuwkkxc6pabcOv6AenjuRpHNEF0ij5m1IkX94treKnyiYUsxZLrVX/P0U+/F7ckkRkoEHP 42FKRKl7G0GDNfUEGh1PV/yZuQFxMZIgi+cRoo0IfTiRHfuJrzjHCLv X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767235062703217056?= X-GMAIL-MSGID: =?utf-8?q?1767235062703217056?= The GPUCC block on SM6375 is powered by VDD_CX and VDD_GX. If the latter rail is not online, GX_GDSC will never turn on. Describe the missing handles. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,sm6375-gpucc.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml index b480ead5bd69..cf4cad76f6c9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml @@ -27,9 +27,21 @@ properties: - description: GPLL0 div branch source - description: SNoC DVM GFX source + power-domains: + description: + A phandle and PM domain specifier for the VDD_GX power rail + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required VDD_GX performance point. + maxItems: 1 + required: - compatible - clocks + - power-domains + - required-opps allOf: - $ref: qcom,gcc.yaml# @@ -40,6 +52,7 @@ examples: - | #include #include + #include soc { #address-cells = <2>; @@ -52,6 +65,8 @@ examples: <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + power-domains = <&rpmpd SM6375_VDDGX>; + required-opps = <&rpmpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Mon May 29 13:14:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 100258 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1508879vqr; Mon, 29 May 2023 06:20:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6R02ocrlCXOR+AkMs9YwbuvLnticG6uH+j5x4xa3xzuZD6Tbje2EaIzBo8FfAmzHEzog/P X-Received: by 2002:a17:902:a710:b0:19f:3d59:e0ac with SMTP id w16-20020a170902a71000b0019f3d59e0acmr9657839plq.44.1685366439371; Mon, 29 May 2023 06:20:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685366439; cv=none; d=google.com; s=arc-20160816; b=s6zyg27Q5x6VVi0nCzVXR4H5Wcpimp/HuMtXW/06XFXBiX4QQ0rny9e+muCrpYtrU4 QheBmyCFQ+CCQTyU860ZECjit1p7Uz/40nRMEb9GSSHe78Ke+Sj7Tt61+KspvvPIS3Nu pb71AyW2amvFgkuNe3SP3cPIozBYgoSxqgtdX2JsQq71U2VJ+6k1ZuWH9leEOJN7odeT X+0B7hItl1CDY0StKVx6txl9VXFd9t/0C4SvwJSbKqwAyVmJ4ygqO1D2lG1kcjecbPWH RmPLqlTtFWXK35znDpn3XOwGiQo1MFMrGTYjICXsPRvsOtL2DnTt58DS0mx8EBZGadEh csqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=x278P3+nKSRirib6kE+simYSKscVONKkDYY89zSUJwA=; b=STSeq2PuHCsPKjytGnbiO+LUpzZKzY2AJ5iLpTf+4GFCv5E8Xki8ivmLjpC/pAZv7e 5VwDRUBJjHoA7l0/iUC4HhOF/k6iuRbGfhOorewBvxdWOGVoCJdNN44QpSQUx50SdWAU j809nrm8kUNBwZPcfyMkC6Jo3jP+2d32ODXN7fJt1CfaTZAEdT2I3M/iNOzjK2UQVIah +quFiYzWDRKCoR9nM8eTQJL1TzDA5sMMKhObEaG72/HwL65hAqnWFN/aulzx95/p3q5d Q1DSmgFBWSF1Hhx8mQ3+3npm7krIiYZy1kPXGETXnPh7OpT7d8aNb0SFsZEldCPYyj8k u8PA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vyonl+av; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id b30-20020ac25e9e000000b004eff4f67f1csm1966375lfq.304.2023.05.29.06.14.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 06:14:27 -0700 (PDT) From: Konrad Dybcio Date: Mon, 29 May 2023 15:14:24 +0200 Subject: [PATCH 2/2] clk: qcom: gpucc-sm6375: Enable runtime pm MIME-Version: 1.0 Message-Id: <20230529-topic-sm6375gpuccpd-v1-2-8d57c41a6066@linaro.org> References: <20230529-topic-sm6375gpuccpd-v1-0-8d57c41a6066@linaro.org> In-Reply-To: <20230529-topic-sm6375gpuccpd-v1-0-8d57c41a6066@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685366063; l=1703; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=FCWtznh8qKMCk7aGI9UAflx31G2nB1pwP25Cm0GDLGM=; b=TIzzdGVj/33FhZbVZwxfJzULE98ho9j5EP0ObW6OgbnLYs/W032xyG2b6VnlD4zyfMypgxTdh 3f28AKawd+1DPldnYJmP4wKIVgSVzDq86t7OOShQ8BndH8/OWYEIDV9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767234799161230488?= X-GMAIL-MSGID: =?utf-8?q?1767234799161230488?= The GPUCC block on SM6375 is powered by VDD_CX and VDD_GX. If the latter rail is not online, GX_GDSC will never turn on. Enable runtime pm so that we can reference VDD_GX from the dt to ensure that. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6375.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c index d3620344a009..2d863dc3d83b 100644 --- a/drivers/clk/qcom/gpucc-sm6375.c +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -434,15 +435,29 @@ MODULE_DEVICE_TABLE(of, gpucc_sm6375_match_table); static int gpucc_sm6375_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); - return qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gpucc_sm6375_driver = {