From patchwork Mon May 29 12:15:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changhuang Liang X-Patchwork-Id: 100234 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1472934vqr; Mon, 29 May 2023 05:27:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7eLiIaJJocxOjzMP4WnPKFUYocIKPfXXjnM5Qc8ERjIuRNg+Xshtn/NYED+loq+3/2seoU X-Received: by 2002:a05:6a00:1896:b0:643:59cd:6cad with SMTP id x22-20020a056a00189600b0064359cd6cadmr15950608pfh.24.1685363271220; Mon, 29 May 2023 05:27:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685363271; cv=none; d=google.com; s=arc-20160816; b=avRTi9Vy4ifiIQx1xTnmmHHeFLgvycSRYy1MFqqkwYbTBvlAPKlXV4ugw7Rm0xbeem jHPqwonkc3MFx5lR+xevDZOpTm2euAtIQDUm4CC1tKUM2G5nrmBj/0SUkff2u0H7OKpB 3IMR5YbH0+WDaTlmTcHlbZX9hxR/J2Jh5j0N61fJbM0GTwkTPG9z3saiyfyRo/uVqBzk 0yfF9UiXG2BOFkVH9A0FZRVrSe49LAcaqUpinTIX1kLuggXIv0kWRyzIABKY3NhvJQT1 cHqNyz8/zkczroBiZWJQBs2aNjB+v0Ne3u85aiPk6GNHGUI1gwhYgzT+fzxIzhcrbHOX G3Kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=M4CguZp/MaL5bKn3PsVO6aPg2pMDkXqxYboTjjJ9Up4=; b=CTfrZiHBMZzP4SsIT1ePYDE2/qrxk2V6oKwQ3jfIIaxi+WTGo9xChv2D6Ow0iAn94Z LkXe/t1BMLu2iicUWVtrS5YRdLgeLjW+Z4aZropEo/nha7JSu0P3TmkCNaxKL7Cp2mbZ 9BfGlpUx54Dt8L8DXYsDUF6rF2UdRKvK/pHWl0Cd6k/ZLn+PRS+jcPRRCUjedWjrlEOG /txB26n/EG6lZbq3DB8Kncz1kjwBn1fPuAsbyKwp2UcO/3vD07bKFpEPIca0+CJN1+gB bQOaeC+Gw784xJjpPIK5GkUfFaMN3W+o/UUwWfLo85chRrGHyICwutvBqI2Uz8XGoDGM 1nrg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 126-20020a620684000000b0064d3beb0d66si9254978pfg.78.2023.05.29.05.27.36; Mon, 29 May 2023 05:27:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231693AbjE2MPS convert rfc822-to-8bit (ORCPT + 99 others); Mon, 29 May 2023 08:15:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230512AbjE2MPQ (ORCPT ); Mon, 29 May 2023 08:15:16 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C96EC7; Mon, 29 May 2023 05:15:15 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 407077FFC; Mon, 29 May 2023 20:15:07 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 29 May 2023 20:15:07 +0800 Received: from ubuntu.localdomain (113.72.147.198) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 29 May 2023 20:15:06 +0800 From: Changhuang Liang To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel CC: Jack Zhu , Changhuang Liang , , , , Subject: [PATCH v5 1/3] dt-bindings: phy: Add starfive,jh7110-dphy-rx Date: Mon, 29 May 2023 05:15:01 -0700 Message-ID: <20230529121503.3544-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230529121503.3544-1-changhuang.liang@starfivetech.com> References: <20230529121503.3544-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.147.198] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767231477763411721?= X-GMAIL-MSGID: =?utf-8?q?1767231477763411721?= StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on a M31 IP. Add a binding for it. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring --- .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml new file mode 100644 index 000000000000..46fd370188e8 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive SoC MIPI D-PHY Rx Controller + +maintainers: + - Jack Zhu + - Changhuang Liang + +description: + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer + CSI camera data. + +properties: + compatible: + const: starfive,jh7110-dphy-rx + + reg: + maxItems: 1 + + clocks: + items: + - description: config clock + - description: reference clock + - description: escape mode transmit clock + + clock-names: + items: + - const: cfg + - const: ref + - const: tx + + resets: + items: + - description: DPHY_HW reset + - description: DPHY_B09_ALWAYS_ON reset + + power-domains: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - power-domains + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@19820000 { + compatible = "starfive,jh7110-dphy-rx"; + reg = <0x19820000 0x10000>; + clocks = <&ispcrg 3>, + <&ispcrg 4>, + <&ispcrg 5>; + clock-names = "cfg", "ref", "tx"; + resets = <&ispcrg 2>, + <&ispcrg 3>; + power-domains = <&dphy_pwrc 1>; + #phy-cells = <0>; + }; From patchwork Mon May 29 12:15:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changhuang Liang X-Patchwork-Id: 100235 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1479002vqr; Mon, 29 May 2023 05:37:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4asrr+rflmuvmx9okEUJ+tMF4R+UZ1ROHYK2dUEhg0Frk7Qi7ipriwYhV4DE8XAFl6fn9B X-Received: by 2002:a17:90a:a50b:b0:253:6637:5656 with SMTP id a11-20020a17090aa50b00b0025366375656mr10537336pjq.16.1685363878372; Mon, 29 May 2023 05:37:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685363878; cv=none; d=google.com; s=arc-20160816; b=cJVMs+w69/HxDCFCbo8YzpVWibD9prhVye8fC6pgNtPYuKAcMHCMQ5p5kySfaesgxf 7yQgpxrTvgRckVGPFPzl1/lyg9cZb3llCBGSehlyRP6k/qTwyiUWz9diVpfbp8IW2EtN YAzRu7hFnogpKYXYrxCSy5Baz1atAP+EY/2Vsg1dlzAioed9eAj0C8LRU+Qan9BLXbkj w9KgWf1xgEZqmmWsDBffEIDTn1gOAT9O3B880RsYe4rVhe6fvu1tSWHCBw6fz81cTG+u /Vx13iAvXzdiDg6WYE/Ds6DOguueXA3XTNvxv9NKwcsMnJWOlj4q5+pBRaL4hnw+c13f APDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=vumxjbb8QVFKO/AX+gl5sxGD23q9AO4f93303QM/i90=; b=oXi6cq94WtRHPSkd9X5cgg9/zy3mUAIETre0M9KOm8I0hEW9IZnxyaNVLbHtVzNbX9 O5elfWMtrns1D/p5ZxwJcfwNY7E9p7AG4QGITRklKE0MtfEMSTbwpvcoorHsj2mfuTOE otq5IqvhUnDrTPhEzSbo8BwgbAa4dVY8M3yEPD/YC5OofpKgE9l290G+LUzUTLsM9amw fe/KsSFb7CyVIqq0wSDav/UTW4zD54Gk9NssnCg/pVxHuqXTdngC/4qu34hUKeRfIoIz Y0ruEDnv4CZFk77klTxUX+u/Qrvneblku9v6CY4CX5w1dH/gwZIJm5/pvgw/HwqdSJ/V rpbw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gv6-20020a17090b11c600b0025327b5caefsi4715403pjb.165.2023.05.29.05.37.42; Mon, 29 May 2023 05:37:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231698AbjE2MPe convert rfc822-to-8bit (ORCPT + 99 others); Mon, 29 May 2023 08:15:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231479AbjE2MPa (ORCPT ); Mon, 29 May 2023 08:15:30 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DAAAEC; Mon, 29 May 2023 05:15:24 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 8C8CF7FFE; Mon, 29 May 2023 20:15:08 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 29 May 2023 20:15:07 +0800 Received: from ubuntu.localdomain (113.72.147.198) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 29 May 2023 20:15:07 +0800 From: Changhuang Liang To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel CC: Jack Zhu , Changhuang Liang , , , , Subject: [PATCH v5 2/3] phy: starfive: Add mipi dphy rx support Date: Mon, 29 May 2023 05:15:02 -0700 Message-ID: <20230529121503.3544-3-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230529121503.3544-1-changhuang.liang@starfivetech.com> References: <20230529121503.3544-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.147.198] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767232114035830895?= X-GMAIL-MSGID: =?utf-8?q?1767232114035830895?= Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to transfer CSI camera data. Signed-off-by: Changhuang Liang --- MAINTAINERS | 7 + drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/starfive/Kconfig | 13 + drivers/phy/starfive/Makefile | 2 + drivers/phy/starfive/phy-starfive-dphy-rx.c | 300 ++++++++++++++++++++ 6 files changed, 324 insertions(+) create mode 100644 drivers/phy/starfive/Kconfig create mode 100644 drivers/phy/starfive/Makefile create mode 100644 drivers/phy/starfive/phy-starfive-dphy-rx.c diff --git a/MAINTAINERS b/MAINTAINERS index 92c7076c4fed..a5fac3f015b4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20092,6 +20092,13 @@ S: Maintained F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c +STARFIVE JH7110 DPHY RX DRIVER +M: Jack Zhu +M: Changhuang Liang +S: Supported +F: Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml +F: drivers/phy/starfive/phy-starfive-dphy-rx.c + STARFIVE JH7110 MMC/SD/SDIO DRIVER M: William Qiu S: Supported diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index f46e3148d286..0000149edbc4 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -91,6 +91,7 @@ source "drivers/phy/rockchip/Kconfig" source "drivers/phy/samsung/Kconfig" source "drivers/phy/socionext/Kconfig" source "drivers/phy/st/Kconfig" +source "drivers/phy/starfive/Kconfig" source "drivers/phy/sunplus/Kconfig" source "drivers/phy/tegra/Kconfig" source "drivers/phy/ti/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 54f312c10a40..fb3dc9de6111 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -31,6 +31,7 @@ obj-y += allwinner/ \ samsung/ \ socionext/ \ st/ \ + starfive/ \ sunplus/ \ tegra/ \ ti/ \ diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig new file mode 100644 index 000000000000..f989b8ff8bcb --- /dev/null +++ b/drivers/phy/starfive/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for StarFive platforms +# + +config PHY_STARFIVE_DPHY_RX + tristate "StarFive D-PHY RX Support" + select GENERIC_PHY + select GENERIC_PHY_MIPI_DPHY + help + Choose this option if you have a StarFive D-PHY in your + system. If M is selected, the module will be called + phy-starfive-dphy-rx. diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile new file mode 100644 index 000000000000..7ec576cb30ae --- /dev/null +++ b/drivers/phy/starfive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) += phy-starfive-dphy-rx.o diff --git a/drivers/phy/starfive/phy-starfive-dphy-rx.c b/drivers/phy/starfive/phy-starfive-dphy-rx.c new file mode 100644 index 000000000000..6974ed904d0d --- /dev/null +++ b/drivers/phy/starfive/phy-starfive-dphy-rx.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DPHY driver for the StarFive JH7110 SoC + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STF_DPHY_APBCFGSAIF_SYSCFG(x) (x) + +#define STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN BIT(6) +#define STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN GENMASK(12, 7) +#define STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN BIT(19) +#define STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN GENMASK(25, 20) + +#define STF_DPHY_DATA_BUS16_8 BIT(8) +#define STF_DPHY_DEBUG_MODE_SEL GENMASK(15, 9) + +#define STF_DPHY_ENABLE_CLK BIT(6) +#define STF_DPHY_ENABLE_CLK1 BIT(7) +#define STF_DPHY_ENABLE_LAN0 BIT(8) +#define STF_DPHY_ENABLE_LAN1 BIT(9) +#define STF_DPHY_ENABLE_LAN2 BIT(10) +#define STF_DPHY_ENABLE_LAN3 BIT(11) +#define STF_DPHY_GPI_EN GENMASK(17, 12) +#define STF_DPHY_HS_FREQ_CHANGE_CLK BIT(18) +#define STF_DPHY_HS_FREQ_CHANGE_CLK1 BIT(19) +#define STF_DPHY_LANE_SWAP_CLK GENMASK(22, 20) +#define STF_DPHY_LANE_SWAP_CLK1 GENMASK(25, 23) +#define STF_DPHY_LANE_SWAP_LAN0 GENMASK(28, 26) +#define STF_DPHY_LANE_SWAP_LAN1 GENMASK(31, 29) + +#define STF_DPHY_LANE_SWAP_LAN2 GENMASK(2, 0) +#define STF_DPHY_LANE_SWAP_LAN3 GENMASK(5, 3) +#define STF_DPHY_MP_TEST_EN BIT(6) +#define STF_DPHY_MP_TEST_MODE_SEL GENMASK(11, 7) +#define STF_DPHY_PLL_CLK_SEL GENMASK(21, 12) +#define STF_DPHY_PRECOUNTER_IN_CLK GENMASK(29, 22) + +#define STF_DPHY_PRECOUNTER_IN_CLK1 GENMASK(7, 0) +#define STF_DPHY_PRECOUNTER_IN_LAN0 GENMASK(15, 8) +#define STF_DPHY_PRECOUNTER_IN_LAN1 GENMASK(23, 16) +#define STF_DPHY_PRECOUNTER_IN_LAN2 GENMASK(31, 24) + +#define STF_DPHY_PRECOUNTER_IN_LAN3 GENMASK(7, 0) +#define STF_DPHY_RX_1C2C_SEL BIT(8) + +#define STF_MAP_LANES_NUM 6 + +struct regval { + u32 addr; + u32 val; +}; + +struct stf_dphy_info { + /** + * @maps: + * + * Physical lanes and logic lanes mapping table. + * + * The default order is: + * [clk lane0, data lane 0, data lane 1, data lane 2, date lane 3, clk lane 1] + */ + u8 maps[STF_MAP_LANES_NUM]; +}; + +struct stf_dphy { + struct device *dev; + void __iomem *regs; + struct clk *cfg_clk; + struct clk *ref_clk; + struct clk *tx_clk; + struct reset_control *rstc; + struct regulator *mipi_0p9; + struct phy *phy; + const struct stf_dphy_info *info; +}; + +static const struct regval stf_dphy_init_list[] = { + { STF_DPHY_APBCFGSAIF_SYSCFG(4), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(8), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(12), 0x0000fff0 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(16), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(20), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(24), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(28), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(32), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(36), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(40), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(40), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(48), 0x24000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(52), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(56), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(60), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(64), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(68), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(72), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(76), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(80), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(84), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(88), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(92), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(96), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(100), 0x02000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(104), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(108), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(112), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(116), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(120), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(124), 0x0000000c }, + { STF_DPHY_APBCFGSAIF_SYSCFG(128), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(132), 0xcc500000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(136), 0x000000cc }, + { STF_DPHY_APBCFGSAIF_SYSCFG(140), 0x00000000 }, + { STF_DPHY_APBCFGSAIF_SYSCFG(144), 0x00000000 }, +}; + +static int stf_dphy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + struct stf_dphy *dphy = phy_get_drvdata(phy); + const struct stf_dphy_info *info = dphy->info; + int i; + + for (i = 0; i < ARRAY_SIZE(stf_dphy_init_list); i++) + writel(stf_dphy_init_list[i].val, + dphy->regs + stf_dphy_init_list[i].addr); + + writel(FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN, 1) | + FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN, 0x1b) | + FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN, 1) | + FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN, 0x1b), + dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(0)); + + writel(FIELD_PREP(STF_DPHY_DATA_BUS16_8, 0) | + FIELD_PREP(STF_DPHY_DEBUG_MODE_SEL, 0x5a), + dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(184)); + + writel(FIELD_PREP(STF_DPHY_ENABLE_CLK, 1) | + FIELD_PREP(STF_DPHY_ENABLE_CLK1, 1) | + FIELD_PREP(STF_DPHY_ENABLE_LAN0, 1) | + FIELD_PREP(STF_DPHY_ENABLE_LAN1, 1) | + FIELD_PREP(STF_DPHY_ENABLE_LAN2, 1) | + FIELD_PREP(STF_DPHY_ENABLE_LAN3, 1) | + FIELD_PREP(STF_DPHY_GPI_EN, 0) | + FIELD_PREP(STF_DPHY_HS_FREQ_CHANGE_CLK, 0) | + FIELD_PREP(STF_DPHY_HS_FREQ_CHANGE_CLK1, 0) | + FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) | + FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) | + FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) | + FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]), + dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188)); + + writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) | + FIELD_PREP(STF_DPHY_LANE_SWAP_LAN3, info->maps[4]) | + FIELD_PREP(STF_DPHY_MP_TEST_EN, 0) | + FIELD_PREP(STF_DPHY_MP_TEST_MODE_SEL, 0) | + FIELD_PREP(STF_DPHY_PLL_CLK_SEL, 0x37c) | + FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK, 8), + dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(192)); + + writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK1, 8) | + FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN0, 7) | + FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN1, 7) | + FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN2, 7), + dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(196)); + + writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN3, 7) | + FIELD_PREP(STF_DPHY_RX_1C2C_SEL, 0), + dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(200)); + + return 0; +} + +static int stf_dphy_power_on(struct phy *phy) +{ + struct stf_dphy *dphy = phy_get_drvdata(phy); + int ret; + + pm_runtime_get_sync(dphy->dev); + + ret = regulator_enable(dphy->mipi_0p9); + if (ret) + return ret; + + clk_set_rate(dphy->cfg_clk, 99000000); + clk_set_rate(dphy->ref_clk, 49500000); + clk_set_rate(dphy->tx_clk, 19800000); + reset_control_deassert(dphy->rstc); + + return 0; +} + +static int stf_dphy_power_off(struct phy *phy) +{ + struct stf_dphy *dphy = phy_get_drvdata(phy); + + reset_control_assert(dphy->rstc); + + regulator_disable(dphy->mipi_0p9); + + pm_runtime_put_sync(dphy->dev); + + return 0; +} + +static const struct phy_ops stf_dphy_ops = { + .configure = stf_dphy_configure, + .power_on = stf_dphy_power_on, + .power_off = stf_dphy_power_off, +}; + +static int stf_dphy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct stf_dphy *dphy; + + dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); + if (!dphy) + return -ENOMEM; + + dphy->info = of_device_get_match_data(&pdev->dev); + + dev_set_drvdata(&pdev->dev, dphy); + dphy->dev = &pdev->dev; + + dphy->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dphy->regs)) + return PTR_ERR(dphy->regs); + + dphy->cfg_clk = devm_clk_get(&pdev->dev, "cfg"); + if (IS_ERR(dphy->cfg_clk)) + return PTR_ERR(dphy->cfg_clk); + + dphy->ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (IS_ERR(dphy->ref_clk)) + return PTR_ERR(dphy->ref_clk); + + dphy->tx_clk = devm_clk_get(&pdev->dev, "tx"); + if (IS_ERR(dphy->tx_clk)) + return PTR_ERR(dphy->tx_clk); + + dphy->rstc = devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(dphy->rstc)) + return PTR_ERR(dphy->rstc); + + dphy->mipi_0p9 = devm_regulator_get(&pdev->dev, "mipi_0p9"); + if (IS_ERR(dphy->mipi_0p9)) + return PTR_ERR(dphy->mipi_0p9); + + dphy->phy = devm_phy_create(&pdev->dev, NULL, &stf_dphy_ops); + if (IS_ERR(dphy->phy)) { + dev_err(&pdev->dev, "Failed to create PHY\n"); + return PTR_ERR(dphy->phy); + } + + pm_runtime_enable(&pdev->dev); + + phy_set_drvdata(dphy->phy, dphy); + phy_provider = devm_of_phy_provider_register(&pdev->dev, + of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct stf_dphy_info starfive_dphy_info = { + .maps = {4, 0, 1, 2, 3, 5}, +}; + +static const struct of_device_id stf_dphy_dt_ids[] = { + { + .compatible = "starfive,jh7110-dphy-rx", + .data = &starfive_dphy_info, + }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, stf_dphy_dt_ids); + +static struct platform_driver stf_dphy_driver = { + .probe = stf_dphy_probe, + .driver = { + .name = "starfive-dphy-rx", + .of_match_table = stf_dphy_dt_ids, + }, +}; +module_platform_driver(stf_dphy_driver); + +MODULE_AUTHOR("Jack Zhu "); +MODULE_AUTHOR("Changhuang Liang "); +MODULE_DESCRIPTION("StarFive DPHY RX driver"); +MODULE_LICENSE("GPL"); From patchwork Mon May 29 12:15:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changhuang Liang X-Patchwork-Id: 100233 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1471086vqr; Mon, 29 May 2023 05:24:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4JwEEPzF0FgCIcJKnaHlnNQ2ok9cm3afraVrS5erYdny7/Gl5anPjW5nYQvNLEtG7k8z7U X-Received: by 2002:a05:6a20:4293:b0:10c:c407:92e5 with SMTP id o19-20020a056a20429300b0010cc40792e5mr8809915pzj.22.1685363063068; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j24-20020a63cf18000000b0051909d663d8si9105848pgg.656.2023.05.29.05.24.05; Mon, 29 May 2023 05:24:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230518AbjE2MPX convert rfc822-to-8bit (ORCPT + 99 others); Mon, 29 May 2023 08:15:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229606AbjE2MPQ (ORCPT ); Mon, 29 May 2023 08:15:16 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 941F1B2; Mon, 29 May 2023 05:15:11 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id B40EE24E207; Mon, 29 May 2023 20:15:08 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 29 May 2023 20:15:08 +0800 Received: from ubuntu.localdomain (113.72.147.198) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 29 May 2023 20:15:07 +0800 From: Changhuang Liang To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel CC: Jack Zhu , Changhuang Liang , , , , Subject: [PATCH v5 3/3] riscv: dts: starfive: Add dphy rx node Date: Mon, 29 May 2023 05:15:03 -0700 Message-ID: <20230529121503.3544-4-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230529121503.3544-1-changhuang.liang@starfivetech.com> References: <20230529121503.3544-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.147.198] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767231259054597058?= X-GMAIL-MSGID: =?utf-8?q?1767231259054597058?= Add dphy rx node for the StarFive JH7110 SoC. It is used to transfer CSI camera data. Signed-off-by: Changhuang Liang --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 2207be7e1b01..e4241e32dd09 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -579,6 +579,19 @@ ispcrg: clock-controller@19810000 { power-domains = <&pwrc JH7110_PD_ISP>; }; + csi_phy: phy@19820000 { + compatible = "starfive,jh7110-dphy-rx"; + reg = <0x0 0x19820000 0x0 0x10000>; + clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>; + clock-names = "cfg", "ref", "tx"; + resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>, + <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>; + power-domains = <&aon_syscon JH7110_PD_DPHY_RX>; + #phy-cells = <0>; + }; + voutcrg: clock-controller@295c0000 { compatible = "starfive,jh7110-voutcrg"; reg = <0x0 0x295c0000 0x0 0x10000>;