From patchwork Wed Oct 26 00:56:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 11028 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1303729wru; Tue, 25 Oct 2022 18:00:28 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7/54UnwiVElY+jfmS0Q4wYWwZkaME/lc9QgUPppM4rJZltjFvLuSoViZE+HYGgYrGcb6tS X-Received: by 2002:a17:907:7da6:b0:791:997e:58fc with SMTP id oz38-20020a1709077da600b00791997e58fcmr36139132ejc.385.1666746027888; Tue, 25 Oct 2022 18:00:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666746027; cv=none; d=google.com; s=arc-20160816; b=FfqpALrHODjOSR9XQC4tTptBzWchZveUP4fnzdTgK/TH6MFfOhWXXmC64mYvqmSAYz EFsc9anZXMnZfHdnsf8Q7wL0raYLJF0LwLHp/tmKxYtNgwLiCqh+6awPB1ATSWseCGAk z2CLjGZGDwOx0LxuZ7F3Rgn3H6SURapcn7spZ47BFp2PP8ssKVMhdP6txBz6dhj8XBSb 7F2wbKUx7sKDytAIAmfhgjP67VhPfXAfIVu1wmL9ldvKP1PAwZzE9YbGaPpK+nprBcYF G/ydW4krdd5DFvxFZcmIFlLua4YztAubO/llYWno2hUQXF9BsTKP69U4JSBzehB5SN/M vAZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-disposition:mime-version:message-id :subject:cc:to:from:date; bh=VuIv1ZL3ztdYYZouQ7Ax8epJfmzjjKGL4kkqK3LH2ak=; b=oFUVXQ83C4y1UsjEYR1+8xeg8JUcgxsNyU5kEFI1ZngSrFPR+2s10pYf1f9GFY1HhO UmbU5VvNM67qjHGs/4aavAtog8O3E9ekmGJtj/dCwnmoDiu/B3/q/uzWk+9nF06t/fqS l7johm3MmzblwueFdVqunuqnQcpYRUeldvzC/LCdEgXcefAEf1byDnXli3SFhirpGksi NwejhUxLfBTD5tuOnJZOq2zHoPNNMnFC432BqNZMKW+h309jaex/FQxAjxamjMfKM/sr sAXwdwGKQW5G6QIoUxQ9SrnQRDTYkKHWE1PTWO38JPeXzKqaB84kvmR2icVM0kJosTtr +t8A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l21-20020a056402345500b0045ca3839229si3783306edc.274.2022.10.25.18.00.03; Tue, 25 Oct 2022 18:00:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231640AbiJZA5O (ORCPT + 99 others); Tue, 25 Oct 2022 20:57:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230057AbiJZA5N (ORCPT ); Tue, 25 Oct 2022 20:57:13 -0400 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50741B56F5; Tue, 25 Oct 2022 17:57:11 -0700 (PDT) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.94.2) (envelope-from ) id 1onUjB-0002Yp-PL; Wed, 26 Oct 2022 02:57:06 +0200 Date: Wed, 26 Oct 2022 01:56:58 +0100 From: Daniel Golle To: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Thierry Reding , Uwe =?iso-8859-1?q?Kleine-K=F6ni?= =?iso-8859-1?q?g?= , Matthias Brugger Cc: Fabien Parent , Zhi Mao , Sam Shih Subject: [PATCH] pwm: mediatek: always use bus clock for PWM on MT7622 Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747709883044367378?= X-GMAIL-MSGID: =?utf-8?q?1747709883044367378?= According to MT7622 Reference Manual for Development Board v1.0 the PWM unit found in the MT7622 SoC also comes with the PWM_CK_26M_SEL register at offset 0x210 just like other modern MediaTek ARM64 SoCs. And also MT7622 sets that register to 0x00000001 on reset which is described as 'Select 26M fix CLK as BCLK' in the datasheet. Hence set has_ck_26m_sel to true also for MT7622 which results in the driver writing 0 to the PWM_CK_26M_SEL register which is described as 'Select bus CLK as BCLK'. Fixes: 0c0ead76235db0 ("pwm: mediatek: Always use bus clock") Signed-off-by: Daniel Golle Reviewed-by: AngeloGioacchino Del Regno Acked-by: Uwe Kleine-König --- drivers/pwm/pwm-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 2219cba033e348..5b5eeaff35da67 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -296,7 +296,7 @@ static const struct pwm_mediatek_of_data mt6795_pwm_data = { static const struct pwm_mediatek_of_data mt7622_pwm_data = { .num_pwms = 6, .pwm45_fixup = false, - .has_ck_26m_sel = false, + .has_ck_26m_sel = true, }; static const struct pwm_mediatek_of_data mt7623_pwm_data = {