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Signed-off-by: Devi Priya Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index fe7ed853e598..888cb8bfd0cd 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -88,6 +88,7 @@ description: | ap-al02-c2 ap-al02-c6 ap-al02-c7 + ap-al02-c8 ap-al02-c9 ap-mi01.2 ap-mi01.6 @@ -357,6 +358,7 @@ properties: - qcom,ipq9574-ap-al02-c2 - qcom,ipq9574-ap-al02-c6 - qcom,ipq9574-ap-al02-c7 + - qcom,ipq9574-ap-al02-c8 - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 From patchwork Fri May 26 15:31:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 99559 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp572292vqr; Fri, 26 May 2023 08:45:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5aEzMiyec7KdvhkRCMRz5tgHmVW3n82VoKu/il6A1BkRtvGsYHqAG57gOEkSzAgvcGJhK2 X-Received: by 2002:a17:902:7c05:b0:1af:bb99:d590 with SMTP id x5-20020a1709027c0500b001afbb99d590mr2759660pll.7.1685115951398; Fri, 26 May 2023 08:45:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685115951; cv=none; d=google.com; s=arc-20160816; b=cEwyIuAr+giYihpDJa3KrWzCxk+3Q0EIUGDEGSeN+AtTWfBavgMclWeiQaR1zDPgvf ZasA/kPcjxxjkL+m/FLUMN/0HEUov5QH6IyKueTGXwHweG33XLTKg2INad24O0G5BcJD HGpXiNh5XPxs4/4i934NyxmpP5ZRBEr8MVzVBIMH2pWFaqNhhjEuPw/F+w7PDZAXXQaV 3q5vOujXn5PKbwZtNF/654an9Wcmh85HxDtmp+pE99aqXrYC9OZb3NEB662y9reLmY7e KLDH0TNHbWBKxcdFcarwkBL79lc3my90v1GKvCV6VLMMmCvLKDZs4vepnjGPn0KTKWSv IFng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=rmFfS9+CInmXaKvLsHk/tFFfud0QKiBuvlJTD9SUPW4=; b=YxqpdhRsA9Qq9gc2DrdfWvoDaJ6fHLr/B3pVw+nEdezEXLsncvmAoepJbN4LLgAK2N 1Zhr5qbW+nCboLz4tNvNy3KUBQUgx7f14i/st7TweVlTo58GmQMQ5+G4f8ESxRsFb5yH jcMnSJfM+qyEYUS9dsFn5p/BK32zt7Rbcw+qGs7X2Dm95jt3u9lcY9AAbj/rjRntUcN0 i53iaQqSDGU+jqrtn5ZYW+difRgp7Xcln8qBfeTu5tHFC8S2qQnHxjwWwd3wLc96yM8T /+Z5II0aJWUUt7dmZrw1q0ufHpEQvyjh6eHmS7yL5nspaXjESywmme66Qrye1ExjHPBS XVJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="RmV/dek2"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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This patch adds support for Console UART, SPI NOR and SMPA1 regulator node. Signed-off-by: Devi Priya Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts | 80 +++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 834e790bec90..56ec3d84ad43 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts new file mode 100644 index 000000000000..f01de6628c3b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP453 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8"; + compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +};