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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id kv4-20020a17090778c400b0096ace683f1fsi1152088ejc.804.2023.05.25.17.53.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 17:53:17 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6A8F03858416 for ; Fri, 26 May 2023 00:53:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [207.46.229.174]) by sourceware.org (Postfix) with ESMTP id 9626B3858D3C for ; Fri, 26 May 2023 00:52:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9626B3858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from host040-ubuntu-1804.lxd (unknown [10.12.130.38]) by app2 (Coremail) with SMTP id EggMCgB3vpTaAnBkaMUbAA--.32468S4; Fri, 26 May 2023 08:52:42 +0800 (CST) From: Die Li To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Die Li Subject: [PATCH] RISC-V: Optimize TARGET_XTHEADCONDMOV Date: Fri, 26 May 2023 00:52:40 +0000 Message-Id: <20230526005240.86495-1-lidie@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: EggMCgB3vpTaAnBkaMUbAA--.32468S4 X-Coremail-Antispam: 1UD129KBjvJXoW3JF45ArW8Ww1xWw4xKFWUCFg_yoWfuFy5pF 43GrZ2vws7JasxuFn3tF4rAF1YkrsYqr1FvwsrJa43KrW7Ar98KFW8K34Iqw13WF98ur4r Ca1xKrn2kw4jqwUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JF0_Jw1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUov38UUUUU X-CM-SenderInfo: 5olgxv46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766915988747330036?= X-GMAIL-MSGID: =?utf-8?q?1766915988747330036?= This patch allows less instructions to be used when TARGET_XTHEADCONDMOV is enabled. Provide an example from the existing testcases. Testcase: int ConEmv_imm_imm_reg(int x, int y){ if (x == 1000) return 10; return y; } Cflags: -O2 -march=rv64gc_xtheadcondmov -mabi=lp64d before patch: ConEmv_imm_imm_reg: addi a5,a0,-1000 li a0,10 th.mvnez a0,zero,a5 th.mveqz a1,zero,a5 or a0,a0,a1 ret after patch: ConEmv_imm_imm_reg: addi a5,a0,-1000 li a0,10 th.mvnez a0,a1,a5 ret Signed-off-by: Die Li gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_conditional_move_onesided): Delete. (riscv_expand_conditional_move): Reuse the TARGET_SFB_ALU expand process for TARGET_XTHEADCONDMOV gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadcondmov-indirect-rv32.c: Update the output. * gcc.target/riscv/xtheadcondmov-indirect-rv64.c: Likewise. --- gcc/config/riscv/riscv.cc | 44 +++-------------- .../riscv/xtheadcondmov-indirect-rv32.c | 48 +++++++------------ .../riscv/xtheadcondmov-indirect-rv64.c | 48 +++++++------------ 3 files changed, 42 insertions(+), 98 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 09fc9e5d95e..8b8ac9181ba 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3442,37 +3442,6 @@ riscv_expand_conditional_branch (rtx label, rtx_code code, rtx op0, rtx op1) emit_jump_insn (gen_condjump (condition, label)); } -/* Helper to emit two one-sided conditional moves for the movecc. */ - -static void -riscv_expand_conditional_move_onesided (rtx dest, rtx cons, rtx alt, - rtx_code code, rtx op0, rtx op1) -{ - machine_mode mode = GET_MODE (dest); - - gcc_assert (GET_MODE_CLASS (mode) == MODE_INT); - gcc_assert (reg_or_0_operand (cons, mode)); - gcc_assert (reg_or_0_operand (alt, mode)); - - riscv_emit_int_compare (&code, &op0, &op1, true); - rtx cond = gen_rtx_fmt_ee (code, mode, op0, op1); - - rtx tmp1 = gen_reg_rtx (mode); - rtx tmp2 = gen_reg_rtx (mode); - - emit_insn (gen_rtx_SET (tmp1, gen_rtx_IF_THEN_ELSE (mode, cond, - cons, const0_rtx))); - - /* We need to expand a sequence for both blocks and we do that such, - that the second conditional move will use the inverted condition. - We use temporaries that are or'd to the dest register. */ - cond = gen_rtx_fmt_ee ((code == EQ) ? NE : EQ, mode, op0, op1); - emit_insn (gen_rtx_SET (tmp2, gen_rtx_IF_THEN_ELSE (mode, cond, - alt, const0_rtx))); - - emit_insn (gen_rtx_SET (dest, gen_rtx_IOR (mode, tmp1, tmp2))); - } - /* Emit a cond move: If OP holds, move CONS to DEST; else move ALT to DEST. Return 0 if expansion failed. */ @@ -3483,6 +3452,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) rtx_code code = GET_CODE (op); rtx op0 = XEXP (op, 0); rtx op1 = XEXP (op, 1); + bool need_eq_ne_p = false; if (TARGET_XTHEADCONDMOV && GET_MODE_CLASS (mode) == MODE_INT @@ -3492,14 +3462,12 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) && GET_MODE (op0) == mode && GET_MODE (op1) == mode && (code == EQ || code == NE)) + need_eq_ne_p = true; + + if (need_eq_ne_p || (TARGET_SFB_ALU + && GET_MODE (op0) == word_mode)) { - riscv_expand_conditional_move_onesided (dest, cons, alt, code, op0, op1); - return true; - } - else if (TARGET_SFB_ALU - && GET_MODE (op0) == word_mode) - { - riscv_emit_int_compare (&code, &op0, &op1); + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p); rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); /* The expander allows (const_int 0) for CONS for the benefit of diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c index 9afdc2eabfd..e2b135f3d00 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c @@ -1,15 +1,13 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=rv32gc_xtheadcondmov -mabi=ilp32 -mriscv-attribute" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Os" "-Og" "-O3" "-Oz" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ /* **ConEmv_imm_imm_reg: ** addi a5,a0,-1000 ** li a0,10 -** th.mvnez a0,zero,a5 -** th.mveqz a1,zero,a5 -** or a0,a0,a1 +** th.mvnez a0,a1,a5 ** ret */ int ConEmv_imm_imm_reg(int x, int y){ @@ -20,9 +18,8 @@ int ConEmv_imm_imm_reg(int x, int y){ /* **ConEmv_imm_reg_reg: ** addi a5,a0,-1000 -** th.mvnez a1,zero,a5 -** th.mveqz a2,zero,a5 -** or a0,a1,a2 +** th.mveqz a2,a1,a5 +** mv a0,a2 ** ret */ int ConEmv_imm_reg_reg(int x, int y, int z){ @@ -34,9 +31,7 @@ int ConEmv_imm_reg_reg(int x, int y, int z){ **ConEmv_reg_imm_reg: ** sub a1,a0,a1 ** li a0,10 -** th.mvnez a0,zero,a1 -** th.mveqz a2,zero,a1 -** or a0,a0,a2 +** th.mvnez a0,a2,a1 ** ret */ int ConEmv_reg_imm_reg(int x, int y, int z){ @@ -47,9 +42,8 @@ int ConEmv_reg_imm_reg(int x, int y, int z){ /* **ConEmv_reg_reg_reg: ** sub a1,a0,a1 -** th.mvnez a2,zero,a1 -** th.mveqz a3,zero,a1 -** or a0,a2,a3 +** th.mveqz a3,a2,a1 +** mv a0,a3 ** ret */ int ConEmv_reg_reg_reg(int x, int y, int z, int n){ @@ -59,12 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){ /* **ConNmv_imm_imm_reg: -** li a5,9998336 -** addi a4,a0,-1000 -** addi a5,a5,1664 -** th.mvnez a1,zero,a4 -** th.mveqz a5,zero,a4 -** or a0,a1,a5 +** addi a5,a0,-1000 +** li a0,9998336 +** addi a0,a0,1664 +** th.mveqz a0,a1,a5 ** ret */ int ConNmv_imm_imm_reg(int x, int y){ @@ -74,10 +66,9 @@ int ConNmv_imm_imm_reg(int x, int y){ /* **ConNmv_imm_reg_reg: -** addi a5,a0,-1000 -** th.mveqz a1,zero,a5 -** th.mvnez a2,zero,a5 -** or a0,a1,a2 +** addi a0,a0,-1000 +** th.mvnez a2,a1,a0 +** mv a0,a2 ** ret */ int ConNmv_imm_reg_reg(int x, int y, int z){ @@ -89,9 +80,7 @@ int ConNmv_imm_reg_reg(int x, int y, int z){ **ConNmv_reg_imm_reg: ** sub a1,a0,a1 ** li a0,10 -** th.mveqz a0,zero,a1 -** th.mvnez a2,zero,a1 -** or a0,a0,a2 +** th.mveqz a0,a2,a1 ** ret */ int ConNmv_reg_imm_reg(int x, int y, int z){ @@ -101,10 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){ /* **ConNmv_reg_reg_reg: -** sub a1,a0,a1 -** th.mveqz a2,zero,a1 -** th.mvnez a3,zero,a1 -** or a0,a2,a3 +** sub a0,a0,a1 +** th.mvnez a3,a2,a0 +** mv a0,a3 ** ret */ int ConNmv_reg_reg_reg(int x, int y, int z, int n){ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c index a1982fd90bd..99956f8496c 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c @@ -1,15 +1,13 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=rv64gc_xtheadcondmov -mabi=lp64d -mriscv-attribute" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Os" "-Og" "-O3" "-Oz" "-flto"} } */ /* { dg-final { check-function-bodies "**" "" } } */ /* **ConEmv_imm_imm_reg: ** addi a5,a0,-1000 ** li a0,10 -** th.mvnez a0,zero,a5 -** th.mveqz a1,zero,a5 -** or a0,a0,a1 +** th.mvnez a0,a1,a5 ** ret */ int ConEmv_imm_imm_reg(int x, int y){ @@ -19,10 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){ /* **ConEmv_imm_reg_reg: -** addi a5,a0,-1000 -** th.mvnez a1,zero,a5 -** th.mveqz a2,zero,a5 -** or a0,a1,a2 +** addi a0,a0,-1000 +** th.mveqz a2,a1,a5 +** mv a0,a2 ** ret */ int ConEmv_imm_reg_reg(int x, int y, int z){ @@ -34,9 +31,7 @@ int ConEmv_imm_reg_reg(int x, int y, int z){ **ConEmv_reg_imm_reg: ** sub a1,a0,a1 ** li a0,10 -** th.mvnez a0,zero,a1 -** th.mveqz a2,zero,a1 -** or a0,a0,a2 +** th.mvnez a0,a2,a1 ** ret */ int ConEmv_reg_imm_reg(int x, int y, int z){ @@ -47,9 +42,8 @@ int ConEmv_reg_imm_reg(int x, int y, int z){ /* **ConEmv_reg_reg_reg: ** sub a1,a0,a1 -** th.mvnez a2,zero,a1 -** th.mveqz a3,zero,a1 -** or a0,a2,a3 +** th.mveqz a3,a2,a1 +** mv a0,a3 ** ret */ int ConEmv_reg_reg_reg(int x, int y, int z, int n){ @@ -59,12 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){ /* **ConNmv_imm_imm_reg: -** li a5,9998336 -** addi a4,a0,-1000 -** addi a5,a5,1664 -** th.mvnez a1,zero,a4 -** th.mveqz a5,zero,a4 -** or a0,a1,a5 +** addi a5,a0,-1000 +** li a0,9998336 +** addi a0,a0,1664 +** th.mveqz a0,a1,a5 ** ret */ int ConNmv_imm_imm_reg(int x, int y){ @@ -75,9 +67,8 @@ int ConNmv_imm_imm_reg(int x, int y){ /* **ConNmv_imm_reg_reg: ** addi a5,a0,-1000 -** th.mveqz a1,zero,a5 -** th.mvnez a2,zero,a5 -** or a0,a1,a2 +** th.mvnez a2,a1,a0 +** mv a0,a2 ** ret */ int ConNmv_imm_reg_reg(int x, int y, int z){ @@ -89,9 +80,7 @@ int ConNmv_imm_reg_reg(int x, int y, int z){ **ConNmv_reg_imm_reg: ** sub a1,a0,a1 ** li a0,10 -** th.mveqz a0,zero,a1 -** th.mvnez a2,zero,a1 -** or a0,a0,a2 +** th.mveqz a0,a2,a1 ** ret */ int ConNmv_reg_imm_reg(int x, int y, int z){ @@ -101,10 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){ /* **ConNmv_reg_reg_reg: -** sub a1,a0,a1 -** th.mveqz a2,zero,a1 -** th.mvnez a3,zero,a1 -** or a0,a2,a3 +** sub a0,a0,a1 +** th.mvnez a3,a2,a0 +** mv a0,a3 ** ret */ int ConNmv_reg_reg_reg(int x, int y, int z, int n){