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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id q9-20020aa7da89000000b0050bd359a5ecsi1615642eds.195.2023.05.25.17.47.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 17:47:32 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Nl0tP4J0; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0665A385841C for ; Fri, 26 May 2023 00:47:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0665A385841C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685062051; bh=9qGVD6uzGIoip1vTYBx+e8tpVVcZftvki1vqvKu7lfM=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=Nl0tP4J0mwZh81KVw6FpxkAn7jI9zb2aFZVPu47PU8cC9n8MDxd5n4xBvNJATAhI6 feaF+NFLcCTJIE/T3+qTxqtIfd//i5NAWyGwysoJJMTS6BJlX4NqHRkFov7Axjdh1J Z84wuoGs+KZkeEwauGnmv4prgbjIVlNkLNz8A5yE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id E35443857712 for ; Fri, 26 May 2023 00:46:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E35443857712 X-IronPort-AV: E=McAfee;i="6600,9927,10721"; a="352912162" X-IronPort-AV: E=Sophos;i="6.00,192,1681196400"; d="scan'208";a="352912162" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2023 17:46:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10721"; a="879346066" X-IronPort-AV: E=Sophos;i="6.00,192,1681196400"; d="scan'208";a="879346066" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga005.jf.intel.com with ESMTP; 25 May 2023 17:46:26 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id D275F10054E2; Fri, 26 May 2023 08:46:25 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc Date: Fri, 26 May 2023 08:46:24 +0800 Message-Id: <20230526004624.3051349-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766915626506419732?= X-GMAIL-MSGID: =?utf-8?q?1766915626506419732?= From: Pan Li This patch would like to remove the magic number in the riscv-v.cc, and align the same value to one macro. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_insn): Eliminate the magic number. (emit_nonvlmax_insn): Ditto. (emit_vlmax_merge_insn): Ditto. (emit_vlmax_cmp_insn): Ditto. (emit_vlmax_cmp_mu_insn): Ditto. (expand_vec_series): Ditto. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-v.cc | 77 ++++++++++++++++++++++--------------- 1 file changed, 46 insertions(+), 31 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 458020ce0a1..20b589bf51b 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -351,13 +351,15 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl) { machine_mode data_mode = GET_MODE (ops[0]); machine_mode mask_mode = get_mask_mode (data_mode).require (); - /* We have a maximum of 11 operands for RVV instruction patterns according to - * vector.md. */ - insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ true, - /*USE_REAL_MERGE_P*/ false, /*HAS_AVL_P*/ true, - /*VLMAX_P*/ true, - /*DEST_MODE*/ data_mode, /*MASK_MODE*/ mask_mode); + insn_expander e (/*OP_NUM*/ op_num, + /*HAS_DEST_P*/ true, + /*FULLY_UNMASKED_P*/ true, + /*USE_REAL_MERGE_P*/ false, + /*HAS_AVL_P*/ true, + /*VLMAX_P*/ true, + /*DEST_MODE*/ data_mode, + /*MASK_MODE*/ mask_mode); + e.set_policy (TAIL_ANY); e.set_policy (MASK_ANY); /* According to LRA mov pattern in vector.md, we have a clobber operand @@ -373,13 +375,15 @@ emit_nonvlmax_insn (unsigned icode, int op_num, rtx *ops, rtx avl) { machine_mode data_mode = GET_MODE (ops[0]); machine_mode mask_mode = get_mask_mode (data_mode).require (); - /* We have a maximum of 11 operands for RVV instruction patterns according to - * vector.md. */ - insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ true, - /*USE_REAL_MERGE_P*/ false, /*HAS_AVL_P*/ true, - /*VLMAX_P*/ false, - /*DEST_MODE*/ data_mode, /*MASK_MODE*/ mask_mode); + insn_expander e (/*OP_NUM*/ op_num, + /*HAS_DEST_P*/ true, + /*FULLY_UNMASKED_P*/ true, + /*USE_REAL_MERGE_P*/ false, + /*HAS_AVL_P*/ true, + /*VLMAX_P*/ false, + /*DEST_MODE*/ data_mode, + /*MASK_MODE*/ mask_mode); + e.set_policy (TAIL_ANY); e.set_policy (MASK_ANY); e.set_vl (avl); @@ -392,10 +396,15 @@ emit_vlmax_merge_insn (unsigned icode, int op_num, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); machine_mode mask_mode = get_mask_mode (dest_mode).require (); - insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ false, - /*USE_REAL_MERGE_P*/ false, /*HAS_AVL_P*/ true, - /*VLMAX_P*/ true, dest_mode, mask_mode); + insn_expander e (/*OP_NUM*/ op_num, + /*HAS_DEST_P*/ true, + /*FULLY_UNMASKED_P*/ false, + /*USE_REAL_MERGE_P*/ false, + /*HAS_AVL_P*/ true, + /*VLMAX_P*/ true, + /*DEST_MODE*/ dest_mode, + /*MASK_MODE*/ mask_mode); + e.set_policy (TAIL_ANY); e.emit_insn ((enum insn_code) icode, ops); } @@ -405,12 +414,15 @@ void emit_vlmax_cmp_insn (unsigned icode, rtx *ops) { machine_mode mode = GET_MODE (ops[0]); - insn_expander<11> e (/*OP_NUM*/ RVV_CMP_OP, /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ true, - /*USE_REAL_MERGE_P*/ false, - /*HAS_AVL_P*/ true, - /*VLMAX_P*/ true, - /*DEST_MODE*/ mode, /*MASK_MODE*/ mode); + insn_expander e (/*OP_NUM*/ RVV_CMP_OP, + /*HAS_DEST_P*/ true, + /*FULLY_UNMASKED_P*/ true, + /*USE_REAL_MERGE_P*/ false, + /*HAS_AVL_P*/ true, + /*VLMAX_P*/ true, + /*DEST_MODE*/ mode, + /*MASK_MODE*/ mode); + e.set_policy (MASK_ANY); e.emit_insn ((enum insn_code) icode, ops); } @@ -420,12 +432,15 @@ void emit_vlmax_cmp_mu_insn (unsigned icode, rtx *ops) { machine_mode mode = GET_MODE (ops[0]); - insn_expander<11> e (/*OP_NUM*/ RVV_CMP_MU_OP, /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ false, - /*USE_REAL_MERGE_P*/ true, - /*HAS_AVL_P*/ true, - /*VLMAX_P*/ true, - /*DEST_MODE*/ mode, /*MASK_MODE*/ mode); + insn_expander e (/*OP_NUM*/ RVV_CMP_MU_OP, + /*HAS_DEST_P*/ true, + /*FULLY_UNMASKED_P*/ false, + /*USE_REAL_MERGE_P*/ true, + /*HAS_AVL_P*/ true, + /*VLMAX_P*/ true, + /*DEST_MODE*/ mode, + /*MASK_MODE*/ mode); + e.set_policy (MASK_UNDISTURBED); e.emit_insn ((enum insn_code) icode, ops); } @@ -443,7 +458,7 @@ expand_vec_series (rtx dest, rtx base, rtx step) /* Step 1: Generate I = { 0, 1, 2, ... } by vid.v. */ rtx vid = gen_reg_rtx (mode); - rtx op[1] = {vid}; + rtx op[] = {vid}; emit_vlmax_insn (code_for_pred_series (mode), RVV_MISC_OP, op); /* Step 2: Generate I * STEP.