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Signed-off-by: Shenwei Wang Reviewed-by: Peng Fan --- .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi index 815bd987b09b..5306d2b3fc3f 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -6,41 +6,82 @@ &lsio_gpio0 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 47 13>, + <&iomuxc 13 61 4>, + <&iomuxc 19 67 4>, + <&iomuxc 24 72 1>; }; &lsio_gpio1 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 4 74 5>, + <&iomuxc 9 80 16>; }; &lsio_gpio2 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 1 98 2>, + <&iomuxc 3 101 1>, + <&iomuxc 5 107 8>; }; &lsio_gpio3 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 115 4>, + <&iomuxc 9 121 1>, + <&iomuxc 10 120 1>, + <&iomuxc 11 123 1>, + <&iomuxc 12 122 1>, + <&iomuxc 13 125 1>, + <&iomuxc 14 124 1>, + <&iomuxc 16 126 1>, + <&iomuxc 17 128 1>, + <&iomuxc 18 131 1>, + <&iomuxc 19 130 1>, + <&iomuxc 20 133 1>, + <&iomuxc 21 132 1>, + <&iomuxc 22 129 1>, + <&iomuxc 23 134 1>; }; &lsio_gpio4 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 7 9 12>, + <&iomuxc 19 22 2>, + <&iomuxc 21 25 2>, + <&iomuxc 29 29 3>; }; &lsio_gpio5 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 32 3>, + <&iomuxc 3 36 6>, + <&iomuxc 9 43 3>; }; &lsio_gpio6 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 53 7>, + <&iomuxc 8 86 10>, + <&iomuxc 19 107 8>; }; &lsio_gpio7 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 8 22 2>, + <&iomuxc 10 25 2>, + <&iomuxc 16 44 2>; }; &lsio_mu0 { From patchwork Tue Oct 25 18:32:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 10925 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1158199wru; Tue, 25 Oct 2022 11:38:46 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5VNxNJ/NjG/ZBMBgKhpxYfZuEfB6VMXpdalXX7O+2yqQx0eFbFOc1bELWeESb7L0tDziY0 X-Received: by 2002:a17:90b:1b05:b0:20d:3b10:3800 with SMTP id nu5-20020a17090b1b0500b0020d3b103800mr81921247pjb.91.1666723116164; Tue, 25 Oct 2022 11:38:36 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666723116; cv=pass; d=google.com; s=arc-20160816; b=C6xEgXKhgEb4j11HVxWQQGJLzllyWI2lOL8hi5SfsA6B81wIRvbjIfikvusOY7sdd9 BN9yIcNKf8zyldCBvADnEm8nzorUVVwqcDo6NrwF+ZiJj74gQT7rxZDK1UxdvuheFr/8 0alCxwNJRTHTnjJBs/MepcbOfUxElg3F2tRYovwiAsQCRY9aPrugtbesJ2b+fgAQjGhq OqCg6BTFXGHYF2faF441iyiZc4bqmX0zEqvOYZoUGPuHKs0lF8M0WUT67yMMswIb+FYA BVXgJ0RHYir/Rb8ywfgGwMacqZNF+2e4V/a796LjYq+ChIhJsCywbe0F7ruHxOZZ2s0R IbMg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=S6R7XbY/QK+4Jb5hG3+4tm7r/yRhLZZvVmeuGrlAlH0=; b=1BEYXAHbOC6+a5i5iqGfusFUfeuFWHn4xiQDSSR/h+aBRd1ZOGOEgIIm6BRqRBlUMk AHKI+ja7osS2PM32dQuWPA2Ho6024z/GjCMdscc9NuBq8grMm7Y/VM17CnxuO5JB3XCC PaetiqUPEyQaMLeekANFi9bj+yj5nSCK0upN5Fnzk5FujjcXT/kRmlOzuvtH8NSTKKts x0ys8Lfv8axebrSaZwuGkyfnZbAo7YGuLqUyoNdufvTGCeEdO9w4H7XdauUsToimIg1y 4P673wBY7aBbyyVL/QG5aPdCIT/TE9TRI8k+gZgrk9kbRaW75Gi003fugWpdcL68NJ8C kJUw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=lcUm87l9; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Shenwei Wang Reviewed-by: Peng Fan --- .../boot/dts/freescale/imx8qm-ss-lsio.dtsi | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi index 669aa14ce9f7..b483134f84d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -6,30 +6,68 @@ &lsio_gpio0 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 0 6>, + <&iomuxc 6 7 22>, + <&iomuxc 28 36 4>; }; &lsio_gpio1 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 40 4>, + <&iomuxc 4 50 12>, + <&iomuxc 16 63 8>, + <&iomuxc 24 72 8>; }; &lsio_gpio2 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 80 4>, + <&iomuxc 4 85 18>, + <&iomuxc 22 104 10>; }; &lsio_gpio3 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 114 2>, + <&iomuxc 2 117 16>, + <&iomuxc 18 141 1>, + <&iomuxc 19 140 1>, + <&iomuxc 20 139 1>, + <&iomuxc 21 138 1>, + <&iomuxc 22 137 1>, + <&iomuxc 23 136 1>, + <&iomuxc 24 135 1>, + <&iomuxc 25 134 1>, + <&iomuxc 26 142 3>, + <&iomuxc 29 146 3>; }; &lsio_gpio4 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 149 3>, + <&iomuxc 3 153 4>, + <&iomuxc 7 158 6>, + <&iomuxc 13 165 6>, + <&iomuxc 19 172 8>, + <&iomuxc 27 198 5>; }; &lsio_gpio5 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 203 1>, + <&iomuxc 1 205 2>, + <&iomuxc 3 210 11>, + <&iomuxc 14 223 3>, + <&iomuxc 17 227 2>, + <&iomuxc 19 230 5>, + <&iomuxc 24 236 6>, + <&iomuxc 30 243 2>; }; &lsio_gpio6 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 245 10>, + <&iomuxc 10 256 12>; }; &lsio_gpio7 { From patchwork Tue Oct 25 18:32:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 10926 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1158237wru; Tue, 25 Oct 2022 11:38:51 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6wriZnICKWdaYARgoHv2/XQPzHRdGtKR7NxjRrQuVzFjteDiR8kTm8PdZugKaEqF94CW9Y X-Received: by 2002:a05:6402:27c9:b0:45d:4539:b462 with SMTP id c9-20020a05640227c900b0045d4539b462mr36948073ede.226.1666723131756; Tue, 25 Oct 2022 11:38:51 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666723131; cv=pass; d=google.com; s=arc-20160816; b=KqI1xOrPVBDO94gGQWz5LIUr8vm3LJ9qP7ujmkecRC7xiMYFpWr/5psokDOb0jzr0o S9IRCkUprYPc+L/pw6MgxZ7iJNJX5mziRZz0Y1rxlg0cz+cG45z4yhr0+/1DulCq7gml Y5y9qUt8/zJkBmxn0SLGc3wjqQNcLqC82OaUr5aOqe/yNES3TrSO1VqdlynzHPhZ/0sO GPo7QFAOSmljqeSq7BVp3FLEmKb/pDwZBbFpDgBTYfybMJ5ogbUiF2H7t4Nc1cs7olTJ Ugm/+nafSx0aIpijHhxC/pZeDu/H7AJOMFiIbETUlvQkZ7fYH7pRREMOfPKz2uIMkALv RfkQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MvNRGO9FYjSRVBb27KW/tFvor3/VmOFsdI3W3Y3QopU=; b=fkX24AIZPNUo7HVXchtwRoit6iJj23aZw5+Bz77aIWRhwIscN0P+1uMkSFWH7GcxON E/Uo5Eoyx5BPJmR/TAhrftBKWLw9HeorUyufqHPwSGcp62sckJiyHj29gY4Kfsj2n9j5 IEI8v+ZZUynUsAVPhd0FdKyTT7zJUn0OfuD0b/6zP8Nn/DNv+rQKdlL/OuAlEmjxMXbN oB+ME0hV1P4P94Cvv9NeXvAunh+F/IhRPxKLVkyt0KVC2JnRLuBfuCsDuvLBhPAFXc6F 2HBivndbaqCeFrJCTwX3fRqy9oMZMRlf3McmCAA0TeNb5hSdNBaNM5Zz9ylDJu4oqzqr GJMg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=Mp2C84+G; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Shenwei Wang Reviewed-by: Peng Fan --- .../boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index 8e2152c6eb88..8f722b1dd078 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -6,26 +6,51 @@ &lsio_gpio0 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 1 56 12>, + <&iomuxc 13 69 4>, + <&iomuxc 19 75 4>, + <&iomuxc 24 80 1>, + <&iomuxc 25 82 7>; }; &lsio_gpio1 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 89 9>, + <&iomuxc 9 99 16>, + <&iomuxc 25 116 7>; }; &lsio_gpio2 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 123 1>, + <&iomuxc 1 126 2>, + <&iomuxc 3 129 1>; }; &lsio_gpio3 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 146 4>, + <&iomuxc 4 151 13>, + <&iomuxc 17 165 8>; }; &lsio_gpio4 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 7 9 6>, + <&iomuxc 13 16 6>, + <&iomuxc 19 23 2>, + <&iomuxc 21 26 2>, + <&iomuxc 23 30 6>, + <&iomuxc 29 37 3>; }; &lsio_gpio5 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 40 3>, + <&iomuxc 3 44 6>, + <&iomuxc 9 51 3>; }; &lsio_gpio6 { From patchwork Tue Oct 25 18:32:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 10927 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1158352wru; Tue, 25 Oct 2022 11:39:10 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7FOiH7mh5acEItqgy3g2PWiwqLHwdumoBaidu8IOzASpyks7QT7tMXngdX1nzKP7hGWkp9 X-Received: by 2002:a05:6a00:8cb:b0:52c:6962:2782 with SMTP id s11-20020a056a0008cb00b0052c69622782mr40454218pfu.81.1666723149739; Tue, 25 Oct 2022 11:39:09 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666723149; cv=pass; d=google.com; s=arc-20160816; b=FSj8NQnN+BCncXmIXta0VVzRNhKgC44ysx9ir+G162NJg7NezvfQqQtgVjEbI22tRV XIZ9gz32HqMGn4GsNbvl9fVXOrPd4GwlbHuwFekb91ch7pWbomF/O+yZqA6k/vies28L o3GpDq8tPPvcqFcj1Fj02BLll+PIrpAuuhIYxyZ5S0NGcwldGZ89w7d0UW4Z76Tu6i7t fyPLbljHwP/mQZh4qOFYbkoD/oJH8FUUEG65Jsv4Nk5PBTk+r1qjV7qLHR72QBesaf48 qqb5f1Hh0wYu3HTV4cJCAboxnW2Uy21LLtYiULZbTX3wfWIJQIz7053+OwMyS3ZJHQtA 5Vvw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8xf3M/pDapRpv9SPS1/daqxjwo3pBb33QMXB95kKr6A=; b=ipwke2F3da9CL6oeA1LpJmC10krfIOLyUQA+tPBRzozLEONw2GdwvkTBVuVtihswIz 0y9/GRZzfyrSCUlTMWj3iDt5tpplNQPi9knPgEGSsbhiGYoxUDWAx7ROpcf4f99TJEx3 je9LjVNrjFor3Y3W6QsIuaysT8aoGL4z7ThkFBLRCpz6IF97NK9Dr/a5o08zq6AbKPQt IFm4n2i/s41f5tW+l2kpVxkprAApbN/4VJM9wMtrUQGzT0VqWlGoA4j5KlEwDYUfXE5R ddwz7HmDQd5zAz56X35lbP5OTwkjRPsKd7vM8ddnsiWze6XxGvXwMjy9IYFFanIS+3VE q2pA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=apTgx34V; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Shenwei Wang --- drivers/pinctrl/freescale/pinctrl-scu.c | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c index 59b5f8a35111..0b172f7e7261 100644 --- a/drivers/pinctrl/freescale/pinctrl-scu.c +++ b/drivers/pinctrl/freescale/pinctrl-scu.c @@ -15,6 +15,11 @@ #include "../core.h" #include "pinctrl-imx.h" +#define IMX_SC_PAD_FUNC_GET_WAKEUP 9 +#define IMX_SC_PAD_FUNC_SET_WAKEUP 4 +#define IMX_SC_IRQ_GROUP_WAKE 3 /* Wakeup interrupts */ +#define IMX_SC_IRQ_PAD 2 /* Pad wakeup */ + enum pad_func_e { IMX_SC_PAD_FUNC_SET = 15, IMX_SC_PAD_FUNC_GET = 16, @@ -36,10 +41,18 @@ struct imx_sc_msg_resp_pad_get { u32 val; } __packed; +struct imx_sc_msg_gpio_set_pad_wakeup { + struct imx_sc_rpc_msg hdr; + u16 pad; + u8 wakeup; +} __packed __aligned(4); + static struct imx_sc_ipc *pinctrl_ipc_handle; int imx_pinctrl_sc_ipc_init(struct platform_device *pdev) { + imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_WAKE, + IMX_SC_IRQ_PAD, true); return imx_scu_get_handle(&pinctrl_ipc_handle); } EXPORT_SYMBOL_GPL(imx_pinctrl_sc_ipc_init); @@ -81,6 +94,23 @@ int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned int val; int ret; + if (num_configs == 1) { + struct imx_sc_msg_gpio_set_pad_wakeup wmsg; + + hdr = &wmsg.hdr; + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_PAD; + hdr->func = IMX_SC_PAD_FUNC_SET_WAKEUP; + hdr->size = 2; + wmsg.pad = pin_id; + wmsg.wakeup = *configs; + ret = imx_scu_call_rpc(pinctrl_ipc_handle, &wmsg, true); + + dev_dbg(ipctl->dev, "wakeup pin_id: %d type: %d\n", + pin_id, *configs); + return ret; + } + /* * Set mux and conf together in one IPC call */ From patchwork Tue Oct 25 18:32:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 10928 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1158410wru; Tue, 25 Oct 2022 11:39:19 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7I1QNb1TYvHsXBtJ5ykjlZVXB9YH0qRPuo7qgeeGOyZYAVHYTyEXZ3/x5z8Rm9JhGqHMlL X-Received: by 2002:a17:90b:33cb:b0:212:f276:62ce with SMTP id lk11-20020a17090b33cb00b00212f27662cemr19083197pjb.149.1666723159399; Tue, 25 Oct 2022 11:39:19 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666723159; cv=pass; d=google.com; s=arc-20160816; b=HRLWDrL3dN+4LfUx0aOezqIsMvkwzvQy8H/sn7XGvHuRloVfRLxWzR0fIr5Wr5EycE 2BKEB8pbHSHKi5vpjApEV1gEAeAJD2SANLs7U0JJJSGarEsMu8zJDW5t8IDUi6Ywj8u4 jG/yDUuZCpap7lS2kOz0RjNA9YjfwMYEu8VJBYmNVz4B2qST5f8ZfI0pPxANRDDDUnyH KxC/MQBS3tSLlVSJG2s0li/kYkvNY/MyzEZgva6F2KWBFNyqQuYQaFjF7IY/RJAKe0Na xbI1EWE49dlJ0Mb6O80STYH79JzvSqkspv3kH2EJnvZU8Zxo1JxXSSo6y3eTVyt0rnuC cwPw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HK8umn/SaBCLANQD/iiVYz01sajoRlXqGCOCY0E7X04=; b=vP8bWXyH/r4a2oYRsxfSaQ8YhiG06C5W6MH3OV2W8bhEl31B3eoC6kQVn5PVWf/XrS 9hzEnxxTB/yKj68b+wp9j8cE5xR/GgCy3QQ0z73E2/7OyQmyi8X/naEmoTPuJ/zVuylf 6LVoMdIN0GUNpYlzrZZG+4a24/sHjnkKcGHK+rT1jsmGAeyeonBRy0UNsJoAIQwqkuYs ao+t9HF9KtxSRyLte4EI5zJxzBXfBAgRT43E8sCwj7K1ssLKVu3mbDQPTpeA0wcbFJc5 cg+8nXAlB+iGhw6+K9ZPVh0M3wS63RFg7sg9UkJcFsFDdDwxUSQcNB81toeXGlQIClXu RbIw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=aMkrsmzj; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Received: from PAXPR04MB9185.eurprd04.prod.outlook.com (2603:10a6:102:231::11) by AS1PR04MB9581.eurprd04.prod.outlook.com (2603:10a6:20b:470::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.33; Tue, 25 Oct 2022 18:33:35 +0000 Received: from PAXPR04MB9185.eurprd04.prod.outlook.com ([fe80::4150:173b:56ec:dc6c]) by PAXPR04MB9185.eurprd04.prod.outlook.com ([fe80::4150:173b:56ec:dc6c%9]) with mapi id 15.20.5746.028; Tue, 25 Oct 2022 18:33:35 +0000 From: Shenwei Wang To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Linus Walleij , Bartosz Golaszewski , Dong Aisheng , Jacky Bai Cc: Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Shenwei Wang , Peng Fan , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v3 5/5] gpio: mxc: enable pad wakeup on i.MX8x platforms Date: Tue, 25 Oct 2022 13:32:44 -0500 Message-Id: <20221025183244.615318-6-shenwei.wang@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221025183244.615318-1-shenwei.wang@nxp.com> References: <20221025183244.615318-1-shenwei.wang@nxp.com> X-ClientProxiedBy: BY5PR17CA0028.namprd17.prod.outlook.com (2603:10b6:a03:1b8::41) To PAXPR04MB9185.eurprd04.prod.outlook.com (2603:10a6:102:231::11) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9185:EE_|AS1PR04MB9581:EE_ X-MS-Office365-Filtering-Correlation-Id: 1dbaaf33-c275-4241-bf41-08dab6b76d54 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This can greatly reduce the power consumption of suspend state because the whole partition can be shutdown. This is called PAD wakeup feature on i.MX8x platform. This patch adds the noirq suspend/resume hooks and uses the pad wakeup feature as the default wakeup method for GPIO modules on i.MX8QM/QXP/DXL platforms. Signed-off-by: Shenwei Wang --- drivers/gpio/gpio-mxc.c | 91 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index c871602fc5ba..a6fe5ed3d320 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -24,6 +24,12 @@ #include #include +#define IMX_SCU_WAKEUP_OFF 0 +#define IMX_SCU_WAKEUP_LOW_LVL 4 +#define IMX_SCU_WAKEUP_FALL_EDGE 5 +#define IMX_SCU_WAKEUP_RISE_EDGE 6 +#define IMX_SCU_WAKEUP_HIGH_LVL 7 + /* device type dependent stuff */ struct mxc_gpio_hwdata { unsigned dr_reg; @@ -61,6 +67,9 @@ struct mxc_gpio_port { u32 both_edges; struct mxc_gpio_reg_saved gpio_saved_reg; bool power_off; + u32 wakeup_pads; + bool is_pad_wakeup; + u32 pad_type[32]; const struct mxc_gpio_hwdata *hwdata; }; @@ -130,6 +139,9 @@ static const struct of_device_id mxc_gpio_dt_ids[] = { { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata }, { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata }, { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); @@ -203,6 +215,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) } writel(1 << gpio_idx, port->base + GPIO_ISR); + port->pad_type[gpio_idx] = type; return 0; } @@ -254,6 +267,9 @@ static void mx3_gpio_irq_handler(struct irq_desc *desc) struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); + if (port->is_pad_wakeup) + return; + chained_irq_enter(chip, desc); irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); @@ -306,11 +322,13 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable) ret = enable_irq_wake(port->irq_high); else ret = enable_irq_wake(port->irq); + port->wakeup_pads |= (1<irq_high && (gpio_idx >= 16)) ret = disable_irq_wake(port->irq_high); else ret = disable_irq_wake(port->irq); + port->wakeup_pads &= ~(1<dev = &pdev->dev; - port->hwdata = device_get_match_data(&pdev->dev); port->base = devm_platform_ioremap_resource(pdev, 0); @@ -498,6 +515,77 @@ static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); } +static int mxc_gpio_generic_config(struct mxc_gpio_port *port, + unsigned int offset, unsigned long config) +{ + struct device_node *np = port->dev->of_node; + + if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") || + of_device_is_compatible(np, "fsl,imx8qxp-gpio") || + of_device_is_compatible(np, "fsl,imx8qm-gpio")) + return gpiochip_generic_config(&port->gc, offset, config); + + return 0; +} + +static void mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable) +{ + unsigned long config; + int i, type; + + static const u32 pad_type_map[] = { + IMX_SCU_WAKEUP_OFF, /* 0 */ + IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */ + IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */ + IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */ + IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */ + IMX_SCU_WAKEUP_OFF, /* 5 */ + IMX_SCU_WAKEUP_OFF, /* 6 */ + IMX_SCU_WAKEUP_OFF, /* 7 */ + IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */ + }; + + for (i = 0; i < 32; i++) { + if ((port->wakeup_pads & (1<pad_type[i]; + if (enable) + config = pad_type_map[type]; + else + config = IMX_SCU_WAKEUP_OFF; + mxc_gpio_generic_config(port, i, config); + } + } +} + +static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + if (port->wakeup_pads > 0) { + mxc_gpio_set_pad_wakeup(port, true); + port->is_pad_wakeup = true; + } + + return 0; +} + +static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + if (port->wakeup_pads > 0) + mxc_gpio_set_pad_wakeup(port, false); + port->is_pad_wakeup = false; + + return 0; +} + +static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume) +}; + static int mxc_gpio_syscore_suspend(void) { struct mxc_gpio_port *port; @@ -537,6 +625,7 @@ static struct platform_driver mxc_gpio_driver = { .name = "gpio-mxc", .of_match_table = mxc_gpio_dt_ids, .suppress_bind_attrs = true, + .pm = &mxc_gpio_dev_pm_ops, }, .probe = mxc_gpio_probe, };