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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n11-20020a05640205cb00b0045dacc047fcsi538328edx.559.2022.10.25.11.08.14; Tue, 25 Oct 2022 11:08:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232550AbiJYSGy (ORCPT + 99 others); Tue, 25 Oct 2022 14:06:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231244AbiJYSGv (ORCPT ); Tue, 25 Oct 2022 14:06:51 -0400 Received: from relay02.th.seeweb.it (relay02.th.seeweb.it [IPv6:2001:4b7a:2000:18::163]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92BF311F for ; Tue, 25 Oct 2022 11:06:49 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2a00:f41:181d:45ba:3479:f7c2:4c21:3ad3]) (using TLSv1.3 with cipher TLS_CHACHA20_POLY1305_SHA256 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA512) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 02D2820097; Tue, 25 Oct 2022 20:06:45 +0200 (CEST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Robin Murphy , Luca Weiss , Iskren Chernev , Thierry Reding , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: arm: cpus: Add Kryo 660 CPUs Date: Tue, 25 Oct 2022 20:06:30 +0200 Message-Id: <20221025180634.28956-1-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747683976437859497?= X-GMAIL-MSGID: =?utf-8?q?1747683976437859497?= Add a compatible for Kryo 660 CPUs found in at least Qualcomm SM6375. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Changes since v1: - Pick up Krzysztof's A-b Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5c13b73e4d57..b2058345bb8e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -183,6 +183,7 @@ properties: - qcom,kryo485 - qcom,kryo560 - qcom,kryo570 + - qcom,kryo660 - qcom,kryo685 - qcom,kryo780 - qcom,scorpion From patchwork Tue Oct 25 18:06:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 10918 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1147137wru; Tue, 25 Oct 2022 11:12:16 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6NKMYGXXfJ6HoIILxgLYAcLg2V9ng5Wkoihn7YUQ9q/IYDUvGNgD80QFx5T1rDqPOKqdC+ X-Received: by 2002:a17:907:8688:b0:791:91a0:fdb3 with SMTP id qa8-20020a170907868800b0079191a0fdb3mr31982204ejc.499.1666721525878; Tue, 25 Oct 2022 11:12:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666721525; cv=none; d=google.com; s=arc-20160816; b=jTaMU/rpqnJDEcu/camz9LNgr2Eu5ZNUNwM7a+aMYbfvjYZZpR5hntap5nB641xtqI IP/29YMvhhIqzQk9XvuV1Vfp6C2xuPadEjjqCr9bDUJ+ZfHrled/3PteK8lhddUdPk1b gvuJegjEDxRlMycYpapc+qE66wNAQmMGde9gE2MQ6JmJ2PPfzZXyhRt0rUYgiYa0W1M0 YiCnGmmrtVN2LOmhaR0EI4NtNEeDtuiq9fXD5fHQPbEwBXis8INBbrDxI9yG0u9jcClo iYppwflagpFuKUOTDebc4BqgnrheEvKwZRh/orjkbNxDDojRtTm9X7xJFmWTLXmVsKCO zuyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=q5fZ9nfQWS6IscJGg8ZAcBEkE6mi2HYfRpR3oQIiLDE=; b=E4LH99/hZ57nXZsPRR1YQ+3RHPj4i5xi3fF20mWoH9jOpnedcwTEUUe926M4RbAkQR PoL6sMN6KomXl+9S7GkWDNJC6LGda5Uq4ybZ5l4/T+VM0iEDiVYRjVmWw79ckeIu2xJf OkUiq8iozpB2iCBom0flezydoWs5ttyw0Cn4gjLlRnwB7hETA+OJi/ZuHP5LRowMuyv2 8GpktOEaweEKfbcXKRF4eQcig6E+W49jjOzam4Z4QeuD/lzqFsdUjkDCrRbAvLzD+f6M mLnnkvDMs1VIg3EdPcegxyi54SzrYtdaYGkJByvyjz6QFBgSH+qIhd87VJBT7bJaMvC9 5dGw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w15-20020aa7da4f000000b0046155426889si3047560eds.272.2022.10.25.11.11.22; Tue, 25 Oct 2022 11:12:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232608AbiJYSHB (ORCPT + 99 others); Tue, 25 Oct 2022 14:07:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231814AbiJYSGy (ORCPT ); Tue, 25 Oct 2022 14:06:54 -0400 Received: from relay03.th.seeweb.it (relay03.th.seeweb.it [IPv6:2001:4b7a:2000:18::164]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B60E167E3 for ; Tue, 25 Oct 2022 11:06:50 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2a00:f41:181d:45ba:3479:f7c2:4c21:3ad3]) (using TLSv1.3 with cipher TLS_CHACHA20_POLY1305_SHA256 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA512) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 5613B200BA; Tue, 25 Oct 2022 20:06:47 +0200 (CEST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Robin Murphy , Luca Weiss , Iskren Chernev , Thierry Reding , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] dt-bindings: arm: qcom: Document SM6375 & Xperia 10 IV Date: Tue, 25 Oct 2022 20:06:31 +0200 Message-Id: <20221025180634.28956-2-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221025180634.28956-1-konrad.dybcio@somainline.org> References: <20221025180634.28956-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747684190910689878?= X-GMAIL-MSGID: =?utf-8?q?1747684190910689878?= Add compatibles for Sony Xperia 10 IV (PDX225) and the SM6375 SoC it's based on. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Changes since v1: - Pick up Krzysztof's R-b Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 207e28260206..35e22cf15f9f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -56,6 +56,7 @@ description: | sdx65 sm6125 sm6350 + sm6375 sm7225 sm8150 sm8250 @@ -718,6 +719,11 @@ properties: - sony,pdx213 - const: qcom,sm6350 + - items: + - enum: + - sony,pdx225 + - const: qcom,sm6375 + - items: - enum: - fairphone,fp4 From patchwork Tue Oct 25 18:06:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 10919 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1147282wru; Tue, 25 Oct 2022 11:12:33 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4fEtsD4cK7EYx2d2Hod/SgjQex1x33St2q1ZSOqLMUkAX4Z560MNlXh8WSx3yhFnrjjHbk X-Received: by 2002:a17:907:5c2:b0:77e:def7:65d8 with SMTP id wg2-20020a17090705c200b0077edef765d8mr34231389ejb.487.1666721553241; Tue, 25 Oct 2022 11:12:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666721553; cv=none; d=google.com; s=arc-20160816; b=DmffNPxeIZ7QVdsuu6VElrunuHNjFG3CQhtXifgsoT2l0dEbV5A+DUTxExYXEwpltO WUTYwgz35JlohGRWCncsDubDDtfRDe6oGc+b8tm9ljGvCNvrEsqlh2QSt3Ty4E3MucY1 a71pj3jiG/WlCHGIREbk22MoCoOABtg0ucztK+hGh+dALaeIEJNIQW2xd/CrPpLU3Iai J1HmpCJ/pySso8CTu3WZTskcjVBpLHlVlczhkDU3SCYVwEq/gl1PoV4GShJzXgwe4sV+ TqwImPmAN45G3PR9i3a83FvB2LD2p6wvlF1zDD+o4CV+5tOup+9B/rWScRJqBS5jLaev Q8bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Wz3zahgOymSaD40Pd9PwApSLdg0df7XwQ+tGXpaGiKA=; b=NgKMjm0XsARhlm8wGgJti4kr67te75Qgdu2EJyEf9AGu1Apo15E+kYwGRagvOMpW+v mBoiDyUH15oX7RuFD+4PtGl+PAAHjczct3f+NL77yxn3htvmP7dhDvHIB4O62nbxwDFO verH5k6d1vjYeXMufNfYBQfL6bJvuONw0/RPKaHc2Wm2mSmv9tuRwfaJaV9W6JqLVOKM fz1FjbIVU9hxZIooj3RKGIQYQBnoaNM88gd0UNqo3XvAMPOzd+MD+H9HEXo29lfatFR8 mc9QtdLu8fnwfyJnIUvgUrnRcM0zaHYLrHpn7XiyUHq+PTDyWnrAlHQP6QEb8luP6w7U d3Kw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x9-20020aa7d389000000b004573c1ae3fasi3084841edq.285.2022.10.25.11.12.00; Tue, 25 Oct 2022 11:12:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232619AbiJYSHE (ORCPT + 99 others); Tue, 25 Oct 2022 14:07:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232568AbiJYSGz (ORCPT ); Tue, 25 Oct 2022 14:06:55 -0400 Received: from m-r1.th.seeweb.it (m-r1.th.seeweb.it [5.144.164.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F03EFB7E8; Tue, 25 Oct 2022 11:06:52 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2a00:f41:181d:45ba:3479:f7c2:4c21:3ad3]) (using TLSv1.3 with cipher TLS_CHACHA20_POLY1305_SHA256 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA512) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id CFFB1200D7; Tue, 25 Oct 2022 20:06:49 +0200 (CEST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Robin Murphy , Luca Weiss , Iskren Chernev , Thierry Reding , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/4] arm64: dts: qcom: Add initial device tree for SM6375 Date: Tue, 25 Oct 2022 20:06:32 +0200 Message-Id: <20221025180634.28956-3-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221025180634.28956-1-konrad.dybcio@somainline.org> References: <20221025180634.28956-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747684219468753781?= X-GMAIL-MSGID: =?utf-8?q?1747684219468753781?= Add an initial device tree for the SM6375 (SD695) SoC. Signed-off-by: Konrad Dybcio --- Changes since v1: - Remove the xo_board freq from SoC DTSI arch/arm64/boot/dts/qcom/sm6375.dtsi | 807 +++++++++++++++++++++++++++ 1 file changed, 807 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6375.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi new file mode 100644 index 000000000000..c40a01f5b467 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Konrad Dybcio + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + local-timer-stop; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sm6375", "qcom,scm"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0 0x80000000 0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@80700000 { + reg = <0 0x80700000 0 0x100000>; + no-map; + }; + + reserved_xbl_uefi: memory@80880000 { + reg = <0 0x80880000 0 0x14000>; + no-map; + }; + + smem_mem: smem@80900000 { + reg = <0 0x80900000 0 0x200000>; + no-map; + }; + + fw_mem: memory@80b00000 { + reg = <0 0x80b00000 0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: memory@80c00000 { + reg = <0 0x80c00000 0 0x1e00000>; + no-map; + }; + + dfps_data_mem: memory@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + pil_wlan_mem: memory@86500000 { + reg = <0 0x86500000 0 0x200000>; + no-map; + }; + + pil_adsp_mem: memory@86700000 { + reg = <0 0x86700000 0 0x2000000>; + no-map; + }; + + pil_cdsp_mem: memory@88700000 { + reg = <0 0x88700000 0 0x1e00000>; + no-map; + }; + + pil_video_mem: memory@8a500000 { + reg = <0 0x8a500000 0 0x500000>; + no-map; + }; + + pil_ipa_fw_mem: memory@8aa00000 { + reg = <0 0x8aa00000 0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@8aa10000 { + reg = <0 0x8aa10000 0 0xa000>; + no-map; + }; + + pil_gpu_micro_code_mem: memory@8aa1a000 { + reg = <0 0x8aa1a000 0 0x2000>; + no-map; + }; + + pil_mpss_wlan_mem: memory@8b800000 { + reg = <0 0x8b800000 0 0x10000000>; + no-map; + }; + + removed_mem: memory@c0000000 { + reg = <0 0xc0000000 0 0x5100000>; + no-map; + }; + + debug_mem: memory@ffb00000 { + reg = <0 0xffb00000 0 0xc0000>; + no-map; + }; + + last_log_mem: memory@ffbc0000 { + reg = <0 0xffbc0000 0 0x80000>; + no-map; + }; + + cmdline_region: memory@ffd00000 { + reg = <0 0xffd00000 0 0x1000>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6375"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6375-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp9 { + opp-level = ; + }; + }; + }; + }; + }; + + smem: smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + ipcc: mailbox@208000 { + compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; + reg = <0 0x00208000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x00340000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6375-tlmm"; + reg = <0 0x00500000 0 0x800000>; + interrupts = ; + gpio-ranges = <&tlmm 0 0 157>; + /* TODO: Hook up MPM as wakeup-parent when it's there */ + interrupt-controller; + gpio-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,sm6375-gcc"; + reg = <0 0x01400000 0 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + #power-domain-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb_1_hsphy: phy@162b000 { + compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x0162b000 0 0x400>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + #phy-cells = <0>; + + status = "disabled"; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x01c40000 0 0x1100>, + <0 0x01e00000 0 0x2000000>, + <0 0x03e00000 0 0x100000>, + <0 0x03f00000 0 0xa0000>, + <0 0x01c0a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0 0x045f0000 0 0x7000>; + }; + + usb_1: usb@4ef8800 { + compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; + reg = <0 0x04ef8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + /* + * This property is there to allow USB2 to work, as + * USB3 is not implemented yet - (re)move it when + * proper support is in place. + */ + qcom,select-utmi-as-pipe-clk; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0 0x04e00000 0 0xcd00>; + interrupts = ; + maximum-speed = "high-speed"; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0xe0 0x0>; + + /* Yes, this impl *does* have an unfunny number of quirks.. */ + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; + reg = <0 0x0c600000 0 0x100000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, + <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, + <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ + <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + #redistributor-regions = <1>; + #interrupt-cells = <3>; + redistributor-stride = <0 0x20000>; + interrupt-controller; + }; + + timer@f420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0 0x0f420000 0 0x1000>; + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@f421000 { + reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@f423000 { + reg = <0x0f243000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@f425000 { + reg = <0x0f425000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@f427000 { + reg = <0x0f427000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@f429000 { + reg = <0x0f429000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@f42b000 { + reg = <0x0f42b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@f42d000 { + reg = <0x0f42d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + cpufreq_hw: cpufreq@fd91000 { + compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Tue Oct 25 18:06:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 10921 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1147591wru; Tue, 25 Oct 2022 11:13:13 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7k1pZ7/B90RinNUP5+FuNMeWCVXVaMCafKOPBSy2QaoZ2A/6FgitzC0kEc9OOUEO15Wmy0 X-Received: by 2002:a05:6a00:1991:b0:565:9912:cbf7 with SMTP id d17-20020a056a00199100b005659912cbf7mr40746872pfl.59.1666721593601; Tue, 25 Oct 2022 11:13:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666721593; cv=none; d=google.com; s=arc-20160816; b=NQN5+MNe+CDALvFWaLK0FbFbX6hKx6wKomdzlzlSsZV9G+KNpEM6aAZ4Y967taoVkV Qy3ftZ88ybMCXguat6zCAGi5NinFhPno5xM+eXeTPwRvZMRbGUT8nHXoP74U4vo2EPjI 4qXE+hGd3g3xmeug0hYcG/S81SuASeUpNo2YNp6g1YGTXGQcej9bbc6tj8/384goMk2y Wo2gkv9npqfs+WumRtMBnBmTHSF1znnPqtYS7bTxSiuOg0ty3mwLbI2nVYv0t+A4p/Rz fs8mvMhV0lqJwMOru6z/D602moxbPRgJFbK3UKFXUgujsRA6X2liwn9UHSpBxhnaL+31 hKWg== ARC-Message-Signature: i=1; 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Piccoli" , linux-hardening@vger.kernel.org Subject: [PATCH v2 4/4] arm64: dts: qcom: Add device tree for Sony Xperia 10 IV Date: Tue, 25 Oct 2022 20:06:33 +0200 Message-Id: <20221025180634.28956-4-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221025180634.28956-1-konrad.dybcio@somainline.org> References: <20221025180634.28956-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747684261792327467?= X-GMAIL-MSGID: =?utf-8?q?1747684261792327467?= Add support for Sony Xperia 10 IV, a.k.a PDX225. This device is a part of the SoMC SM6375 Murray platform and currently it is the only device based on that board, so no -common DTSI is created until (if?) other Murray devices appear. This commit brings support for: * USB (only USB2 for now) * Display via simplefb To create a working boot image, you need to run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm6375-sony-xperia-\ murray-pdx225.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 1 \ --os_version 12 \ --os_patch_level 2022-04 \ # or newer -o boot.img-sony-xperia-pdx225 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: First, you need to get rid of vendor_boot. However, the bootloader is utterly retarded and it will not let you neither flash nor erase it. There are a couple ways to handle this: you can either dd /dev/zero to it from Android (if you have root) or a custom recovery or from fastbootd (fastboot/adb reboot fastboot). You will not be able to boot Android images on your phone unless you lock the bootloader (fastboot oem lock) and restore the factory image with Xperia Companion Windows-and-macOS-only software. The best way so far is probably to use the second (_b) slot and flash mainline there. This will however require you to flash some partitions manually, as they are not populated from factory: (boot_b, dtbo_b, vendor_boot_b, vbmeta_b, vbmeta_system_b) - these we don't really care about as we nuke/replace them (dsp_b, imagefv_b, modem_b, oem_b, rdimage_b) - these you NEED to populate to get a successful boot on slot B, otherwise you will have limited / no functionality. To switch slots, simply run: fastboot --set-active=a //or =b The rest assumes you are on slot A. // You have to either pull vbmeta{"","_system"} from // /dev/block/bootdevice/by-name/ or build one as a part of AOSP fastboot --disable-verity --disable-verification flash vbmeta_b vbmeta.img fastboot --disable-verity --disable-verification flash vbmeta_system_b \ vbmeta_system.img fastboot flash boot_b boot.img-sony-xperia-pdx225 fastboot reboot fastboot // entering fastbootd fastboot flash vendor_boot_b emptything.img fastboot flash dtbo_b emptything.img fastboot reboot bootloader // entering bootloader fastboot fastboot --set-active=b fastboot reboot // mainline time! Where emptything.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. From there on you can flash new mainline builds by simply flashing boot.img that you create after each kernel rebuild. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Changes since v1: - Move the xo_board freq into device DTS arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 86 +++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0558d3389e5..0292d116c25b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -144,6 +144,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts new file mode 100644 index 000000000000..08a705e8ff92 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include +#include "sm6375.dtsi" +#include "pmr735a.dtsi" + +/ { + model = "Sony Xperia 10 IV"; + compatible = "sony,pdx225", "qcom,sm6375"; + chassis-type = "handset"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@85200000 { + compatible = "simple-framebuffer"; + reg = <0 0x85200000 0 0xc00000>; + + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + /* + * That's (going to be) a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet + */ + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + }; + }; + + reserved-memory { + cont_splash_mem: memory@85200000 { + reg = <0 0x85200000 0 0xc00000>; + no-map; + }; + + ramoops@ffc40000 { + compatible = "ramoops"; + reg = <0 0xffc40000 0 0xb0000>; + record-size = <0x10000>; + console-size = <0x60000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&tlmm { + gpio-reserved-ranges = <13 4>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +};