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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id t1-20020a1709060c4100b0094ee039da42si535737ejf.751.2023.05.25.03.09.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 03:09:24 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=CinFzb5f; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1B4B33858004 for ; Thu, 25 May 2023 10:09:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1B4B33858004 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685009363; bh=b9UW6AD1mqWYMXxQTbkVjGhS1hv6dmDx31ZVVTj5PJU=; h=Date:Cc:Subject:To:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=CinFzb5fkIeF17j7DKxOFjUlihZq0OYWgevLdBSsCXbuvqR6pReYk7thJEmOCRzC9 Uj26PPow9Vr7Mqev+e2X4mwax/tx7IXRZiSP/z/cAJTrDPgFxh08yg2WD7R3i0+adP JqoksI9ljgVDSRFKbeNEkAKDzxb879kcpBByZlfI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by sourceware.org (Postfix) with ESMTPS id 07B653858D32 for ; Thu, 25 May 2023 10:08:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 07B653858D32 Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-510eb3dbaaeso3815977a12.1 for ; Thu, 25 May 2023 03:08:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685009306; x=1687601306; h=content-transfer-encoding:to:subject:from:content-language:cc :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=b9UW6AD1mqWYMXxQTbkVjGhS1hv6dmDx31ZVVTj5PJU=; b=VamPikC+1tdHExvIlRk6I70VeMslyFkaNCgbxSilTS2Rz+/t15IgJ5PdbkH8qI+OX/ +7G3l/JtLNyTMXkcBSlv0rWYBcUJiSY0CX5pUvFyiEIg3KEheOQa9nb8FBzIoTqshubu 1wRu0xZ7qv1Ere02j9rpwbkBfAqinHVAaqiyI8pjVl7JOZ7EoEUVNbPfY0YjRjC6Bgr0 p7C2HeW0W2yJN6wq73Ad5KkuOxKnThEKuek3OeM2jVndZgRC2BNXpMVJoN4zeXg2LeKl WNsNJXIqzVwMVEb9vsfSuiuhvR8ogPOsnB7mT8NsB55XaUnq/xu1fWhu/o3Vm+DSIvgc qGbQ== X-Gm-Message-State: AC+VfDxwnwg3ep7Q7NTmrbF4yMng8e6gD/zOQGDJ5BZAYA0gQTiisyIo Vot/KwTDGYA3Y7ER+vZwVymM2DVqCKo= X-Received: by 2002:a17:907:97cc:b0:966:4bb3:5b8d with SMTP id js12-20020a17090797cc00b009664bb35b8dmr1112321ejc.30.1685009305698; Thu, 25 May 2023 03:08:25 -0700 (PDT) Received: from [192.168.1.23] (ip-046-005-130-086.um12.pools.vodafone-ip.de. [46.5.130.86]) by smtp.gmail.com with ESMTPSA id j21-20020a17090686d500b00965a0f30fbfsm623053ejy.186.2023.05.25.03.08.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 May 2023 03:08:25 -0700 (PDT) Message-ID: Date: Thu, 25 May 2023 12:08:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Cc: rdapp.gcc@gmail.com Content-Language: en-US Subject: [PATCH v2] RISC-V: Implement autovec abs, vneg, vnot. To: gcc-patches , Kito Cheng , palmer , "juzhe.zhong@rivai.ai" , jeffreyalaw X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Robin Dapp via Gcc-patches From: Robin Dapp Reply-To: Robin Dapp Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766860379538935008?= X-GMAIL-MSGID: =?utf-8?q?1766860379538935008?= Hi, this patch implements abs2, vneg2 and vnot2 expanders for integer vector registers and adds tests for them. v2 is rebased against Juzhe's latest refactoring. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md (2): Add vneg/vnot. (abs2): Add. * config/riscv/riscv-protos.h (emit_vlmax_masked_insn): Declare. * config/riscv/riscv-v.cc (emit_vlmax_masked_insn): New function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add unop tests. * gcc.target/riscv/rvv/autovec/unop/abs-run.c: New test. * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/unop/abs-template.h: New test. * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: New test. * gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/unop/vneg-template.h: New test. * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: New test. * gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/unop/vnot-template.h: New test. --- gcc/config/riscv/autovec.md | 45 ++++++++++++++++++- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 16 +++++++ .../riscv/rvv/autovec/unop/abs-run.c | 29 ++++++++++++ .../riscv/rvv/autovec/unop/abs-rv32gcv.c | 7 +++ .../riscv/rvv/autovec/unop/abs-rv64gcv.c | 7 +++ .../riscv/rvv/autovec/unop/abs-template.h | 26 +++++++++++ .../riscv/rvv/autovec/unop/vneg-run.c | 29 ++++++++++++ .../riscv/rvv/autovec/unop/vneg-rv32gcv.c | 6 +++ .../riscv/rvv/autovec/unop/vneg-rv64gcv.c | 6 +++ .../riscv/rvv/autovec/unop/vneg-template.h | 18 ++++++++ .../riscv/rvv/autovec/unop/vnot-run.c | 43 ++++++++++++++++++ .../riscv/rvv/autovec/unop/vnot-rv32gcv.c | 6 +++ .../riscv/rvv/autovec/unop/vnot-rv64gcv.c | 6 +++ .../riscv/rvv/autovec/unop/vnot-template.h | 22 +++++++++ gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + 16 files changed, 268 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-template.h diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 7fe4d94de39..8d26f16d5dc 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -145,7 +145,7 @@ (define_expand "3" }) ;; ------------------------------------------------------------------------- -;; ---- [INT] Binary shifts by scalar. +;; ---- [INT] Binary shifts by vector. ;; ------------------------------------------------------------------------- ;; Includes: ;; - vsll.vv/vsra.vv/vsrl.vv @@ -373,3 +373,46 @@ (define_expand "vcondu" DONE; } ) + +;; ========================================================================= +;; == Unary arithmetic +;; ========================================================================= + +;; ------------------------------------------------------------------------------- +;; ---- [INT] Unary operations +;; ------------------------------------------------------------------------------- +;; Includes: +;; - vneg.v/vnot.v +;; ------------------------------------------------------------------------------- +(define_expand "2" + [(set (match_operand:VI 0 "register_operand") + (any_int_unop:VI + (match_operand:VI 1 "register_operand")))] + "TARGET_VECTOR" +{ + insn_code icode = code_for_pred (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands); + DONE; +}) + +;; ------------------------------------------------------------------------------- +;; - ABS expansion to vmslt and vneg +;; ------------------------------------------------------------------------------- + +(define_expand "abs2" + [(set (match_operand:VI 0 "register_operand") + (match_operand:VI 1 "register_operand"))] + "TARGET_VECTOR" +{ + rtx zero = gen_const_vec_duplicate (mode, GEN_INT (0)); + machine_mode mask_mode = riscv_vector::get_mask_mode (mode).require (); + rtx mask = gen_reg_rtx (mask_mode); + riscv_vector::expand_vec_cmp (mask, LT, operands[1], zero); + + /* For masking we need two more operands than a regular unop, the mask + itself and the maskoff operand. */ + rtx ops[] = {operands[0], mask, operands[1], operands[1]}; + riscv_vector::emit_vlmax_masked_insn (code_for_pred (NEG, mode), + riscv_vector::RVV_UNOP + 2, ops); + DONE; +}) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 36419c95bbd..a24a47a42db 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -180,6 +180,7 @@ void emit_nonvlmax_insn (unsigned, int, rtx *, rtx); void emit_vlmax_merge_insn (unsigned, int, rtx *); void emit_vlmax_cmp_insn (unsigned, rtx *); void emit_vlmax_cmp_mu_insn (unsigned, rtx *); +void emit_vlmax_masked_insn (unsigned, int, rtx *); enum vlmul_type get_vlmul (machine_mode); unsigned int get_ratio (machine_mode); unsigned int get_nf (machine_mode); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index f71ad9e46a1..2fed3865ea5 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -426,6 +426,22 @@ emit_vlmax_cmp_mu_insn (unsigned icode, rtx *ops) e.emit_insn ((enum insn_code) icode, ops); } +/* This function emits a masked instruction. */ +void +emit_vlmax_masked_insn (unsigned icode, int op_num, rtx *ops) +{ + machine_mode dest_mode = GET_MODE (ops[0]); + machine_mode mask_mode = get_mask_mode (dest_mode).require (); + insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, + /*FULLY_UNMASKED_P*/ false, + /*USE_REAL_MERGE_P*/ true, + /*HAS_AVL_P*/ true, + /*VLMAX_P*/ true, dest_mode, mask_mode); + e.set_policy (TAIL_ANY); + e.set_policy (MASK_ANY); + e.emit_insn ((enum insn_code) icode, ops); +} + /* Expand series const vector. */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c new file mode 100644 index 00000000000..d6aaa785055 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "abs-template.h" + +#include + +#define SZ 255 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = i - 127; \ + } \ + vabs_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (a##TYPE[i] == abs (i - 127)); \ + +#define RUN_ALL() \ + RUN(int8_t) \ + RUN(int16_t) \ + RUN(int32_t) \ + RUN(int64_t) + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c new file mode 100644 index 00000000000..cbe0ba0b0ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "abs-template.h" + +/* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */ +/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c new file mode 100644 index 00000000000..c0c52176a42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "abs-template.h" + +/* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */ +/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h new file mode 100644 index 00000000000..a54238c8ff2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h @@ -0,0 +1,26 @@ +#include +#include + +#define TEST_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = abs (a[i]); \ + } + +#define TEST_TYPE2(TYPE) \ + __attribute__((noipa)) \ + void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = llabs (a[i]); \ + } + +#define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(int16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE2(int64_t) + +TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c new file mode 100644 index 00000000000..abeb50f21ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "vneg-template.h" + +#include + +#define SZ 255 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = i - 127; \ + } \ + vneg_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (a##TYPE[i] == -(i - 127)); + +#define RUN_ALL() \ + RUN(int8_t) \ + RUN(int16_t) \ + RUN(int32_t) \ + RUN(int64_t) + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c new file mode 100644 index 00000000000..69d9ebb0953 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "vneg-template.h" + +/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c new file mode 100644 index 00000000000..d2c2e17c13e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "vneg-template.h" + +/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h new file mode 100644 index 00000000000..f766a3b6461 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h @@ -0,0 +1,18 @@ +#include +#include + +#define TEST_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vneg_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = -a[i]; \ + } + +#define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(int16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(int64_t) + +TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c new file mode 100644 index 00000000000..2870b21a218 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c @@ -0,0 +1,43 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "vnot-template.h" + +#include + +#define SZ 255 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = i - 127; \ + } \ + vnot_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (a##TYPE[i] == (TYPE)~(i - 127)); + +#define RUN2(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = i; \ + } \ + vnot_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (a##TYPE[i] == (TYPE)~i); + +#define RUN_ALL() \ + RUN(int8_t) \ + RUN(int16_t) \ + RUN(int32_t) \ + RUN(int64_t) \ + RUN(uint8_t) \ + RUN(uint16_t) \ + RUN(uint32_t) \ + RUN(uint64_t) + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c new file mode 100644 index 00000000000..ecc4316bd4f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "vnot-template.h" + +/* { dg-final { scan-assembler-times {\tvnot\.v} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c new file mode 100644 index 00000000000..67e28af2cd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "vnot-template.h" + +/* { dg-final { scan-assembler-times {\tvnot\.v} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-template.h new file mode 100644 index 00000000000..b7a63f04485 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-template.h @@ -0,0 +1,22 @@ +#include +#include + +#define TEST_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vnot_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = ~a[i]; \ + } + +#define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 9809a421fc8..f5c022d0a30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -65,6 +65,8 @@ foreach op $AUTOVEC_TEST_OPTS { "" "$op" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/cmp/*.\[cS\]]] \ "" "$op" + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/unop/*.\[cS\]]] \ + "" "$op" } # VLS-VLMAX tests