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[8.43.85.97]) by mx.google.com with ESMTPS id b2-20020a170906d10200b0096efab3de24si22660ejz.459.2023.05.24.16.16.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 16:16:21 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="MRN/X1oY"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DE8DF3856954 for ; Wed, 24 May 2023 23:15:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DE8DF3856954 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1684970153; bh=Cj6XvPfqG43maNLcEPdLfegfEBUAaDcy5YV6y/Df84k=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=MRN/X1oY79XsQCLDrPV83kXJ+GeOboqk6zObT3YndeCbY0fHJ302dH5DhsiAKAzJU QBicNXN1WfHU8mpE9Vep2TqK6iEzZgzkY5ChMFTDDXIHHuftiKoXPDWFfRWYE6x4NU ptuUbtcdyV81otNLv9q1v3YUoxv1FcfcSIontgfo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by sourceware.org (Postfix) with ESMTPS id 68A0B3858D20 for ; Wed, 24 May 2023 23:15:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 68A0B3858D20 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1ae52ce3250so7979605ad.2 for ; Wed, 24 May 2023 16:15:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684970105; x=1687562105; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=BoEqwhtnQmIQN9SjADcHUwhitgIHCnCJw8HN2RsiU9w=; b=QuksmC5Yzh8xWDHIhOs4TX2Zds6M/1LLuflrVOzDjV/BNfoZrz0nYZdNau60ZDF0lf Bi4M7ZjaCf4Axy8iXKoRzsM0zZ2UZrfqjfmIIBMZgx86Alg2Bc2dP73OXNun9WRGtDxu hlRJ7vrIN7SSmOKM5LCcicN+lQhLC+MskmkS0BQUlxwS5bHcvvYfhPlKgG4bDTgKRVt9 Msr5t1WJodLXOgZ/gf8wQlhkRWDhmwa0UcQdHb96Qc0+2BWTwjIPP6rX2JgkKmWR3jOO 2AjnxoTwSQQuc2tJuZJS9cKpUTSJUXiUzmgsKKq/0LbjKH14/2FIQMPQQ1TL0eQ+KFqU svpw== X-Gm-Message-State: AC+VfDzNDMJ8gpyME9fY5G5Wxz0H4uATcbwrfFHToDqctUjYNK2Xlgy3 OnUJ+bqTJabRk+watb2Z+9mS0PDTbnfBMgzVXvK4E+idknA= X-Received: by 2002:a17:903:2283:b0:1a6:a405:f714 with SMTP id b3-20020a170903228300b001a6a405f714mr24169804plh.63.1684970105023; Wed, 24 May 2023 16:15:05 -0700 (PDT) MIME-Version: 1.0 Date: Thu, 25 May 2023 03:14:48 +0400 Message-ID: Subject: [RFC] RISC-V: Eliminate extension after for *w instructions To: gcc-patches@gcc.gnu.org X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, HTML_MESSAGE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jivan Hakobyan via Gcc-patches From: Jivan Hakobyan Reply-To: Jivan Hakobyan Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766819292948536457?= X-GMAIL-MSGID: =?utf-8?q?1766819292948536457?= `This patch tries to prevent generating unnecessary sign extension after *w instructions like "addiw" or "divw". The main idea of it is to add SUBREG_PROMOTED fields during expanding. I have tested on SPEC2017 there is no regression. Only gcc.dg/pr30957-1.c test failed. To solve that I did some changes in loop-iv.cc, but not sure that it is suitable. gcc/ChangeLog: * config/riscv/bitmanip.md (rotrdi3): New pattern. (rotrsi3): Likewise. (rotlsi3): Likewise. * config/riscv/riscv-protos.h (riscv_emit_binary): New function declaration * config/riscv/riscv.cc (riscv_emit_binary): Removed static * config/riscv/riscv.md (addsi3): New pattern (subsi3): Likewise. (negsi2): Likewise. (mulsi3): Likewise. (si3): New pattern for any_div. (si3): New pattern for any_shift. * loop-iv.cc (get_biv_step_1): Process src of extension when it PLUS gcc/testsuite/ChangeLog: * testsuite/gcc.target/riscv/shift-and-2.c: New test * testsuite/gcc.target/riscv/shift-shift-2.c: New test * testsuite/gcc.target/riscv/sign-extend.c: New test * testsuite/gcc.target/riscv/zbb-rol-ror-03.c: New test diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 96d31d92670b27d495dc5a9fbfc07e8767f40976..0430af7c95b1590308648dc4d5aaea78ada71760 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -304,9 +304,9 @@ [(set_attr "type" "bitmanip,load") (set_attr "mode" "HI")]) -(define_expand "rotr3" - [(set (match_operand:GPR 0 "register_operand") - (rotatert:GPR (match_operand:GPR 1 "register_operand") +(define_expand "rotrdi3" + [(set (match_operand:DI 0 "register_operand") + (rotatert:DI (match_operand:DI 1 "register_operand") (match_operand:QI 2 "arith_operand")))] "TARGET_ZBB || TARGET_XTHEADBB || TARGET_ZBKB" { @@ -322,6 +322,26 @@ "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) +(define_expand "rotrsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotatert:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "arith_operand" "rI")))] + "TARGET_ZBB || TARGET_ZBKB || TARGET_XTHEADBB" +{ + if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode)) + FAIL; + if (TARGET_64BIT && register_operand(operands[2], QImode)) + { + rtx t = gen_reg_rtx (DImode); + emit_insn (gen_rotrsi3_sext (t, operands[1], operands[2])); + t = gen_lowpart (SImode, t); + SUBREG_PROMOTED_VAR_P (t) = 1; + SUBREG_PROMOTED_SET (t, SRP_SIGNED); + emit_move_insn (operands[0], t); + DONE; + } +}) + (define_insn "*rotrdi3" [(set (match_operand:DI 0 "register_operand" "=r") (rotatert:DI (match_operand:DI 1 "register_operand" "r") @@ -330,7 +350,7 @@ "ror%i2\t%0,%1,%2" [(set_attr "type" "bitmanip")]) -(define_insn "*rotrsi3_sext" +(define_insn "rotrsi3_sext" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI"))))] @@ -338,7 +358,7 @@ "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) -(define_insn "rotlsi3" +(define_insn "*rotlsi3" [(set (match_operand:SI 0 "register_operand" "=r") (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] @@ -346,6 +366,24 @@ "rol%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) +(define_expand "rotlsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotate:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "register_operand" "r")))] + "TARGET_ZBB || TARGET_ZBKB" +{ + if (TARGET_64BIT) + { + rtx t = gen_reg_rtx (DImode); + emit_insn (gen_rotlsi3_sext (t, operands[1], operands[2])); + t = gen_lowpart (SImode, t); + SUBREG_PROMOTED_VAR_P (t) = 1; + SUBREG_PROMOTED_SET (t, SRP_SIGNED); + emit_move_insn (operands[0], t); + DONE; + } +}) + (define_insn "rotldi3" [(set (match_operand:DI 0 "register_operand" "=r") (rotate:DI (match_operand:DI 1 "register_operand" "r") diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 36419c95bbd8eebcb499ae0e02ca7aafde6c879f..de16ffd607e8e004e9b98ee9e25e4f3693818762 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -61,6 +61,7 @@ extern const char *riscv_output_return (); extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx); extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx); extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx); +extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y); #endif extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx); extern rtx riscv_legitimize_call_address (rtx); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 09fc9e5d95e611f94bc05b4851fef6f50a651c28..f14b128c9b429ee3b67c0b73e227e7a8d1f85a44 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1404,7 +1404,7 @@ riscv_emit_set (rtx target, rtx src) /* Emit an instruction of the form (set DEST (CODE X Y)). */ -static rtx +rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y) { return riscv_emit_set (dest, gen_rtx_fmt_ee (code, GET_MODE (dest), x, y)); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 124d8c95804b48a05b45b15a9cf926d27b13d029..39c0e4ec67fc7dd96b3e35f91dba26f683a6984e 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -512,7 +512,7 @@ [(set_attr "type" "fadd") (set_attr "mode" "")]) -(define_insn "addsi3" +(define_insn "*addsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") (plus:SI (match_operand:SI 1 "register_operand" " r,r") (match_operand:SI 2 "arith_operand" " r,I")))] @@ -521,6 +521,24 @@ [(set_attr "type" "arith") (set_attr "mode" "SI")]) +(define_expand "addsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (plus:SI (match_operand:SI 1 "register_operand" " r,r") + (match_operand:SI 2 "arith_operand" " r,I")))] + "" +{ + if (TARGET_64BIT) + { + rtx t = gen_reg_rtx (DImode); + emit_insn (gen_addsi3_extended (t, operands[1], operands[2])); + t = gen_lowpart (SImode, t); + SUBREG_PROMOTED_VAR_P (t) = 1; + SUBREG_PROMOTED_SET (t, SRP_SIGNED); + emit_move_insn (operands[0], t); + DONE; + } +}) + (define_insn "adddi3" [(set (match_operand:DI 0 "register_operand" "=r,r") (plus:DI (match_operand:DI 1 "register_operand" " r,r") @@ -544,7 +562,7 @@ rtx t5 = gen_reg_rtx (DImode); rtx t6 = gen_reg_rtx (DImode); - emit_insn (gen_addsi3 (operands[0], operands[1], operands[2])); + riscv_emit_binary(PLUS, operands[0], operands[1], operands[2]); if (GET_CODE (operands[1]) != CONST_INT) emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0)); else @@ -590,7 +608,7 @@ emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0)); else t3 = operands[1]; - emit_insn (gen_addsi3 (operands[0], operands[1], operands[2])); + riscv_emit_binary(PLUS, operands[0], operands[1], operands[2]); emit_insn (gen_extend_insn (t4, operands[0], DImode, SImode, 0)); riscv_expand_conditional_branch (operands[3], LTU, t4, t3); @@ -605,7 +623,7 @@ DONE; }) -(define_insn "*addsi3_extended" +(define_insn "addsi3_extended" [(set (match_operand:DI 0 "register_operand" "=r,r") (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" " r,r") @@ -652,7 +670,7 @@ [(set_attr "type" "arith") (set_attr "mode" "DI")]) -(define_insn "subsi3" +(define_insn "*subsi3" [(set (match_operand:SI 0 "register_operand" "= r") (minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ") (match_operand:SI 2 "register_operand" " r")))] @@ -661,6 +679,24 @@ [(set_attr "type" "arith") (set_attr "mode" "SI")]) +(define_expand "subsi3" + [(set (match_operand:SI 0 "register_operand" "= r") + (minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ") + (match_operand:SI 2 "register_operand" " r")))] + "" +{ + if (TARGET_64BIT) + { + rtx t = gen_reg_rtx (DImode); + emit_insn (gen_subsi3_extended (t, operands[1], operands[2])); + t = gen_lowpart (SImode, t); + SUBREG_PROMOTED_VAR_P (t) = 1; + SUBREG_PROMOTED_SET (t, SRP_SIGNED); + emit_move_insn (operands[0], t); + DONE; + } +}) + (define_expand "subv4" [(set (match_operand:GPR 0 "register_operand" "= r") (minus:GPR (match_operand:GPR 1 "reg_or_0_operand" " rJ") @@ -675,7 +711,7 @@ rtx t5 = gen_reg_rtx (DImode); rtx t6 = gen_reg_rtx (DImode); - emit_insn (gen_subsi3 (operands[0], operands[1], operands[2])); + riscv_emit_binary(MINUS, operands[0], operands[1], operands[2]); if (GET_CODE (operands[1]) != CONST_INT) emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0)); else @@ -724,7 +760,7 @@ emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0)); else t3 = operands[1]; - emit_insn (gen_subsi3 (operands[0], operands[1], operands[2])); + riscv_emit_binary(MINUS, operands[0], operands[1], operands[2]); emit_insn (gen_extend_insn (t4, operands[0], DImode, SImode, 0)); riscv_expand_conditional_branch (operands[3], LTU, t3, t4); @@ -740,7 +776,7 @@ }) -(define_insn "*subsi3_extended" +(define_insn "subsi3_extended" [(set (match_operand:DI 0 "register_operand" "= r") (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ") @@ -769,7 +805,7 @@ [(set_attr "type" "arith") (set_attr "mode" "DI")]) -(define_insn "negsi2" +(define_insn "*negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "register_operand" " r")))] "" @@ -777,7 +813,24 @@ [(set_attr "type" "arith") (set_attr "mode" "SI")]) -(define_insn "*negsi2_extended" +(define_expand "negsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (match_operand:SI 1 "register_operand" " r")))] + "" +{ + if (TARGET_64BIT) + { + rtx t = gen_reg_rtx (DImode); + emit_insn (gen_negsi2_extended (t, operands[1])); + t = gen_lowpart (SImode, t); + SUBREG_PROMOTED_VAR_P (t) = 1; + SUBREG_PROMOTED_SET (t, SRP_SIGNED); + emit_move_insn (operands[0], t); + DONE; + } +}) + +(define_insn "negsi2_extended" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (neg:SI (match_operand:SI 1 "register_operand" " r"))))] @@ -813,7 +866,7 @@ [(set_attr "type" "fmul") (set_attr "mode" "")]) -(define_insn "mulsi3" +(define_insn "*mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] @@ -822,6 +875,24 @@ [(set_attr "type" "imul") (set_attr "mode" "SI")]) +(define_expand "mulsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (mult:SI (match_operand:SI 1 "register_operand" " r") + (match_operand:SI 2 "register_operand" " r")))] + "TARGET_ZMMUL || TARGET_MUL" +{ + if (TARGET_64BIT) + { + rtx t = gen_reg_rtx (DImode); + emit_insn (gen_mulsi3_extended (t, operands[1], operands[2])); + t = gen_lowpart (SImode, t); + SUBREG_PROMOTED_VAR_P (t) = 1; + SUBREG_PROMOTED_SET (t, SRP_SIGNED); + emit_move_insn (operands[0], t); + DONE; + } +}) + (define_insn "muldi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "register_operand" " r") @@ -867,8 +938,8 @@ emit_insn (gen_smul3_highpart (hp, operands[1], operands[2])); emit_insn (gen_mul3 (operands[0], operands[1], operands[2])); - emit_insn (gen_ashr3 (lp, operands[0], - GEN_INT (BITS_PER_WORD - 1))); + riscv_emit_binary(ASHIFTRT, lp, operands[0], + GEN_INT (BITS_PER_WORD - 1)); riscv_expand_conditional_branch (operands[3], NE, hp, lp); } @@ -922,7 +993,7 @@ DONE; }) -(define_insn "*mulsi3_extended" +(define_insn "mulsi3_extended" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (mult:SI (match_operand:SI 1 "register_operand" " r") @@ -1023,7 +1094,7 @@ "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" { rtx temp = gen_reg_rtx (SImode); - emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); + riscv_emit_binary(MULT, temp, operands[1], operands[2]); emit_insn (gen_mulsi3_highpart (riscv_subword (operands[0], true), operands[1], operands[2])); emit_insn (gen_movsi (riscv_subword (operands[0], false), temp)); @@ -1054,7 +1125,7 @@ "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" { rtx temp = gen_reg_rtx (SImode); - emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); + riscv_emit_binary(MULT, temp, operands[1], operands[2]); emit_insn (gen_usmulsi3_highpart (riscv_subword (operands[0], true), operands[1], operands[2])); emit_insn (gen_movsi (riscv_subword (operands[0], false), temp)); @@ -1083,7 +1154,7 @@ ;; .................... ;; -(define_insn "si3" +(define_insn "*si3" [(set (match_operand:SI 0 "register_operand" "=r") (any_div:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] @@ -1092,6 +1163,24 @@ [(set_attr "type" "idiv") (set_attr "mode" "SI")]) +(define_expand "si3" + [(set (match_operand:SI 0 "register_operand" "=r") + (any_div:SI (match_operand:SI 1 "register_operand" " r") + (match_operand:SI 2 "register_operand" " r")))] + "TARGET_DIV" +{ + if (TARGET_64BIT) + { + rtx t = gen_reg_rtx (DImode); + emit_insn (gen_si3_extended (t, operands[1], operands[2])); + t = gen_lowpart (SImode, t); + SUBREG_PROMOTED_VAR_P (t) = 1; + SUBREG_PROMOTED_SET (t, SRP_SIGNED); + emit_move_insn (operands[0], t); + DONE; + } +}) + (define_insn "di3" [(set (match_operand:DI 0 "register_operand" "=r") (any_div:DI (match_operand:DI 1 "register_operand" " r") @@ -1117,7 +1206,7 @@ DONE; }) -(define_insn "*si3_extended" +(define_insn "si3_extended" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (any_div:SI (match_operand:SI 1 "register_operand" " r") @@ -2032,7 +2121,7 @@ ;; expand_shift_1 can do this automatically when SHIFT_COUNT_TRUNCATED is ;; defined, but use of that is discouraged. -(define_insn "si3" +(define_insn "*si3" [(set (match_operand:SI 0 "register_operand" "= r") (any_shift:SI (match_operand:SI 1 "register_operand" " r") @@ -2048,6 +2137,24 @@ [(set_attr "type" "shift") (set_attr "mode" "SI")]) +(define_expand "si3" + [(set (match_operand:SI 0 "register_operand" "= r") + (any_shift:SI (match_operand:SI 1 "register_operand" " r") + (match_operand:QI 2 "arith_operand" " rI")))] + "" +{ + if (TARGET_64BIT) + { + rtx t = gen_reg_rtx (DImode); + emit_insn (gen_si3_extend (t, operands[1], operands[2])); + t = gen_lowpart (SImode, t); + SUBREG_PROMOTED_VAR_P (t) = 1; + SUBREG_PROMOTED_SET (t, SRP_SIGNED); + emit_move_insn (operands[0], t); + DONE; + } +}) + (define_insn "di3" [(set (match_operand:DI 0 "register_operand" "= r") (any_shift:DI @@ -2082,7 +2189,7 @@ [(set_attr "type" "shift") (set_attr "mode" "")]) -(define_insn "*si3_extend" +(define_insn "si3_extend" [(set (match_operand:DI 0 "register_operand" "= r") (sign_extend:DI (any_shift:SI (match_operand:SI 1 "register_operand" " r") diff --git a/gcc/loop-iv.cc b/gcc/loop-iv.cc index 6c40db947f7f549303f8bb4d4f38aa98b6561bcc..bec1ea7e4ccf7291bb3dba91161f948e66c7bea9 100644 --- a/gcc/loop-iv.cc +++ b/gcc/loop-iv.cc @@ -637,7 +637,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg, { rtx set, rhs, op0 = NULL_RTX, op1 = NULL_RTX; rtx next, nextr; - enum rtx_code code; + enum rtx_code code, prev_code; rtx_insn *insn = DF_REF_INSN (def); df_ref next_def; enum iv_grd_result res; @@ -697,6 +697,23 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg, return false; op0 = XEXP (rhs, 0); + + if (GET_CODE (op0) == PLUS) + { + rhs = op0; + op0 = XEXP (rhs, 0); + op1 = XEXP (rhs, 1); + + if (CONSTANT_P (op0)) + std::swap (op0, op1); + + if (!simple_reg_p (op0) || !CONSTANT_P (op1)) + return false; + + prev_code = code; + code = PLUS; + } + if (!simple_reg_p (op0)) return false; @@ -769,6 +786,11 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg, else *outer_step = simplify_gen_binary (code, outer_mode, *outer_step, op1); + + if (prev_code == SIGN_EXTEND) + *extend = IV_SIGN_EXTEND; + else if (prev_code == ZERO_EXTEND) + *extend = IV_ZERO_EXTEND; break; case SIGN_EXTEND: diff --git a/gcc/testsuite/gcc.target/riscv/shift-and-2.c b/gcc/testsuite/gcc.target/riscv/shift-and-2.c index bc01e8ef99268ff154f0759620d501cadf338561..ee9925b749859950bd90de07aa63680bd3d8a5f2 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-and-2.c +++ b/gcc/testsuite/gcc.target/riscv/shift-and-2.c @@ -38,5 +38,24 @@ sub6 (long i, long j) { return i << (j & 0x3f); } + +/* Test for si3_extend. */ +int +sub7 (int i, int j) { + return (i << 10) & j; +} + +/* Test for si3_extend. */ +unsigned +sub8 (unsigned i, unsigned j) { + return (i << 10) & j; +} + +/* Test for si3_extend. */ +unsigned +sub9 (unsigned i, unsigned j) { + return (i >> 10) & j; +} + /* { dg-final { scan-assembler-not "andi" } } */ /* { dg-final { scan-assembler-not "sext.w" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c index 5f93be15ac5dc5234b75fb4004abd1fb4c37124d..bc8c4ef382897d849697e525986c4cdfa82f3699 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c @@ -38,5 +38,6 @@ sub5 (unsigned int i) } /* { dg-final { scan-assembler-times "slli" 5 } } */ /* { dg-final { scan-assembler-times "srli" 5 } } */ -/* { dg-final { scan-assembler-times "slliw" 1 } } */ -/* { dg-final { scan-assembler-times "srliw" 1 } } */ +/* { dg-final { scan-assembler-times ",40" 2 } } */ /* For sub5 test */ +/* { dg-final { scan-assembler-not "slliw" } } */ +/* { dg-final { scan-assembler-not "srliw" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend.c b/gcc/testsuite/gcc.target/riscv/sign-extend.c new file mode 100644 index 0000000000000000000000000000000000000000..6f8401948330d7772dce2fe5ae1399696896a534 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sign-extend.c @@ -0,0 +1,81 @@ +/* { dg-do compile { target { riscv64*-*-* } } } */ +/* { dg-options "-march=rv64gc -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +unsigned +foo1 (unsigned x, unsigned y, unsigned z) +{ + return x & (y - z); +} + +int +foo2 (int x, int y, int z) +{ + return x & (y - z); +} + +unsigned +foo3 (unsigned x, unsigned y, unsigned z) +{ + return x & (y * z); +} + +int +foo4 (int x, int y, int z) +{ + return x & (y * z); +} + +unsigned +foo5 (unsigned x, unsigned y) +{ + return x & (y / x); +} + +int +foo6 (int x, int y) +{ + return x & (y / x); +} + +unsigned +foo7 (unsigned x, unsigned y) +{ + return x & (y % x); +} + +int +foo8 (int x, int y) +{ + return x & (y % x); +} + +int +foo9 (int x) +{ + return x & (-x); +} + +unsigned +foo10 (unsigned x, unsigned y) +{ + return x & (y + x); +} + + +unsigned +foo11 (unsigned x) +{ + return x & (15 + x); +} + +/* { dg-final { scan-assembler-times "subw" 2 } } */ +/* { dg-final { scan-assembler-times "addw" 1 } } */ +/* { dg-final { scan-assembler-times "addiw" 1 } } */ +/* { dg-final { scan-assembler-times "mulw" 2 } } */ +/* { dg-final { scan-assembler-times "divw" 1 } } */ +/* { dg-final { scan-assembler-times "divuw" 1 } } */ +/* { dg-final { scan-assembler-times "remw" 1 } } */ +/* { dg-final { scan-assembler-times "remuw" 1 } } */ +/* { dg-final { scan-assembler-times "negw" 1 } } */ +/* { dg-final { scan-assembler-not "sext.w" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c index b44d7fe8920b3a6bdb81329626f20a508d0ca277..e7e5cbb9a1ab7b0af5b85c71fd4e2bd56aca3c00 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c @@ -16,4 +16,5 @@ unsigned int ror(unsigned int rs1, unsigned int rs2) /* { dg-final { scan-assembler-times "rolw" 1 } } */ /* { dg-final { scan-assembler-times "rorw" 1 } } */ -/* { dg-final { scan-assembler-not "and" } } */ \ No newline at end of file +/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not "sext.w" } } */