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[8.43.85.97]) by mx.google.com with ESMTPS id g25-20020aa7c599000000b00510de951919si798615edq.55.2023.05.24.00.28.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 00:28:13 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 949543857722 for ; Wed, 24 May 2023 07:28:03 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by sourceware.org (Postfix) with ESMTPS id CB5433858C78 for ; Wed, 24 May 2023 07:27:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CB5433858C78 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp87t1684913245tn5o6946 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 24 May 2023 15:27:24 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: OAh47716wYbJNmjCMDDfOazYTKVDbmwMuum/QvmF/zSQUSnsUcS8AeJ+EqkXp fkQC1Sv+fzM830bJoIWLyojnkoscQB30QousFNT9/hl1FSG8hIKovGdTZasEMY8b9fYsvyF UkWjXPb3jS3fuASfwoRbbLZKYi8PrL/U0R+ka5bEsQsD/FRL72wYEiQSV3LDdAL1auXRZrI YCXK5bKYdzo367pFo7/KrUKbadRjR0bsnAs/qRjzT0+cqrDq6chU+1RRkgeb9bChXjnQEHB tOaOOwkbnU/qmjmsXkcBN6Be5TNUKE+3DEhqpU7KQOEbghVnU6hEL5gTIAmqinzWrRgx3FI j6Po+2jECC7He63KEMKVV28djWNhnGHLKqdhKm3kWFLeesjnn0OhawrIPzVMV3c5BvZXfVg LT/O+JuNezBrHPTKHjKZa3AEa1oW5LJQ X-QQ-GoodBg: 2 X-BIZMAIL-ID: 16148038484170078136 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, pan2.li@intel.com, Juzhe-Zhong Subject: [V2 COMMITTED] RISC-V: Add RVV mask logic auto-vectorization Date: Wed, 24 May 2023 15:27:23 +0800 Message-Id: <20230524072723.1387346-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766758144543754018?= X-GMAIL-MSGID: =?utf-8?q?1766759641105983146?= From: Juzhe-Zhong This patch is adding mask logic auto-vectorization. define the pattern as "define_insn_and_split" to allow combine PASS easily combine series instructions. For example: combine vmxor.mm + vmnot.m into vmxnor.mm Build success and regression PASS And committed. --- gcc/config/riscv/autovec.md | 99 +++++++++++++++++++ gcc/config/riscv/riscv-v.cc | 7 +- .../riscv/rvv/autovec/cmp/vcond-4.c | 53 ++++++++++ .../riscv/rvv/autovec/cmp/vcond_run-4.c | 35 +++++++ 4 files changed, 191 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 4eeeab624a4..7fe4d94de39 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -163,6 +163,105 @@ DONE; }) +;; ------------------------------------------------------------------------- +;; ---- [BOOL] Binary logical operations +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmand.mm +;; - vmxor.mm +;; - vmor.mm +;; ------------------------------------------------------------------------- + +(define_insn_and_split "3" + [(set (match_operand:VB 0 "register_operand" "=vr") + (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr") + (match_operand:VB 2 "register_operand" " vr")))] + "TARGET_VECTOR" + "#" + "&& can_create_pseudo_p ()" + [(const_int 0)] + { + insn_code icode = code_for_pred (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); + DONE; + } + [(set_attr "type" "vmalu") + (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------- +;; ---- [BOOL] Inverse +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmnot.m +;; ------------------------------------------------------------------------- + +(define_insn_and_split "one_cmpl2" + [(set (match_operand:VB 0 "register_operand" "=vr") + (not:VB (match_operand:VB 1 "register_operand" " vr")))] + "TARGET_VECTOR" + "#" + "&& can_create_pseudo_p ()" + [(const_int 0)] + { + insn_code icode = code_for_pred_not (mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands); + DONE; + } + [(set_attr "type" "vmalu") + (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------- +;; ---- [BOOL] Binary logical operations (inverted second input) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmandnot.mm +;; - vmornot.mm +;; ------------------------------------------------------------------------- + +(define_insn_and_split "*not" + [(set (match_operand:VB 0 "register_operand" "=vr") + (bitmanip_bitwise:VB + (not:VB (match_operand:VB 2 "register_operand" " vr")) + (match_operand:VB 1 "register_operand" " vr")))] + "TARGET_VECTOR" + "#" + "&& can_create_pseudo_p ()" + [(const_int 0)] + { + insn_code icode = code_for_pred_not (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); + DONE; + } + [(set_attr "type" "vmalu") + (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------- +;; ---- [BOOL] Binary logical operations (inverted result) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmnand.mm +;; - vmnor.mm +;; - vmxnor.mm +;; ------------------------------------------------------------------------- + +(define_insn_and_split "*n" + [(set (match_operand:VB 0 "register_operand" "=vr") + (not:VB + (any_bitwise:VB + (match_operand:VB 1 "register_operand" " vr") + (match_operand:VB 2 "register_operand" " vr"))))] + "TARGET_VECTOR" + "#" + "&& can_create_pseudo_p ()" + [(const_int 0)] + { + insn_code icode = code_for_pred_n (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); + DONE; + } + [(set_attr "type" "vmalu") + (set_attr "mode" "")]) + ;; ========================================================================= ;; == Comparisons and selects ;; ========================================================================= diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 10de5a19937..f71ad9e46a1 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1550,9 +1550,10 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1, emit_move_insn (target, eq0); return true; } - insn_code icode = code_for_pred_not (mask_mode); - rtx ops[] = {target, eq0}; - emit_vlmax_insn (icode, RVV_UNOP, ops); + + /* We use one_cmpl2 to make Combine PASS to combine mask instructions + into: vmand.mm/vmnor.mm/vmnand.mm/vmnor.mm/vmxnor.mm. */ + emit_insn (gen_rtx_SET (target, gen_rtx_NOT (mask_mode, eq0))); return false; } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c new file mode 100644 index 00000000000..435a59c97f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ + +#include + +#define b_and(A, B) ((A) & (B)) +#define b_orr(A, B) ((A) | (B)) +#define b_xor(A, B) ((A) ^ (B)) +#define b_nand(A, B) (!((A) & (B))) +#define b_nor(A, B) (!((A) | (B))) +#define b_xnor(A, B) (!(A) ^ (B)) +#define b_andnot(A, B) ((A) & !(B)) +#define b_ornot(A, B) ((A) | !(B)) + +#define LOOP(TYPE, BINOP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE##_##BINOP (TYPE *restrict dest, TYPE *restrict src, \ + TYPE *restrict a, TYPE *restrict b, TYPE *restrict c, \ + TYPE *restrict d, TYPE fallback, int count) \ + { \ + for (int i = 0; i < count; ++i) \ + { \ + TYPE srcv = src[i]; \ + dest[i] = (BINOP (__builtin_isunordered (a[i], b[i]), \ + __builtin_isunordered (c[i], d[i])) \ + ? srcv \ + : fallback); \ + } \ + } + +#define TEST_BINOP(T, BINOP) \ + T (float, BINOP) \ + T (double, BINOP) + +#define TEST_ALL(T) \ + TEST_BINOP (T, b_and) \ + TEST_BINOP (T, b_orr) \ + TEST_BINOP (T, b_xor) \ + TEST_BINOP (T, b_nand) \ + TEST_BINOP (T, b_nor) \ + TEST_BINOP (T, b_xnor) \ + TEST_BINOP (T, b_andnot) \ + TEST_BINOP (T, b_ornot) + +TEST_ALL (LOOP) + +/* { dg-final { scan-assembler-times {\tvmand\.mm} 2 } } */ +/* { dg-final { scan-assembler-times {\tvmor\.mm} 2 } } */ +/* { dg-final { scan-assembler-times {\tvmxor\.mm} 2 } } */ +/* { dg-final { scan-assembler-times {\tvmnot\.m} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmxnor\.mm} 2 } } */ +/* { dg-final { scan-assembler-times {\tvmandn\.mm} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmorn\.mm} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c new file mode 100644 index 00000000000..6c45c274c33 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ + +#include "vcond-4.c" + +#define N 401 + +#define RUN_LOOP(TYPE, BINOP) \ + { \ + TYPE dest[N], src[N], a[N], b[N], c[N], d[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + src[i] = i * i; \ + a[i] = i % 5 < 3 ? __builtin_nan("") : i; \ + b[i] = i % 7 < 4 ? __builtin_nan("") : i; \ + c[i] = i % 9 < 5 ? __builtin_nan("") : i; \ + d[i] = i % 11 < 6 ? __builtin_nan("") : i; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##BINOP (dest, src, a, b, c, d, 100, N); \ + for (int i = 0; i < N; ++i) \ + { \ + int res = BINOP (__builtin_isunordered (a[i], b[i]), \ + __builtin_isunordered (c[i], d[i])); \ + if (dest[i] != (res ? src[i] : 100.0)) \ + __builtin_abort (); \ + } \ + } + +int __attribute__ ((optimize (1))) +main (void) +{ + TEST_ALL (RUN_LOOP) + return 0; +}