From patchwork Fri May 19 03:48:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 96176 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp963864vqo; Thu, 18 May 2023 20:49:33 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5cTA6MDgsfoagzIQ0+QHpN4eOaPbc6HBSdzJXsLJ7/JpJceRrk7AYJHYVOOaHNJhevpkn1 X-Received: by 2002:a17:906:2dce:b0:94f:2852:1d2b with SMTP id h14-20020a1709062dce00b0094f28521d2bmr308515eji.72.1684468172891; Thu, 18 May 2023 20:49:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684468172; cv=none; d=google.com; s=arc-20160816; b=fWUWQCVYO6S+097rwypjbx4G2qSUsGuY87oYxthEscMT0OjBvzlXb0aki5bdp5F4QL qskdI8jnUfJjpiHu6hvGsw3L28XziCxfVGL9/VMo23jd5pahVGHnwpE8uCxw8Wda98cN 7Ax1imXLs0qWZmCw5v6nXfgM3bmo/ue5KO8FQzalhDPU+9bEUsu45LSy04FVjRaFFnpI 8uoFre3O6WdKFZRvZ+d12J+zYV1QnE7IE0C2N2ZJVlYStMpusRJvU8UEeeeizu2CWFpX DA2ZHDQYLBNOg9KlMNULQWMd9A08bUZK3IgQpprNvhjNHFASF6Eem85FIDPHy2dtC/o0 OXIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dmarc-filter:delivered-to; bh=3gDXDyLH/NK7DWsLEsFszZzb/5cQxkBxugEM1ijYPBE=; b=IYI5tYQfVbUFm+L5yTirdjkw4o6zfs46y+wAdU0xROOnmBKajn7HvX2HIECPzZocwr ZeWGv3xJ887SajDYnl6p2Ox3r52x80HWuSyxYDjQsEINWSjb9E4kyq4PDPUoTkNd5for sQg/lY0IX5ZZ9jW9EvotfcesXiZdSbc9wyF3jrbo+p8KFV9Kj3o6L9erIQKgafCysC/t uOEbFGTZYP6SZH/ot1YQTjRY06C0HBdjG3kJrkG1WMCkVqCy0vgxc4AfGfvm74Pdmg6r V4OFwKbcvtBB16/Mjn20fLSobeSpzINZIcuIaL8exMRP9BUxt/2ALL81/dRX/6Fe8XB5 oa5Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id vi18-20020a170907d41200b0096f6be51ec8si295143ejc.161.2023.05.18.20.49.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 20:49:32 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 93E373839DD7 for ; Fri, 19 May 2023 03:49:17 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTPS id A14E53846415 for ; Fri, 19 May 2023 03:49:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A14E53846415 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-05 (Coremail) with SMTP id zQCowAAHuxGt8WZk_iYmAQ--.24085S3; Fri, 19 May 2023 11:49:02 +0800 (CST) From: Liao Shihua To: binutils@sourceware.org Cc: kito.cheng@sifive.com, jiawei@iscas.ac.cn, palmer@dabbelt.com, guoren@kernel.org, wuwei2016@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Liao Shihua Subject: [RFC PATCH 1/4] RISC-V : Remove checking when -march=rv64XX and -mabi=ilp32X Date: Fri, 19 May 2023 11:48:32 +0800 Message-Id: <20230519034835.664-2-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230519034835.664-1-shihua@iscas.ac.cn> References: <20230519034835.664-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowAAHuxGt8WZk_iYmAQ--.24085S3 X-Coremail-Antispam: 1UD129KBjvJXoW7uFWfWr4DXryxKF1DKFW3ZFb_yoW8ur13pr 4DCF1qkFWkCFn7Jry7Kr4xG3WxJ34S93909r1fJryxtr4xJrWjqwn8K3W7Xay7XF4rCw1r uwsIkrWfZrW8ta7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9l14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVWxJr0_GcWl e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1l42xK82IYc2Ij64vIr41l4I 8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AK xVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcV AFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8I cIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r 4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUOtC7UUUUU X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCQQQEWRmyJedfwAAsz X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766292898796575868?= X-GMAIL-MSGID: =?utf-8?q?1766292898796575868?= This patch remove check in riscv_set_abi_by_arch() when -march=rv64XX and -mabi=ilp32X gas/ChangeLog: * config/tc-riscv.c (riscv_set_abi_by_arch): Remove check. * testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d: Removed. * testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l: Removed. --- gas/config/tc-riscv.c | 2 +- gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d | 3 --- gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l | 2 -- 3 files changed, 1 insertion(+), 6 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d delete mode 100644 gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 0cc2484b049..99903deccec 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -379,7 +379,7 @@ riscv_set_abi_by_arch (void) gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT); if (abi_xlen > xlen) as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); - else if (abi_xlen < xlen) + else if (abi_xlen < xlen && (abi_xlen != 32 && xlen != 64)) as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi) diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d b/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d deleted file mode 100644 index e3155f48956..00000000000 --- a/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d +++ /dev/null @@ -1,3 +0,0 @@ -#as: -march-attr -mabi=ilp32 -#source: mabi-attr-rv64iq.s -#error_output: mabi-fail-rv64iq-ilp32.l diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l b/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l deleted file mode 100644 index 8d45a07fd36..00000000000 --- a/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l +++ /dev/null @@ -1,2 +0,0 @@ -.*Assembler messages: -.*Error: 32-bit ABI not yet supported on 64-bit ISA From patchwork Fri May 19 03:48:33 2023 Content-Type: text/plain; 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[8.43.85.97]) by mx.google.com with ESMTPS id a10-20020a170906244a00b00965b0d9d40esi1607170ejb.631.2023.05.18.20.51.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 20:51:24 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 732B8382CD6B for ; Fri, 19 May 2023 03:49:50 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTPS id 61B1D3857034 for ; Fri, 19 May 2023 03:49:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 61B1D3857034 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-05 (Coremail) with SMTP id zQCowAAHuxGt8WZk_iYmAQ--.24085S4; Fri, 19 May 2023 11:49:03 +0800 (CST) From: Liao Shihua To: binutils@sourceware.org Cc: kito.cheng@sifive.com, jiawei@iscas.ac.cn, palmer@dabbelt.com, guoren@kernel.org, wuwei2016@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Liao Shihua Subject: [RFC PATCH 2/4] RISC-V : Add support for rv64 arch using ilp32 abi Date: Fri, 19 May 2023 11:48:33 +0800 Message-Id: <20230519034835.664-3-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230519034835.664-1-shihua@iscas.ac.cn> References: <20230519034835.664-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowAAHuxGt8WZk_iYmAQ--.24085S4 X-Coremail-Antispam: 1UD129KBjvJXoW3tFW3Aw48Jr4DCr4UWFy8Zrb_yoWDWw4xpF WFkryDuFn5ZFyxW3y7Aw47Ww1rJ3y09w4aywsY93yUAFnrXrWfXr4kJw1F9FyDGF4kC3yj vFyUGr1UZwsYyrDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9l14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVWxJr0_GcWl e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1l42xK82IYc2Ij64vIr41l4I 8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AK xVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcV AFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8I cIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r 4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUe1v3UUUUU X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCg0QEWRmxtSiigABs- X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DRUGS_ERECTILE, DRUGS_ERECTILE_OBFU, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766293015810693795?= X-GMAIL-MSGID: =?utf-8?q?1766293015810693795?= This patch add a new bfd_mach bfd_mach_riscv64x32 and a new e_flags X32. bfd_mach_riscv64x32 has the same bits in a word/address and ARCH_SIZE with rv32, but use rv64's PRSTATUS. X32 use the 6th bit of e_flags layout. In addition, this patch replace xlen with abi_xlen in riscv_target_format(). Thanks for Jim Wilson's help. bfd/ChangeLog: * archures.c: Add bfd_mach_riscv64x32. * bfd-in2.h (bfd_mach_riscv64x32): Likewise. * cpu-riscv.c:Likewise. * elfnn-riscv.c (ABI_X32_P): Add a flag when used x32. (perform_relocation): Check relocation. (riscv_merge_arch_attr_info): Remove elf check when use x32. (_bfd_riscv_elf_merge_private_bfd_data):Allow linking X32 flag. (_bfd_riscv_relax_call):Check relocation. (_bfd_riscv_relax_section):Check relocation. (riscv_elf_object_p): Set bfd_default_set_arch_mach is bfd_mach_riscv64x32 when use x32. binutils/ChangeLog: * readelf.c (get_machine_flags): gas/ChangeLog: * config/tc-riscv.c (riscv_set_x32):Add X32 flag when use X32. (riscv_set_abi_by_arch): (riscv_target_format):init target_format by abi_xlen (md_begin):set mach. (s_riscv_attribute):Likewise include/ChangeLog: * elf/riscv.h (EF_RISCV_X32):Add e_flags X32. --- bfd/archures.c | 1 + bfd/bfd-in2.h | 1 + bfd/cpu-riscv.c | 2 ++ bfd/elfnn-riscv.c | 33 ++++++++++++++++++++++----------- binutils/readelf.c | 3 +++ gas/config/tc-riscv.c | 21 +++++++++++++++++---- include/elf/riscv.h | 3 +++ 7 files changed, 49 insertions(+), 15 deletions(-) diff --git a/bfd/archures.c b/bfd/archures.c index 6fe8701b412..fb3554d253a 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -447,6 +447,7 @@ DESCRIPTION . bfd_arch_riscv, .#define bfd_mach_riscv32 132 .#define bfd_mach_riscv64 164 +.#define bfd_mach_riscv64x32 16432 . bfd_arch_rl78, .#define bfd_mach_rl78 0x75 . bfd_arch_rx, {* Renesas RX. *} diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 7be18db20a8..c0615d3aeed 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1700,6 +1700,7 @@ enum bfd_architecture bfd_arch_riscv, #define bfd_mach_riscv32 132 #define bfd_mach_riscv64 164 +#define bfd_mach_riscv64x32 16432 bfd_arch_rl78, #define bfd_mach_rl78 0x75 bfd_arch_rx, /* Renesas RX. */ diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c index a478797da69..38b7eb4a7b5 100644 --- a/bfd/cpu-riscv.c +++ b/bfd/cpu-riscv.c @@ -86,6 +86,7 @@ riscv_scan (const struct bfd_arch_info *info, const char *string) enum { I_riscv64, + I_riscv64x32, I_riscv32 }; @@ -96,6 +97,7 @@ enum static const bfd_arch_info_type arch_info_struct[] = { N (64, bfd_mach_riscv64, "riscv:rv64", false, NN (I_riscv64)), + N (32, bfd_mach_riscv64x32, "riscv:rv64", false, NN (I_riscv64x32)), N (32, bfd_mach_riscv32, "riscv:rv32", false, NULL) }; diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c index a23b91ac15c..f1f72e9bd35 100644 --- a/bfd/elfnn-riscv.c +++ b/bfd/elfnn-riscv.c @@ -122,6 +122,11 @@ #define RISCV_ELF_WORD_BYTES (1 << RISCV_ELF_LOG_WORD_BYTES) +#define ABI_X32_P(abfd) \ + ((elf_elfheader (abfd)->e_flags & EF_RISCV_X32) != 0) + +static bool ABI_X32 = false; + /* The name of the dynamic interpreter. This is put in the .interp section. */ @@ -1721,7 +1726,7 @@ perform_relocation (const reloc_howto_type *howto, case R_RISCV_GOT_HI20: case R_RISCV_TLS_GOT_HI20: case R_RISCV_TLS_GD_HI20: - if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value))) + if ((ARCH_SIZE > 32 || ABI_X32_P(input_bfd)) && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value))) return bfd_reloc_overflow; value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); break; @@ -1744,7 +1749,7 @@ perform_relocation (const reloc_howto_type *howto, case R_RISCV_CALL: case R_RISCV_CALL_PLT: - if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value))) + if ((ARCH_SIZE > 32 || ABI_X32_P(input_bfd))&& !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value))) return bfd_reloc_overflow; value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)) | (ENCODE_ITYPE_IMM (value) << 32); @@ -3685,7 +3690,7 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch) return NULL; /* Checking XLEN. */ - if (xlen_out != xlen_in) + if (xlen_out != xlen_in && !ABI_X32_P(ibfd)) { _bfd_error_handler (_("error: %pB: ISA string of input (%s) doesn't match " @@ -3705,7 +3710,7 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch) if (!riscv_merge_multi_letter_ext (&in, &out)) return NULL; - if (xlen_in != xlen_out) + if (xlen_in != xlen_out && !ABI_X32_P(ibfd)) { _bfd_error_handler (_("error: %pB: XLEN of input (%u) doesn't match " @@ -3713,7 +3718,7 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch) return NULL; } - if (xlen_in != ARCH_SIZE) + if (xlen_in != ARCH_SIZE && !ABI_X32_P(ibfd)) { _bfd_error_handler (_("error: %pB: unsupported XLEN (%u), you might be " @@ -3721,7 +3726,7 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch) return NULL; } - merged_arch_str = riscv_arch_str (ARCH_SIZE, &merged_subsets); + merged_arch_str = riscv_arch_str (xlen_in, &merged_subsets); /* Release the subset lists. */ riscv_release_subset_list (&in_subsets); @@ -3992,6 +3997,9 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) /* Allow linking TSO and non-TSO, and keep the TSO flag. */ elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_TSO; + /* Allow linking X32 and non-X32, and keep the X32 flag. */ + elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_X32; + return true; fail: @@ -4431,7 +4439,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec, rvc = rvc && VALID_CJTYPE_IMM (foff); /* C.J exists on RV32 and RV64, but C.JAL is RV32-only. */ - rvc = rvc && (rd == 0 || (rd == X_RA && ARCH_SIZE == 32)); + rvc = rvc && (rd == 0 || (rd == X_RA && ARCH_SIZE == 32 && !ABI_X32_P(abfd))); if (rvc) { @@ -5140,7 +5148,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec, return ret; } -#if ARCH_SIZE == 32 +#if ARCH_SIZE == 32 && !ABI_X32 # define PRSTATUS_SIZE 204 # define PRSTATUS_OFFSET_PR_CURSIG 12 # define PRSTATUS_OFFSET_PR_PID 24 @@ -5310,9 +5318,12 @@ riscv_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) static bool riscv_elf_object_p (bfd *abfd) { - /* There are only two mach types in RISCV currently. */ - if (strcmp (abfd->xvec->name, "elf32-littleriscv") == 0 - || strcmp (abfd->xvec->name, "elf32-bigriscv") == 0) + ABI_X32 = ABI_X32_P(abfd); + /* There are only three mach types in RISCV currently. */ + if (ABI_X32) + bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv64x32); + else if (strcmp (abfd->xvec->name, "elf32-littleriscv") == 0 + || strcmp (abfd->xvec->name, "elf32-bigriscv") == 0) bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv32); else bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv64); diff --git a/binutils/readelf.c b/binutils/readelf.c index b872876a8b6..5e3378457c7 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -4119,6 +4119,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) if (e_flags & EF_RISCV_TSO) strcat (buf, ", TSO"); + if (e_flags & EF_RISCV_X32) + strcat (buf, ", X32"); + switch (e_flags & EF_RISCV_FLOAT_ABI) { case EF_RISCV_FLOAT_ABI_SOFT: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 99903deccec..7c47530801e 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -278,6 +278,14 @@ riscv_set_tso (void) elf_flags |= EF_RISCV_TSO; } +/* Turn on the x32 flag for elf_flags once we have enabled x32 model. */ + +static void +riscv_set_x32 (void) +{ + elf_flags |= EF_RISCV_X32; +} + /* The linked list hanging off of .subsets_list records all enabled extensions, which are parsed from the architecture string. The architecture string can be set by the -march option, the elf architecture attributes, and the @@ -405,6 +413,9 @@ riscv_set_abi_by_arch (void) if (rve_abi) elf_flags |= EF_RISCV_RVE; + + if (abi_xlen == 32 && xlen == 64) + riscv_set_x32 (); } /* Handle of the OPCODE hash table. */ @@ -706,9 +717,9 @@ const char * riscv_target_format (void) { if (target_big_endian) - return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv"; + return abi_xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv"; else - return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; + return abi_xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; } /* Return the length of instruction INSN. */ @@ -1505,7 +1516,8 @@ init_opcode_hash (const struct riscv_opcode *opcodes, void md_begin (void) { - unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; + unsigned long mach = xlen == 64 ? + (abi_xlen == 32 ? bfd_mach_riscv64x32 : bfd_mach_riscv64) : bfd_mach_riscv32; if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) as_warn (_("could not set architecture and machine")); @@ -4912,7 +4924,8 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) if (old_xlen != xlen) { /* We must re-init bfd again if xlen is changed. */ - unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; + unsigned long mach = xlen == 64 ? (abi_xlen == 32 ? + bfd_mach_riscv64x32 : bfd_mach_riscv64) : bfd_mach_riscv32; bfd_find_target (riscv_target_format (), stdoutput); if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) diff --git a/include/elf/riscv.h b/include/elf/riscv.h index aabc71cf979..932ce42bf97 100644 --- a/include/elf/riscv.h +++ b/include/elf/riscv.h @@ -124,6 +124,9 @@ END_RELOC_NUMBERS (R_RISCV_max) /* File uses the TSO model. */ #define EF_RISCV_TSO 0x0010 +/* File uses the X32 model. */ +#define EF_RISCV_X32 0x0020 + /* Additional section types. */ #define SHT_RISCV_ATTRIBUTES 0x70000003 /* Section holds attributes. */ From patchwork Fri May 19 03:48:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 96177 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp963979vqo; Thu, 18 May 2023 20:50:00 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7/U5XkiEeP6HIcYreASk5mSqIjoDDGJAIR9atT05hz6qyP3G2PMEhGtEVioKcAfUBf+MBp X-Received: by 2002:aa7:c716:0:b0:50b:c58a:a7ae with SMTP id i22-20020aa7c716000000b0050bc58aa7aemr419689edq.4.1684468199894; Thu, 18 May 2023 20:49:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684468199; cv=none; d=google.com; s=arc-20160816; b=XwNAT1JwF0vPqv+QmdzufUaTWroy3cFWtxvtHz9og4sa6siCZoA0WQyx6krhRaQQRh kjs8B9zgtaiOGgLJt2aoKgjFl+54MOysgmRFln3vEnotCTjLSB4dJbSl0XV/H1C3Dh0t Ix3NxzdGkzsp/OWiS/pGiG8Og3i0vsLMqN8CZpXirvEdW78UQJOTgxpkfjfkODGONyIA 9pp1+PyExsvTXu53ix/BQj2aw1C9YLo34pSDiljKnSvj+wyOQ5bJpI06gZ7N0jJ8/khl nxn0z91001v/gQa6kFi+TZAnrgjYN0EREVKiIkp/DD/V0WZFX+g/m2hN7NrqcAS0/V4I B3Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dmarc-filter:delivered-to; bh=5qYEje3zvSQT0V7J4fmp94KPHcPdbyaqaaCxwASyFac=; b=GOtLP3ZT/IMcoBQQeQ5t/K5/khR0L4mcL9WHdVI1QwJNDzVSCrD8plG9jnCtzyJrqA 7y4Pb5nngsSZGTvODOd3BYy5lRHSitnrJk8JOybAZoq1dKaqMpg3VJJKc5qiS3j5olTQ Ry9pOboPjxeu1bs/Bled+jkUb9TjBGe0RK2mFTZofNHs/wMOBzIxS3fwVl/CB4KJ1p6p l42IWMNXBrZJzBpK7a75F0jll2vN2wZ7Mx6iqzlIZtQcxpVlxTdc4ruQ5AYVVNNNs6fV LZofpS2ayh5lciw09xU1np9W1E5kNFgDU3NsijKpM7vmZc9gPA7kfdgo69eZ9/BV2o8U 4Www== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from sourceware.org (server2.sourceware.org. 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- if (info->mach == bfd_mach_riscv64 + if ((info->mach == bfd_mach_riscv64 || info->mach == bfd_mach_riscv64x32) && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0) maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1); print (info->stream, dis_style_immediate, "%d", @@ -463,7 +463,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) || (l & MASK_JALR) == MATCH_JALR) maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); - if (info->mach == bfd_mach_riscv64 + if ((info->mach == bfd_mach_riscv64 || info->mach == bfd_mach_riscv64x32) && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0) maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1); print (info->stream, dis_style_immediate, "%d", @@ -724,7 +724,7 @@ riscv_disassemble_insn (bfd_vma memaddr, if (op != NULL) { /* If XLEN is not known, get its value from the ELF class. */ - if (info->mach == bfd_mach_riscv64) + if (info->mach == bfd_mach_riscv64 || info->mach == bfd_mach_riscv64x32) xlen = 64; else if (info->mach == bfd_mach_riscv32) xlen = 32; From patchwork Fri May 19 03:48:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 96180 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp964541vqo; Thu, 18 May 2023 20:51:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ50/25Pmd+hPwPODXaDc8iCWtUcC2EJvUb6bwfRdHTFMRPZ3xWwa+symUMEKoy/lFB9j1FR X-Received: by 2002:a17:907:3e92:b0:969:e88a:6071 with SMTP id hs18-20020a1709073e9200b00969e88a6071mr318039ejc.61.1684468309345; Thu, 18 May 2023 20:51:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684468309; cv=none; d=google.com; s=arc-20160816; b=Fwt7rRSZCO4f4S0JvTCGY0TJA7TIsSq5/fyT2+9sbyXbLpN+S87dMx1g8ISq7M7g84 k8z0lyoWi8UbhoHToiYsr1X2XtsEThB0uE0qt5xanSs5dfBb+/GVHFvSDYje1GdfsCPP Y2nM8VtMuADCPURuBtgSmRCId/4JZ+ggfENbfghqGxyUFmsqISAC5tcJNzRtN+Ka8HFX c88d2a7tN0siLZd4xTTqOBeeZqBnm5czp/omeQC+A2+z5a0hF+cW1f7JRGDe/R+a0cAs DU7K9iLAuAGc5qudVC1lCuVh+CmNj1+Qya9meYNu5sbOmxCmHlXgDzPClcutMOOlR4mF OEwA== ARC-Message-Signature: i=1; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id e19-20020a170906c01300b0096a27ebb5f5si2389224ejz.793.2023.05.18.20.51.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 20:51:49 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 181773888C59 for ; Fri, 19 May 2023 03:49:59 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTPS id 0BEB8384643E for ; Fri, 19 May 2023 03:49:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0BEB8384643E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-05 (Coremail) with SMTP id zQCowAAHuxGt8WZk_iYmAQ--.24085S6; Fri, 19 May 2023 11:49:04 +0800 (CST) From: Liao Shihua To: binutils@sourceware.org Cc: kito.cheng@sifive.com, jiawei@iscas.ac.cn, palmer@dabbelt.com, guoren@kernel.org, wuwei2016@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Liao Shihua Subject: [RFC PATCH 4/4] gdb/riscv : Add rv64 ilp32 support in gdb Date: Fri, 19 May 2023 11:48:35 +0800 Message-Id: <20230519034835.664-5-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230519034835.664-1-shihua@iscas.ac.cn> References: <20230519034835.664-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowAAHuxGt8WZk_iYmAQ--.24085S6 X-Coremail-Antispam: 1UD129KBjvJXoWxXFy8Kry8Zw1fKF47tFy7ZFb_yoW5uryUpr 4rC3ZxArs8WF1xCay3Ars7uF4rXr1vg3yYvr1DAw45JFn8W3yfuFs5u3WIkrsrJa4F9F13 ua1DKryUZw4UAw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr1j 6rxdM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6x IIjxv20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_ Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI4 8JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xv wVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjx v20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k2 6cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxV AFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUArcfUUUUU= X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCg0QEWRmxtSiigAAs+ X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766293041577302510?= X-GMAIL-MSGID: =?utf-8?q?1766293041577302510?= This patch supports rv64 ilp32 in gdb. I know should send it to gdb maillist, but due to its close correlation with the previous patch, it is temporarily placed here. It add a new gdb features abi_xlen. ChangeLog: * gdb/arch/riscv.h (struct riscv_gdbarch_features):Add abi_xlen . * gdb/riscv-tdep.c (riscv_abi_xlen):Likewise (riscv_features_from_bfd):Likewise (riscv_gdbarch_init):change long_bit by abi_xlen. --- gdb/arch/riscv.h | 10 +++++++++- gdb/riscv-tdep.c | 20 ++++++++++++++++---- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h index 54610ed6c16..a41faba1168 100644 --- a/gdb/arch/riscv.h +++ b/gdb/arch/riscv.h @@ -41,6 +41,12 @@ struct riscv_gdbarch_features uninitialised. */ int xlen = 0; + /* The size of the pointer_size in bytes. This is either 4 (ILP32), 8 + (LP64). No other value is valid. Initialise to the + invalid 0 value so we can spot if one of these is used + uninitialised. */ + int abi_xlen = 0; + /* The size of the f-registers in bytes. This is either 4 (RV32), 8 (RV64), or 16 (RV128). This can also hold the value 0 to indicate that there are no f-registers. No other value is valid. */ @@ -68,6 +74,7 @@ struct riscv_gdbarch_features bool operator== (const struct riscv_gdbarch_features &rhs) const { return (xlen == rhs.xlen && flen == rhs.flen + && abi_xlen == rhs.abi_xlen && embedded == rhs.embedded && vlen == rhs.vlen && has_fflags_reg == rhs.has_fflags_reg && has_frm_reg == rhs.has_frm_reg @@ -88,8 +95,9 @@ struct riscv_gdbarch_features | (has_frm_reg ? 1 : 0) << 12 | (has_fcsr_reg ? 1 : 0) << 13 | (xlen & 0x1f) << 5 + | (abi_xlen & 0x1f) << 14 | (flen & 0x1f) << 0 - | (vlen & 0xfff) << 14); + | (vlen & 0xfff) << 19); return val; } }; diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 500279e1ae9..d4531896cc1 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -774,7 +774,7 @@ int riscv_abi_xlen (struct gdbarch *gdbarch) { riscv_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - return tdep->abi_features.xlen; + return tdep->abi_features.abi_xlen; } /* See riscv-tdep.h. */ @@ -3835,9 +3835,15 @@ riscv_features_from_bfd (const bfd *abfd) int e_flags = elf_elfheader (abfd)->e_flags; if (eclass == ELFCLASS32) - features.xlen = 4; + { + features.xlen == 4; + features.abi_xlen = 4; + } else if (eclass == ELFCLASS64) - features.xlen = 8; + { + features.xlen == 8; + features.abi_xlen = 8; + } else internal_error (_("unknown ELF header class %d"), eclass); @@ -3846,6 +3852,12 @@ riscv_features_from_bfd (const bfd *abfd) else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE) features.flen = 4; + if (e_flags & EF_RISCV_X32) + { + features.xlen == 8; + features.abi_xlen = 4; + } + if (e_flags & EF_RISCV_RVE) { if (features.xlen == 8) @@ -4175,7 +4187,7 @@ riscv_gdbarch_init (struct gdbarch_info info, /* Target data types. */ set_gdbarch_short_bit (gdbarch, 16); set_gdbarch_int_bit (gdbarch, 32); - set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); + set_gdbarch_long_bit (gdbarch, riscv_abi_xlen (gdbarch) * 8); set_gdbarch_long_long_bit (gdbarch, 64); set_gdbarch_float_bit (gdbarch, 32); set_gdbarch_double_bit (gdbarch, 64);