From patchwork Fri May 19 03:48:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 96175 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp963825vqo; Thu, 18 May 2023 20:49:26 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ78amMbI1ziff3ibSKrjN8oMHjPL8fX2n5sEu+DvfxGNu/0S9AG8LsFmr4URG+lsVzbKkjE X-Received: by 2002:a05:6402:12c3:b0:510:f6e9:6d92 with SMTP id k3-20020a05640212c300b00510f6e96d92mr368299edx.0.1684468165941; Thu, 18 May 2023 20:49:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684468165; cv=none; d=google.com; s=arc-20160816; b=XBNNBdKho93nbpNcHW1BNw+s9xj6CsfoxMFDcA8xL/1PEjAtA1H1pLC4mQRnPo2kSA j99e5CKeBGebq1BUSF5XalArEKDx9qT8hFCwEdv8z910JgZr3eoe9aEZzFgaXmUpp/JT jvbkUOzlx0UXgKRWnD/myigatxXlS4lgfFCr7o8m6DiXqi2SFU7ikR7TL9XZzrSzdf0W diSK6tGQJ6uqBRJKDdeeye67fq42HV0keurpwU9FVevHajuIlGbtf2S5fdjMuu9gNsAs rrH1ikSuWNcZH5qJtKTBzpPNPipuxF+bZfOMA7dz6XRJr+glfp7MiCHGcoBA8bm92xtB fOpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dmarc-filter :delivered-to; bh=usDan2qJ5d4B6eCKVqN0ZXVy5y3+M+AlDpUvFbPbqMM=; b=LeQ8nXzlIklxwwka8CozQrrtMvSUTWq4p9IUdqL5qj9s8Dj5fr5gHTUf/VW6RYEqEL KXswq/pXZQD3uBS9NgPLcd8tF4qwqvXeIwXVFBdMobuHjky665V/1HwNWt9MRfcNqV0K yS6jwZS2oOpuq1Dz7gjHPGYkGm909kn3Q05/cMr8hdhiZyP/rAgtVOv8sfQcwzBNU2MC yr6sNxv/tjsSxAD2zRruhvwDISbOQSgCjsrRRaT03+TvWtBfRROBiwoDuu6t9ViBQrOa lHOx/S5FTiXq50I2x4DrmEcdWKISfYAaEyi+WZfXTqtFFafp1SVzcRRG9tsvSNQThxgY dhZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id v19-20020aa7d653000000b00510d71d00f9si2256783edr.543.2023.05.18.20.49.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 20:49:25 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4FF9F384646F for ; Fri, 19 May 2023 03:49:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTPS id 2DE443858D39 for ; Fri, 19 May 2023 03:48:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2DE443858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-05 (Coremail) with SMTP id zQCowAB36xGR8WZkRRwmAQ--.24136S2; Fri, 19 May 2023 11:48:35 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, jiawei@iscas.ac.cn, palmer@dabbelt.com, guoren@kernel.org, wuwei2016@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Liao Shihua Subject: [RFC V2] RISC-V : Support rv64 ilp32 Date: Fri, 19 May 2023 11:48:23 +0800 Message-Id: <20230519034823.653-1-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 MIME-Version: 1.0 X-CM-TRANSID: zQCowAB36xGR8WZkRRwmAQ--.24136S2 X-Coremail-Antispam: 1UD129KBjvJXoW3XFy3CF18CFWDAr1xXFyUtrb_yoW7Ar4DpF WUGw4ayryrAF4fWws3trWxGw45Gwnagw4Yk3ykZr47Aa15trykZFn8Ww43XrWDWF4Yqr17 Z3Z2kayay3yUC37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUyG14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr 1j6rxdM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj 6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr 0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAK I48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7 xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xII jxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw2 0EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x02 67AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbUUUUUU== X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiAxEQEWRmwMazVQAAsx X-Spam-Status: No, score=-15.3 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_LOW, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766292891598698402?= X-GMAIL-MSGID: =?utf-8?q?1766292891598698402?= This patch support ilp32 on rv64. It remove option check when -march=rv64* -mabi=ilp32. And replace XLEN_SPEC in LINK_SPEC by ABI_LEN_SPEC. In addition, it some machine descriptions. The series kernel support in this link. https://lore.kernel.org/linux-riscv/20230518131013.3366406-1-guoren@kernel.org/ gcc/ChangeLog: * config.gcc: * config/riscv/elf.h (LINK_SPEC): * config/riscv/linux.h (LINK_SPEC): * config/riscv/riscv.cc (riscv_option_override): * config/riscv/riscv.h (TARGET_ILP32): (POINTER_SIZE): (Pmode): (ABI_LEN_SPEC): * config/riscv/riscv.md: --- gcc/config.gcc | 3 +++ gcc/config/riscv/elf.h | 2 +- gcc/config/riscv/linux.h | 2 +- gcc/config/riscv/riscv.cc | 4 ---- gcc/config/riscv/riscv.h | 12 ++++++++++-- gcc/config/riscv/riscv.md | 8 ++++++-- 6 files changed, 21 insertions(+), 10 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 6fd1594480a..db8e8f20791 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4658,6 +4658,9 @@ case "${target}" in ilp32,rv32* | ilp32e,rv32e* \ | ilp32f,rv32*f* | ilp32f,rv32g* \ | ilp32d,rv32*d* | ilp32d,rv32g* \ + | ilp32f,rv64*f* | ilp32f,rv64g* \ + | ilp32d,rv64*d* | ilp32d,rv64g* \ + | ilp32,rv64* \ | lp64,rv64* \ | lp64f,rv64*f* | lp64f,rv64g* \ | lp64d,rv64*d* | lp64d,rv64g*) diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h index a725c00b637..bea531ebe89 100644 --- a/gcc/config/riscv/elf.h +++ b/gcc/config/riscv/elf.h @@ -18,7 +18,7 @@ along with GCC; see the file COPYING3. If not see . */ #define LINK_SPEC "\ --melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \ +-melf" ABI_LEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \ %{mno-relax:--no-relax} \ %{mbig-endian:-EB} \ %{mlittle-endian:-EL} \ diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h index b9557a75dc7..4f33c88ef6e 100644 --- a/gcc/config/riscv/linux.h +++ b/gcc/config/riscv/linux.h @@ -58,7 +58,7 @@ along with GCC; see the file COPYING3. If not see "%{mabi=ilp32:_ilp32}" #define LINK_SPEC "\ --melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \ +-melf" ABI_LEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \ %{mno-relax:--no-relax} \ %{mbig-endian:-EB} \ %{mlittle-endian:-EL} \ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5f44f6dc5c9..09ab940447d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6291,10 +6291,6 @@ riscv_option_override (void) && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) error ("z*inx requires ABI ilp32, ilp32e or lp64"); - /* We do not yet support ILP32 on RV64. */ - if (BITS_PER_WORD != POINTER_SIZE) - error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); - /* Validate -mpreferred-stack-boundary= value. */ riscv_stack_boundary = ABI_STACK_BOUNDARY; if (riscv_preferred_stack_boundary_arg) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 66fb07d6652..54fd328b5b0 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -77,6 +77,10 @@ extern const char *riscv_multi_lib_check (int argc, const char **argv); #define TARGET_64BIT (__riscv_xlen == 64) #endif /* IN_LIBGCC2 */ +#ifndef TARGET_ILP32 +#define TARGET_ILP32 (riscv_abi <= ABI_ILP32D) +#endif /*TARGET_ILP32*/ + #ifdef HAVE_AS_MISA_SPEC #define ASM_MISA_SPEC "%{misa-spec=*}" #else @@ -172,7 +176,7 @@ ASM_MISA_SPEC #define SHORT_TYPE_SIZE 16 #define INT_TYPE_SIZE 32 #define LONG_LONG_TYPE_SIZE 64 -#define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32) +#define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) #define LONG_TYPE_SIZE POINTER_SIZE #define FLOAT_TYPE_SIZE 32 @@ -789,7 +793,7 @@ typedef struct { After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ -#define Pmode word_mode +#define Pmode (TARGET_ILP32 ? SImode : DImode) /* Give call MEMs SImode since it is the "most permissive" mode for both 32-bit and 64-bit targets. */ @@ -1039,6 +1043,10 @@ extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int); "%{march=rv32*:32}" \ "%{march=rv64*:64}" \ +#define ABI_LEN_SPEC \ + "%{mabi=ilp32*:32}" \ + "%{mabi=lp64*:64}" \ + #define ABI_SPEC \ "%{mabi=ilp32:ilp32}" \ "%{mabi=ilp32e:ilp32e}" \ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index bc384d9aedf..260b0907cf5 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2737,6 +2737,10 @@ "reload_completed" [(const_int 0)] { + if (GET_MODE (operands[0]) != Pmode) + operands[0] = convert_to_mode (Pmode, operands[0], 0); + if (GET_MODE (operands[1]) != Pmode) + operands[1] = convert_to_mode (Pmode, operands[1], 0); riscv_set_return_address (operands[0], operands[1]); DONE; }) @@ -2946,8 +2950,8 @@ (define_insn "stack_tie" [(set (mem:BLK (scratch)) - (unspec:BLK [(match_operand:X 0 "register_operand" "r") - (match_operand:X 1 "register_operand" "r")] + (unspec:BLK [(match_operand:P 0 "register_operand" "r") + (match_operand:P 1 "register_operand" "r")] UNSPEC_TIE))] "" ""