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Thu, 18 May 2023 19:56:02 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 1/5] iommu/amd: Switch amd_iommu_update_ga() to use modify_irte_ga() Date: Thu, 18 May 2023 20:55:25 -0400 Message-ID: <20230519005529.28171-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> References: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT070:EE_|DM4PR12MB5311:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f2087f5-3c37-4886-61a8-08db5803d242 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Njc34ouT1EZ5O7QwsHbFBmH8GvYigtVjc9tKlQLHTlAEi/MzhddBamE9X+G3dtmDn7xt66/Zi/S9HZCN8vIgGhx5vXJZZ6AlME8TkRPT6KFZDGhmpNUAmZmXSGlnCJol4JlInozMIeTTM/C3O91gZIUz0k1r+7pCALaerW0TKKWi9jEWzOCJKBtbwRXnd5m5aC+ToUlYpa7AZcbc5DrzsPFOsI2AZsGYmvCYDcskItxYkDhhxH+yjM52QI9r+NQ6OxbS8FgiJ5WMUmRFrbKezWFlaZ8368n++lHx98aIBNxYEvCWXecV2jQ95SCw+AWkrmiBSvsHFG1OrX3SmYyT82J7lIhKuQkqbBFHfzlZOf9IZ8ZtaK9astn7+g9J744wACZcuXsQQah0wldM3BnzbXkT/nb1RKDL7UmjmfmudXKcfGVBXAGPmD/67l7OMce/ar98PTTDg5Xj6wreZ6ceHvv+7XgC1USdsxNG9tWdzqCWCpNWMY2sciwRxeY61dNs9bO4q91RHjs8NkN+w1FpFF+jbJtFwgSN8Pm8snGy0zV+GWgAeh1C842ezjYELc3Gbjp5Whi76+JucQvROng+PT+mKwUyx3NZh5fCdBDafARQF+Kz62trIFyF6oIg3gMp5J4Khh/UHebhL+zrih8Y3CVFG+RfghBnlqFTkQeDZpjsWMMqFOtT33gA9AYU5s2ohd1hR80YwNJu9mtgR85hL0yjx657p9CIXHAzsW0TbyTOj/Gak+TFc2G1lx6OjC9g6dyT7sjE7Owu6uOCPI40JA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(376002)(136003)(39860400002)(451199021)(40470700004)(36840700001)(46966006)(86362001)(36756003)(40480700001)(82310400005)(8676002)(8936002)(26005)(1076003)(2616005)(44832011)(426003)(336012)(2906002)(5660300002)(16526019)(186003)(316002)(54906003)(70586007)(70206006)(110136005)(41300700001)(478600001)(7696005)(6666004)(81166007)(356005)(82740400003)(4326008)(36860700001)(47076005)(83380400001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2023 00:56:03.7206 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f2087f5-3c37-4886-61a8-08db5803d242 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT070.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5311 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766282837031103273?= X-GMAIL-MSGID: =?utf-8?q?1766282837031103273?= From: Joao Martins The modify_irte_ga() uses cmpxchg_double() to update the IRTE in one shot, which is necessary when adding IRTE cache disabling support since the driver no longer need to flush the IRT for hardware to take effect. Please note that there is a functional change where the IsRun and Destination bits of IRTE are now cached in the struct amd_ir_data.entry. Signed-off-by: Joao Martins Signed-off-by: Suravee Suthikulpanit Reviewed-by: Jerry Snitselaar --- drivers/iommu/amd/iommu.c | 38 ++++++++++---------------------------- 1 file changed, 10 insertions(+), 28 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index ebb155bfef15..4a3a7346ab21 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3700,44 +3700,26 @@ int amd_iommu_create_irq_domain(struct amd_iommu *iommu) int amd_iommu_update_ga(int cpu, bool is_run, void *data) { - unsigned long flags; - struct amd_iommu *iommu; - struct irq_remap_table *table; struct amd_ir_data *ir_data = (struct amd_ir_data *)data; - int devid = ir_data->irq_2_irte.devid; struct irte_ga *entry = (struct irte_ga *) ir_data->entry; - struct irte_ga *ref = (struct irte_ga *) ir_data->ref; if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || - !ref || !entry || !entry->lo.fields_vapic.guest_mode) + !entry || !entry->lo.fields_vapic.guest_mode) return 0; - iommu = ir_data->iommu; - if (!iommu) - return -ENODEV; - - table = get_irq_table(iommu, devid); - if (!table) + if (!ir_data->iommu) return -ENODEV; - raw_spin_lock_irqsave(&table->lock, flags); - - if (ref->lo.fields_vapic.guest_mode) { - if (cpu >= 0) { - ref->lo.fields_vapic.destination = - APICID_TO_IRTE_DEST_LO(cpu); - ref->hi.fields.destination = - APICID_TO_IRTE_DEST_HI(cpu); - } - ref->lo.fields_vapic.is_run = is_run; - barrier(); + if (cpu >= 0) { + entry->lo.fields_vapic.destination = + APICID_TO_IRTE_DEST_LO(cpu); + entry->hi.fields.destination = + APICID_TO_IRTE_DEST_HI(cpu); } + entry->lo.fields_vapic.is_run = is_run; - raw_spin_unlock_irqrestore(&table->lock, flags); - - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); - return 0; + return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, + ir_data->irq_2_irte.index, entry, ir_data); } EXPORT_SYMBOL(amd_iommu_update_ga); #endif From patchwork Fri May 19 00:55:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suravee Suthikulpanit X-Patchwork-Id: 96152 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp910495vqo; Thu, 18 May 2023 18:20:29 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7vTq3s2jwS1RorHU+W372CXTjBars5ixtsjiltpwnyAqHOlN+Dc3dPvkPxSkwxm//Ph0dE X-Received: by 2002:a05:6a00:138f:b0:645:fc7b:63d6 with SMTP id t15-20020a056a00138f00b00645fc7b63d6mr1142145pfg.6.1684459229372; Thu, 18 May 2023 18:20:29 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1684459229; cv=pass; d=google.com; s=arc-20160816; b=0EA40gvbLcpGeI2c4MX/Nh74jbqWRijJETKRTiivvI+M9Uujasyy1JpcwO0kWKEkPc 6ajfUDsbeFBCzzl+fP9WF3srhgRvQ6dFHrx9RN0O+PbDGoMdqpYMYqunWnxskAdx6gJ3 LRtFXtht3ohQxWscAmK3RpowPbOJU4YLRrHCqKcb1Y/5xx+SdKWx7xjDHmzEj//MQU9y SgForvH8ZlJWPqr2TS4q58PBOUFlL6E81KDn8LeEzYMdxKq+V2ccnBxv5ECKPmQYpst3 +VSUworUTBw/K0vOHliU9VRaOCA6pBd+fZL6rVWHn9s1W/PTzelsOpWN45Xcy1PCyA8k Czyw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xq73+IZrlw9jHoBVbO87NURLM734QIXFzrUPsqkI7Ro=; b=QzjzTtHBV6R74fxCNUK6WVVnHxjEyS2WsfvA2IDnwB4s52HAiB7fyCqTWDejdl0CU2 rGBEA6gJAer0d1DX+Z6nj8GI67LnbfGM3iqUZXtK6BEPAfCNADrKkv5Ul+S3VQRrGTO1 mNUSS2nCCm2Zc6gnlD8gZdQB/3aMW9bjUDn0CdTzJRuxlV5YISBzm4NuP2u2GMoaONoy ldXJTn6Swj3RWVRlkBaxu60LYsIw9AjpEM2igqzLghR6P+LV9l+dOdAdcpwCqeBxr5yH 7hob4dp3KMKGXh2LYS14ts4Pd72ytyjsx2MupTKjjBTYyrOiJp/YHpTFCfHyqkSyd5BR 8DYw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=utBvS0dS; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 18 May 2023 19:56:03 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 2/5] iommu/amd: Remove the unused struct amd_ir_data.ref Date: Thu, 18 May 2023 20:55:26 -0400 Message-ID: <20230519005529.28171-3-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> References: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT070:EE_|DM4PR12MB5794:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e30c014-20f3-41cb-6325-08db5803d36c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: d8Zah0cCRG7b0vbynZB8D9hsEpjuIGaua05YqpxEnZSkMf7f3y3imDqlo5dCIPAJdr3fbVDOsNvpNr8ioTxFb3JNG2bIVt/ToCRPJgLy7rYMD2JX3GNRrNAVXUL137fANn2vjJ0dDQiJW+EjZg6tmnqfmcXNgfeR6ubRl0lVve3+NcZwh/j8mw8n8VXQI2yZjP/soQS7lukK2tL+Vydum4ncMIpGQnJmHegqxjZmcVjNRHrJMaqYC6uDvn4rBaSJrmQUAwRinDIjXY0a8mELBFafmsITDGEyYxAw3D9F7hjH0xKWXYqcPaVZaMdKQiF7Nlw9Atsktti+bXBVbSlysbGeeetIGkDlkZJ0m113TJHdbsAxZ8RsrGdZCaIhtbjEUfdxRpX62kgAk+Ad6oosCHcR/bQqp6GPfKuAWTbskYeTNWC1M6DKvdmswiqZ7r48xAKvoOIwVw6MEPK3tDVmL21UabgikJSKXxx5D+zW6lzmu58Qty108eh4DnkEU9h4dEBl1xeqd7u1uUD4zaTqYaCau9Cm/3Dtq9MsxqWs7xcgWH/JiMlALG22of/Vf5WZjIL1rsw75Znrv8YVnga1z8Qmfkwe/euxvCZ4PVjSVmadaaeOOV4RfJH/PBDkQFmpvCULsJTR5705y+bw5GPJ/dokn2IH9BkRyN2xxh8tSIPIBc8gOYwmRTBWwDE8Bt3xxQmSltOsavYNtYfJSuxx77IFnRVptyw/SGmjnH8EU89eDCdqTt7DPYXxu07ZHhe/CrWHgzpvrNOml3oLQnv4Sw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(346002)(376002)(136003)(396003)(451199021)(40470700004)(46966006)(36840700001)(36860700001)(81166007)(356005)(82740400003)(36756003)(40460700003)(8676002)(8936002)(5660300002)(44832011)(41300700001)(82310400005)(4326008)(316002)(86362001)(40480700001)(70206006)(70586007)(426003)(336012)(83380400001)(47076005)(110136005)(16526019)(1076003)(26005)(186003)(2906002)(7696005)(478600001)(6666004)(2616005)(54906003)(36900700001);DIR:OUT;SFP:1101; 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Suggested-by: Vasant Hegde Signed-off-by: Suravee Suthikulpanit Reviewed-by: Jerry Snitselaar --- drivers/iommu/amd/amd_iommu_types.h | 1 - drivers/iommu/amd/iommu.c | 17 +++++++---------- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 3d684190b4d5..a0ff1e852efc 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -993,7 +993,6 @@ struct amd_ir_data { struct irq_2_irte irq_2_irte; struct msi_msg msi_entry; void *entry; /* Pointer to union irte or struct irte_ga */ - void *ref; /* Pointer to the actual irte */ /** * Store information for activate/de-activate diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4a3a7346ab21..0c4a2796bb0a 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2999,7 +2999,7 @@ static int alloc_irq_index(struct amd_iommu *iommu, u16 devid, int count, } static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index, - struct irte_ga *irte, struct amd_ir_data *data) + struct irte_ga *irte) { bool ret; struct irq_remap_table *table; @@ -3026,9 +3026,6 @@ static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index, */ WARN_ON(!ret); - if (data) - data->ref = entry; - raw_spin_unlock_irqrestore(&table->lock, flags); iommu_flush_irt(iommu, devid); @@ -3117,7 +3114,7 @@ static void irte_ga_activate(struct amd_iommu *iommu, void *entry, u16 devid, u1 struct irte_ga *irte = (struct irte_ga *) entry; irte->lo.fields_remap.valid = 1; - modify_irte_ga(iommu, devid, index, irte, NULL); + modify_irte_ga(iommu, devid, index, irte); } static void irte_deactivate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index) @@ -3133,7 +3130,7 @@ static void irte_ga_deactivate(struct amd_iommu *iommu, void *entry, u16 devid, struct irte_ga *irte = (struct irte_ga *) entry; irte->lo.fields_remap.valid = 0; - modify_irte_ga(iommu, devid, index, irte, NULL); + modify_irte_ga(iommu, devid, index, irte); } static void irte_set_affinity(struct amd_iommu *iommu, void *entry, u16 devid, u16 index, @@ -3157,7 +3154,7 @@ static void irte_ga_set_affinity(struct amd_iommu *iommu, void *entry, u16 devid APICID_TO_IRTE_DEST_LO(dest_apicid); irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid); - modify_irte_ga(iommu, devid, index, irte, NULL); + modify_irte_ga(iommu, devid, index, irte); } } @@ -3508,7 +3505,7 @@ int amd_iommu_activate_guest_mode(void *data) entry->lo.fields_vapic.ga_tag = ir_data->ga_tag; return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, - ir_data->irq_2_irte.index, entry, ir_data); + ir_data->irq_2_irte.index, entry); } EXPORT_SYMBOL(amd_iommu_activate_guest_mode); @@ -3538,7 +3535,7 @@ int amd_iommu_deactivate_guest_mode(void *data) APICID_TO_IRTE_DEST_HI(cfg->dest_apicid); return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, - ir_data->irq_2_irte.index, entry, ir_data); + ir_data->irq_2_irte.index, entry); } EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode); @@ -3719,7 +3716,7 @@ int amd_iommu_update_ga(int cpu, bool is_run, void *data) entry->lo.fields_vapic.is_run = is_run; return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, - ir_data->irq_2_irte.index, entry, ir_data); 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Thu, 18 May 2023 19:56:04 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 3/5] iommu/amd: Introduce Disable IRTE Caching Support Date: Thu, 18 May 2023 20:55:27 -0400 Message-ID: <20230519005529.28171-4-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> References: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT063:EE_|IA0PR12MB7652:EE_ X-MS-Office365-Filtering-Correlation-Id: fbf0ae2e-cd22-450f-3f0b-08db5803d438 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OMhw6UF6czx4XAmZbsVsAeV3x5WG+cPS+s73wGpqEXmfFWKSoo1DO+d5IjF2P7BBBHwBX1Crvh64NAN+/XFeguumm89uRgPJl7QJqMJWn/NRVQZGo1U3QgKOvVqp/RQLO+hjBE5bVFugPD9Dcr06PZW8DsuAHEaq7i0ibSnlv76rPy4pAqOPL5P6Iue+8rs0kIUN1Kys7t+35hXoNCi0Vwnf1R/wNMcXaU/JL7TYlAXkT7naB6WRmWXdxUNjeE8bHzr8vljdsk7dQbILfjUurktxFKpv5F7BgU/7uy+DNN6omsZ1yYoWXi67+eFk+AI2DiTFHVMf8T0XmIPXFck2rTuLyNQ40qbduwCF50tNyrLtqk1bm1bHrWVOFrHDx/BLhp1SlVjkhF3OdYiW5Sh0B9Ubsi6KWlLVvPV/L/TQ11usJgI6RkBOVA/tLA9waOedapa6nFmEy+6BRcqWnAGZU4yoZh788YJ3SlkBh0YDEc/CWpE0dZFSphZBtuH7qyzyRoSWEFSTEnOKBgh7rlbSapuav6aKdsjUVnXf0Dkt1swvnP+kumptJJhb+qUeHOJ7rEYnHIfYrOCYFkjrkWB0SufuX5mYJIIn273bL7XcvrK0Zn89moxEvdhYj3CgZ858xa2us2NtAP2ejxpXo7XUvMtjJao5+XyRzh8W9qdwp9CmrNLiVjHy2dykm6bPKGAwNl0lLD/Y98gCsT6Tpin9X5SAbtbSScpHs5+ArGhXGWwE9jsnfuJ19CNCgUdmRlJrM9UL+TX4wR+cstvqQR3+sXytwth8zI6pzMk6RCtulTpC6QuwMPGrde/Wxk3Ja4Fg X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(396003)(376002)(136003)(346002)(451199021)(36840700001)(46966006)(40470700004)(36756003)(7696005)(110136005)(4326008)(478600001)(70206006)(316002)(70586007)(54906003)(40480700001)(6666004)(82310400005)(44832011)(8936002)(8676002)(2906002)(5660300002)(336012)(81166007)(356005)(41300700001)(82740400003)(36860700001)(16526019)(426003)(26005)(186003)(2616005)(47076005)(83380400001)(1076003)(86362001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2023 00:56:07.0096 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fbf0ae2e-cd22-450f-3f0b-08db5803d438 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7652 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766282769658401423?= X-GMAIL-MSGID: =?utf-8?q?1766282769658401423?= An Interrupt Remapping Table (IRT) stores interrupt remapping configuration for each device. In a normal operation, the AMD IOMMU caches the table to optimize subsequent data accesses. This requires the IOMMU driver to invalidate IRT whenever it updates the table. The invalidation process includes issuing an INVALIDATE_INTERRUPT_TABLE command following by a COMPLETION_WAIT command. However, there are cases in which the IRT is updated at a high rate. For example, for IOMMU AVIC, the IRTE[IsRun] bit is updated on every vcpu scheduling (i.e. amd_iommu_update_ga()). On system with large amount of vcpus and VFIO PCI pass-through devices, the invalidation process could potentially become a performance bottleneck. Introducing a new kernel boot option: amd_iommu=irtcachedis which disables IRTE caching by setting the IRTCachedis bit in each IOMMU Control register, and bypass the IRT invalidation process. Co-developed-by: Alejandro Jimenez [Awaiting sign-off by Alejandro] Signed-off-by: Suravee Suthikulpanit Signed-off-by: Alejandro Jimenez --- .../admin-guide/kernel-parameters.txt | 1 + drivers/iommu/amd/amd_iommu_types.h | 4 +++ drivers/iommu/amd/init.c | 36 +++++++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 6221a1d057dd..f29dee600faf 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -323,6 +323,7 @@ option with care. pgtbl_v1 - Use v1 page table for DMA-API (Default). pgtbl_v2 - Use v2 page table for DMA-API. + irtcachedis - Disable Interrupt Remapping Table (IRT) caching. amd_iommu_dump= [HW,X86-64] Enable AMD IOMMU driver option to dump the ACPI table diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index a0ff1e852efc..486a052e37ca 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -172,6 +172,7 @@ #define CONTROL_GAINT_EN 29 #define CONTROL_XT_EN 50 #define CONTROL_INTCAPXT_EN 51 +#define CONTROL_IRTCACHEDIS 59 #define CONTROL_SNPAVIC_EN 61 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) @@ -708,6 +709,9 @@ struct amd_iommu { /* if one, we need to send a completion wait command */ bool need_sync; + /* true if disable irte caching */ + bool irtcachedis_enabled; + /* Handle for IOMMU core code */ struct iommu_device iommu; diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index fd487c33b28a..fc0392d706db 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -160,6 +160,7 @@ static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; static bool amd_iommu_detected; static bool amd_iommu_disabled __initdata; static bool amd_iommu_force_enable __initdata; +static bool amd_iommu_irtcachedis; static int amd_iommu_target_ivhd_type; /* Global EFR and EFR2 registers */ @@ -477,6 +478,9 @@ static void iommu_disable(struct amd_iommu *iommu) /* Disable IOMMU hardware itself */ iommu_feature_disable(iommu, CONTROL_IOMMU_EN); + + /* Clear IRTE cache disabling bit */ + iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); } /* @@ -2700,6 +2704,33 @@ static void iommu_enable_ga(struct amd_iommu *iommu) #endif } +static void iommu_disable_irtcachedis(struct amd_iommu *iommu) +{ + iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); +} + +static void iommu_enable_irtcachedis(struct amd_iommu *iommu) +{ + u64 ctrl; + + if (!amd_iommu_irtcachedis) + return; + + /* + * Note: + * The support for IRTCacheDis feature is dertermined by + * checking if the bit is writable. + */ + iommu_feature_enable(iommu, CONTROL_IRTCACHEDIS); + ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); + ctrl &= (1ULL << CONTROL_IRTCACHEDIS); + if (ctrl) + iommu->irtcachedis_enabled = true; + pr_info("iommu%d (%#06x) : IRT cache is %s\n", + iommu->index, iommu->devid, + iommu->irtcachedis_enabled ? "disabled" : "enabled"); +} + static void early_enable_iommu(struct amd_iommu *iommu) { iommu_disable(iommu); @@ -2710,6 +2741,7 @@ static void early_enable_iommu(struct amd_iommu *iommu) iommu_set_exclusion_range(iommu); iommu_enable_ga(iommu); iommu_enable_xt(iommu); + iommu_enable_irtcachedis(iommu); iommu_enable(iommu); iommu_flush_all_caches(iommu); } @@ -2760,10 +2792,12 @@ static void early_enable_iommus(void) for_each_iommu(iommu) { iommu_disable_command_buffer(iommu); iommu_disable_event_buffer(iommu); + iommu_disable_irtcachedis(iommu); iommu_enable_command_buffer(iommu); iommu_enable_event_buffer(iommu); iommu_enable_ga(iommu); iommu_enable_xt(iommu); + iommu_enable_irtcachedis(iommu); iommu_set_device_table(iommu); iommu_flush_all_caches(iommu); } @@ -3411,6 +3445,8 @@ static int __init parse_amd_iommu_options(char *str) amd_iommu_pgtable = AMD_IOMMU_V1; } else if (strncmp(str, "pgtbl_v2", 8) == 0) { amd_iommu_pgtable = AMD_IOMMU_V2; + } else if (strncmp(str, "irtcachedis", 11) == 0) { + amd_iommu_irtcachedis = true; } else { pr_notice("Unknown option - '%s'\n", str); } From patchwork Fri May 19 00:55:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suravee Suthikulpanit X-Patchwork-Id: 96147 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp901861vqo; Thu, 18 May 2023 18:00:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7Uk7hpTJY0noBPGLAX4yu/kuRshAtWbru/O15bWm8QAnuCLBMxJ+4YJ9gm7psX+e7x4VIU X-Received: by 2002:a17:90a:3186:b0:252:7372:460c with SMTP id j6-20020a17090a318600b002527372460cmr1054954pjb.4.1684458038509; Thu, 18 May 2023 18:00:38 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1684458038; cv=pass; d=google.com; s=arc-20160816; b=AyL0qon2Hn7qy2LWkyvYWAa0lmzFvRF2kq2rPt83rUbzCObIyAmGytil1QDqsee0VU GbrXb+VAGJS9rL5JhJ5pPRDb4Vt2x9Rv/OphGI2Sg/fUTGH/NZgXnwQEPdxHWVNteVG2 bJbzUy4yOnSP0ZPC4QfdgY3vFJxOwxVDW2xzrOvFet3HbBjNC+kSFM3vVE0G9LGCp0rB xvgBvF8S13JshHzOmkVB/ra7viVENcTmd/91+eakvgPzw6vro6nydRQQ+EhIL4LuYvlX +BIImQUzbTT7Mq4UsoCkHa83irQ4DVow2dB6ok1YdDjuyfLXvax7GGeBYYoufHDuyqV3 26pA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DhGNxVBuLU8j6nRMP9u1WkiBJLLOolekgHbORFlHSAg=; b=cp5tJ9HYrn8WWvLpTb8LP/r/2/pwP5X9hd5ccc+srEoLomAh+LuCYYnDFN4r+0pZAh nmnprLXnngBW24vRovLoIJ9FPGMR58ieq1vS2Miotc9EsO8SBjgYjy6nLvg7BO5+jQ6n v70rjRtBcP3dPfax192IO/RMfvEu0gClRYXT7KawxTlB+qo4tNT7qyH6bzdEvSVQu1HP LgTbnNxyEBRTgeTwxROPzvC0xU991fczKJYg0jzsGslTlruOgB9AzIBtZ8tjzVFdEJ5q JSenxpR+kf/l9eE9cK0GVHC3V3iltbe2d4+h2pF3CYZoifbg6qJXTZ2QfHWc6EdZAL23 Wk+g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=YY4+bT5T; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 18 May 2023 19:56:06 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 4/5] iommu/amd: Do not Invalidate IRT when disable IRTE caching Date: Thu, 18 May 2023 20:55:28 -0400 Message-ID: <20230519005529.28171-5-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> References: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT063:EE_|DM6PR12MB4123:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e2a9398-dd71-4a64-32f1-08db5803d4f2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rLVYZFY0uUUPN++PsohbtXEg5Hb6N5zfhou3gn5ntPxQYv3aIo9i88yZQIlIJzBvNmPJdMXZc9r5JSEGjGHmzZKoOtwvtaVwRvuNkUp2KImEq04cd6eeYsNgxjzX5BcG6lxB+KIPjXJ03Top90AwncOexZ1OUN7uj0GyzLfGFHZdj2+tjFhp1U/FRhawdTjzIh7+sxbabDFHfhMWtOsa7TAeyCDdDbellvkCXYlOINrVPGaAM26rg8aa0FBYsKKiqQaGoHcYf1tQz8I2jU1zCF4VC4x0bc2wZV71vpXr+E1ni/jPalGVoJ0T4TMihUTXB638KnyY9AnKM7obxiukJFCa+guHKvNSBPtzNAEH2OdW8fqAhZ6fNCqd/xKpHy61N1mjGeZWo2CweQc/1RkqpVRKlrjCEgID2K6VwloqsaaCGrVneDIIluy0SHWXR0t+Bm3+0/MMk2Pje2TUNFESQDNSm6qEMJ6lLYKCiPa9CJWAwBH89LP1BOxtPirIHVgWXmfXkiGq2sd1M0E7suAXZaV46UJISvV1PRXR2JrGbvYk8yu9sah8QJZVjIym0G+CZS9PRMP3Gy0xghEUgSmk/5fL0hiiSndphSLW5JJu4+KPvFslBwGVf/upOAjf30dUlMRnFgd6MQCH7jMlu9TbqaYYPmpMMGvy0mp7PDOouIjaQ6w/nXrMo57OUX17Uz57IfFcY+PAlGprA2qUfAm0I/QYfCTHretFnEnsHzyF6QXRWR9m0StBFdt0bJ911bcN7Uu9o0n/hM+JXOkXVjPBrg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(39860400002)(376002)(136003)(451199021)(36840700001)(40470700004)(46966006)(1076003)(26005)(7696005)(40460700003)(36860700001)(36756003)(2616005)(40480700001)(47076005)(83380400001)(426003)(336012)(86362001)(82310400005)(82740400003)(356005)(16526019)(186003)(81166007)(110136005)(316002)(54906003)(44832011)(478600001)(2906002)(4326008)(8936002)(8676002)(41300700001)(5660300002)(70586007)(70206006)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2023 00:56:08.2283 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e2a9398-dd71-4a64-32f1-08db5803d4f2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4123 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766282271987660429?= X-GMAIL-MSGID: =?utf-8?q?1766282271987660429?= With the Interrupt Remapping Table cache disabled, there is no need to issue invalidate IRT and wait for its completion. Therefore, add logic to bypass the operation. Suggested-by: Joao Martins Signed-off-by: Suravee Suthikulpanit Reviewed-by: Jerry Snitselaar --- drivers/iommu/amd/iommu.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 0c4a2796bb0a..51c2b018433d 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1273,12 +1273,24 @@ static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) u32 devid; u16 last_bdf = iommu->pci_seg->last_bdf; + if (iommu->irtcachedis_enabled) + return; + for (devid = 0; devid <= last_bdf; devid++) iommu_flush_irt(iommu, devid); iommu_completion_wait(iommu); } +static void iommu_flush_irt_and_complete(struct amd_iommu *iommu, u16 devid) +{ + if (iommu->irtcachedis_enabled) + return; + + iommu_flush_irt(iommu, devid); + iommu_completion_wait(iommu); +} + void iommu_flush_all_caches(struct amd_iommu *iommu) { if (iommu_feature(iommu, FEATURE_IA)) { @@ -3028,8 +3040,7 @@ static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index, raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); return 0; } @@ -3048,8 +3059,7 @@ static int modify_irte(struct amd_iommu *iommu, table->table[index] = irte->val; raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); return 0; } @@ -3067,8 +3077,7 @@ static void free_irte(struct amd_iommu *iommu, u16 devid, int index) iommu->irte_ops->clear_allocated(table, index); raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); } static void irte_prepare(void *entry, From patchwork Fri May 19 00:55:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suravee Suthikulpanit X-Patchwork-Id: 96151 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp910367vqo; Thu, 18 May 2023 18:20:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7FTa4Kad3cqYEQCbOugzCwW0mXxYJKDNBykNgY9AcykRCx1ft9/KV7Izph0JwJtkOF35TV X-Received: by 2002:a05:6a00:1486:b0:63f:120a:1dc3 with SMTP id v6-20020a056a00148600b0063f120a1dc3mr1265956pfu.0.1684459205346; Thu, 18 May 2023 18:20:05 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1684459205; cv=pass; d=google.com; s=arc-20160816; b=ZOm2Ex6SQC+0/aFthRCIweB5EUGweLkQA87LdUkJv0UtSRXYSFvXlheNXUv4LQV3aQ dj1mpCwV5/jWmO4nicnhTmaziA2/KGxuEqUAYZVx5S8oF24IT9lJrCPqjuhE9i4ChmM2 Dqz8PSKYVcwLM7qsWU5qdQLpzdy+z2p3QFOaswa4cNkYnR93N4G72DBjsCoLF/R1p65J deRm3znH5H/M84X5MxAtKItK6+W3OoyIiIeE+TsiyhZKIDUAzc1m3VgHd3fdGvpMjyXy DblmSVMK0F6Ht4t7IegbeBWLktQT7laM1UZdOJw4t4uh8EOmntX2qJ/PvIada3r3Js7g X9Lw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vBhOL0jUPEE03ICFVxiMjPZqqR2ysO3QoiGzRk2CjJE=; b=lSMyGR61na996anBfpub69dtolh6fy0EnwUbdxLnjI4LBWurCE5C2vmwWSXFykNrxZ 8P/IvPFLiPUhzQOovOrEcu2gsfEhUSP3tuhFoiWZejsqn+BxUHdd0tFsLoL7+Ksug339 UOC4CrGrcVR5yAoORXEcrnCcTMVppShSCOTkdcAnYRM+oWwDHI09C0bFXADyJtveIuzf +MAY+IvRFmTFqZXXHzqClXsZVTzEZKfGls/DTm7KU6STl+7e7w93MKpvbs4qNjXoBtpJ YOjIi6z0w5YKYO2uxRq1g1rw0IDMTyxOE8K7r2D5ghJDipz/h3D2O/3WMAcPxS8BYnLe AAiA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=g+kDhmIQ; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 18 May 2023 19:56:07 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 5/5] iommu/amd: Improving Interrupt Remapping Table Invalidation Date: Thu, 18 May 2023 20:55:29 -0400 Message-ID: <20230519005529.28171-6-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> References: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT057:EE_|MW6PR12MB8949:EE_ X-MS-Office365-Filtering-Correlation-Id: c417290f-4a6a-4f55-0ee3-08db5803d61b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /N0SyD1Je0bHBayAcpfF95+XH2XTkhsYhD77T+Z53qZ6Qg08TjurACrN/C/ImDq/nNJpOFfRUwdNto/kUlIl2kuGDhjoqvRS982HIxaKPH0g0J3WUKQWBggCg1M09vpSyx6qlq16P10GF9popY+0kLBmIGNF5dPxJ2laU0TuzXrmBGBbz4x+ved2689nP8MAkvFH6tryagfqwGkZvEMTmJUXKtHhDFhI6TUlkPtaDRMZX7NNvncvFCR96y1Cnil17alZSLCKS6JRMLaL2zGKN1tA+yyc/8hAMbNVg/64XbTF/AE3x2zPalzaCdMkpzaAHt4hC84fpKsVVyl/Cwgb15eYT9RpViD1FAj36YFfoPSqzgZDngpezxIs+udDdNLd61Mo7DABxgY/IDCE6pRFR0D7/5aCdhJRjjZRse5C1Zw6oJD9dLZvp7sXS6ZonnAo3xv2M08I2Zh9Yk/JarHO27/dsZYYtU8XNB9E8CFbrWWHiWzsu+Tc25tz0BH9pn/3cgVrgbG8TnBTiXb1VHSqY7lFvSgeG4Kp2rg6jQzET+HYNWY+NCcJpZ859GxKPqzN/EbbUpnmr24RO0iKGB1b1xtlqZyXOK/L72EzIkv4Gdadokg6FDBrg9XOWjpUapsV62KVT26ty/z4NpZv3vqujYxxuQhEcgqlN9Gc61FxaRdlUtnYQGvtDAaiGhwpj5r2gDfMLj0r1CG5in0p7y6KBpg+XDJyx3gGOVJTnAY4OvSYutMw2uz3qhgRlaPj0pCp2vxKhR1zezMMGnRTGe3zTQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(39860400002)(376002)(136003)(396003)(451199021)(46966006)(36840700001)(40470700004)(2906002)(44832011)(8676002)(8936002)(316002)(4326008)(70586007)(70206006)(5660300002)(41300700001)(86362001)(2616005)(426003)(47076005)(336012)(110136005)(40460700003)(54906003)(478600001)(36756003)(40480700001)(7696005)(6666004)(1076003)(186003)(26005)(16526019)(36860700001)(83380400001)(82310400005)(81166007)(82740400003)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2023 00:56:10.1738 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c417290f-4a6a-4f55-0ee3-08db5803d61b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8949 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766283495645440977?= X-GMAIL-MSGID: =?utf-8?q?1766283495645440977?= Invalidating Interrupt Remapping Table (IRT) requires, the AMD IOMMU driver to issue INVALIDATE_INTERRUPT_TABLE and COMPLETION_WAIT commands. Currently, the driver issues the two commands separately, which requires calling raw_spin_lock_irqsave() twice. In addition, the COMPLETION_WAIT could potentially be interleaved with other commands causing delay of the COMPLETION_WAIT command. Therefore, combine issuing of the two commands in one spin-lock, and changing struct amd_iommu.cmd_sem_val to use atomic64 to minimize locking. Signed-off-by: Suravee Suthikulpanit Reviewed-by: Jerry Snitselaar --- drivers/iommu/amd/amd_iommu_types.h | 2 +- drivers/iommu/amd/init.c | 2 +- drivers/iommu/amd/iommu.c | 27 ++++++++++++++++++++++----- 3 files changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 486a052e37ca..2fa65da2a9a5 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -744,7 +744,7 @@ struct amd_iommu { u32 flags; volatile u64 *cmd_sem; - u64 cmd_sem_val; + atomic64_t cmd_sem_val; #ifdef CONFIG_AMD_IOMMU_DEBUGFS /* DebugFS Info */ diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index fc0392d706db..16737819f79a 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -1750,7 +1750,7 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, iommu->pci_seg = pci_seg; raw_spin_lock_init(&iommu->lock); - iommu->cmd_sem_val = 0; + atomic64_set(&iommu->cmd_sem_val, 0); /* Add IOMMU to internal data structures */ list_add_tail(&iommu->list, &amd_iommu_list); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 51c2b018433d..57ae4a8072d3 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1182,11 +1182,11 @@ static int iommu_completion_wait(struct amd_iommu *iommu) if (!iommu->need_sync) return 0; - raw_spin_lock_irqsave(&iommu->lock, flags); - - data = ++iommu->cmd_sem_val; + data = atomic64_add_return(1, &iommu->cmd_sem_val); build_completion_wait(&cmd, iommu, data); + raw_spin_lock_irqsave(&iommu->lock, flags); + ret = __iommu_queue_command_sync(iommu, &cmd, false); if (ret) goto out_unlock; @@ -1284,11 +1284,28 @@ static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) static void iommu_flush_irt_and_complete(struct amd_iommu *iommu, u16 devid) { + int ret; + u64 data; + unsigned long flags; + struct iommu_cmd cmd, cmd2; + if (iommu->irtcachedis_enabled) return; - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + build_inv_irt(&cmd, devid); + data = atomic64_add_return(1, &iommu->cmd_sem_val); + build_completion_wait(&cmd2, iommu, data); + + raw_spin_lock_irqsave(&iommu->lock, flags); + ret = __iommu_queue_command_sync(iommu, &cmd, true); + if (ret) + goto out; + ret = __iommu_queue_command_sync(iommu, &cmd2, false); + if (ret) + goto out; + wait_on_sem(iommu, data); +out: + raw_spin_unlock_irqrestore(&iommu->lock, flags); } void iommu_flush_all_caches(struct amd_iommu *iommu)