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Thu, 18 May 2023 10:59:19 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 18 May 2023 10:59:18 +0000 Received: from e127973.arm.com (10.57.22.31) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Thu, 18 May 2023 10:59:18 +0000 To: CC: , , Andrea Corallo Subject: [commited trunk 1/9] arm: Mve testsuite improvements Date: Thu, 18 May 2023 11:59:07 +0100 Message-ID: <20230518105915.1304768-1-stam.markianos-wright@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT030:EE_|DB9PR08MB8338:EE_|DBAEUR03FT026:EE_|DB9PR08MB9610:EE_ X-MS-Office365-Filtering-Correlation-Id: 39914fc1-3b8f-45b1-8408-08db578ef87b x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT026.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB9610 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Stam Markianos-Wright via Gcc-patches From: Stamatis Markianos-Wright Reply-To: Stam Markianos-Wright Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766229381182260249?= X-GMAIL-MSGID: =?utf-8?q?1766229815827680394?= From: Andrea Corallo Hello all, this patch improves a number of MVE tests in the testsuite for more precise and better coverage using check-function-bodies instead of scan-assembler checks. Also all intrusctions prescribed in the ACLE[1] are now checked. Best Regards Andrea [1] gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vld1q_f16.c: Use check-function-bodies instead of scan-assembler checks. Use extern "C" for C++ testing. * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise. --- .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 29 +++++++++-- .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 29 +++++++++-- .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 29 +++++++++-- .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 29 +++++++++-- .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 29 +++++++++-- .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 29 +++++++++-- .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 29 +++++++++-- .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 29 +++++++++-- .../arm/mve/intrinsics/vld1q_z_f16.c | 38 ++++++++++++-- .../arm/mve/intrinsics/vld1q_z_f32.c | 38 ++++++++++++-- .../arm/mve/intrinsics/vld1q_z_s16.c | 38 ++++++++++++-- .../arm/mve/intrinsics/vld1q_z_s32.c | 38 ++++++++++++-- .../arm/mve/intrinsics/vld1q_z_s8.c | 38 ++++++++++++-- .../arm/mve/intrinsics/vld1q_z_u16.c | 38 ++++++++++++-- .../arm/mve/intrinsics/vld1q_z_u32.c | 38 ++++++++++++-- .../arm/mve/intrinsics/vld1q_z_u8.c | 38 ++++++++++++-- .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 37 +++++++++++--- .../mve/intrinsics/vldrbq_gather_offset_s16.c | 28 +++++++++-- .../mve/intrinsics/vldrbq_gather_offset_s32.c | 28 +++++++++-- .../mve/intrinsics/vldrbq_gather_offset_s8.c | 28 +++++++++-- .../mve/intrinsics/vldrbq_gather_offset_u16.c | 28 +++++++++-- .../mve/intrinsics/vldrbq_gather_offset_u32.c | 28 +++++++++-- .../mve/intrinsics/vldrbq_gather_offset_u8.c | 28 +++++++++-- .../intrinsics/vldrbq_gather_offset_z_s16.c | 36 +++++++++++-- .../intrinsics/vldrbq_gather_offset_z_s32.c | 36 +++++++++++-- .../intrinsics/vldrbq_gather_offset_z_s8.c | 36 +++++++++++-- .../intrinsics/vldrbq_gather_offset_z_u16.c | 36 +++++++++++-- .../intrinsics/vldrbq_gather_offset_z_u32.c | 36 +++++++++++-- .../intrinsics/vldrbq_gather_offset_z_u8.c | 36 +++++++++++-- .../arm/mve/intrinsics/vldrbq_s16.c | 19 ++++++- .../arm/mve/intrinsics/vldrbq_s32.c | 19 ++++++- .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 20 ++++++-- .../arm/mve/intrinsics/vldrbq_u16.c | 19 ++++++- .../arm/mve/intrinsics/vldrbq_u32.c | 19 ++++++- .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 20 ++++++-- .../arm/mve/intrinsics/vldrbq_z_s16.c | 23 ++++++++- .../arm/mve/intrinsics/vldrbq_z_s32.c | 23 ++++++++- .../arm/mve/intrinsics/vldrbq_z_s8.c | 25 ++++++++-- .../arm/mve/intrinsics/vldrbq_z_u16.c | 23 ++++++++- .../arm/mve/intrinsics/vldrbq_z_u32.c | 23 ++++++++- .../arm/mve/intrinsics/vldrbq_z_u8.c | 25 ++++++++-- .../mve/intrinsics/vldrdq_gather_base_s64.c | 19 ++++++- .../mve/intrinsics/vldrdq_gather_base_u64.c | 19 ++++++- .../intrinsics/vldrdq_gather_base_wb_s64.c | 24 ++++++--- .../intrinsics/vldrdq_gather_base_wb_u64.c | 24 ++++++--- .../intrinsics/vldrdq_gather_base_wb_z_s64.c | 31 +++++++++--- .../intrinsics/vldrdq_gather_base_wb_z_u64.c | 31 +++++++++--- .../mve/intrinsics/vldrdq_gather_base_z_s64.c | 23 ++++++++- .../mve/intrinsics/vldrdq_gather_base_z_u64.c | 23 ++++++++- .../mve/intrinsics/vldrdq_gather_offset_s64.c | 28 +++++++++-- .../mve/intrinsics/vldrdq_gather_offset_u64.c | 28 +++++++++-- .../intrinsics/vldrdq_gather_offset_z_s64.c | 36 +++++++++++-- .../intrinsics/vldrdq_gather_offset_z_u64.c | 36 +++++++++++-- .../vldrdq_gather_shifted_offset_s64.c | 28 +++++++++-- .../vldrdq_gather_shifted_offset_u64.c | 28 +++++++++-- .../vldrdq_gather_shifted_offset_z_s64.c | 36 +++++++++++-- .../vldrdq_gather_shifted_offset_z_u64.c | 36 +++++++++++-- .../arm/mve/intrinsics/vldrhq_f16.c | 20 ++++++-- .../mve/intrinsics/vldrhq_gather_offset_f16.c | 28 +++++++++-- .../mve/intrinsics/vldrhq_gather_offset_s16.c | 28 +++++++++-- .../mve/intrinsics/vldrhq_gather_offset_s32.c | 28 +++++++++-- .../mve/intrinsics/vldrhq_gather_offset_u16.c | 28 +++++++++-- .../mve/intrinsics/vldrhq_gather_offset_u32.c | 28 +++++++++-- .../intrinsics/vldrhq_gather_offset_z_f16.c | 36 +++++++++++-- .../intrinsics/vldrhq_gather_offset_z_s16.c | 36 +++++++++++-- .../intrinsics/vldrhq_gather_offset_z_s32.c | 36 +++++++++++-- .../intrinsics/vldrhq_gather_offset_z_u16.c | 36 +++++++++++-- .../intrinsics/vldrhq_gather_offset_z_u32.c | 36 +++++++++++-- .../vldrhq_gather_shifted_offset_f16.c | 28 +++++++++-- .../vldrhq_gather_shifted_offset_s16.c | 28 +++++++++-- .../vldrhq_gather_shifted_offset_s32.c | 28 +++++++++-- .../vldrhq_gather_shifted_offset_u16.c | 28 +++++++++-- .../vldrhq_gather_shifted_offset_u32.c | 28 +++++++++-- .../vldrhq_gather_shifted_offset_z_f16.c | 36 +++++++++++-- .../vldrhq_gather_shifted_offset_z_s16.c | 36 +++++++++++-- .../vldrhq_gather_shifted_offset_z_s32.c | 36 +++++++++++-- .../vldrhq_gather_shifted_offset_z_u16.c | 36 +++++++++++-- .../vldrhq_gather_shifted_offset_z_u32.c | 36 +++++++++++-- .../arm/mve/intrinsics/vldrhq_s16.c | 20 ++++++-- .../arm/mve/intrinsics/vldrhq_s32.c | 20 ++++++-- .../arm/mve/intrinsics/vldrhq_u16.c | 20 ++++++-- .../arm/mve/intrinsics/vldrhq_u32.c | 20 ++++++-- .../arm/mve/intrinsics/vldrhq_z_f16.c | 23 +++++++-- .../arm/mve/intrinsics/vldrhq_z_s16.c | 23 +++++++-- .../arm/mve/intrinsics/vldrhq_z_s32.c | 25 ++++++++-- .../arm/mve/intrinsics/vldrhq_z_u16.c | 23 +++++++-- .../arm/mve/intrinsics/vldrhq_z_u32.c | 25 ++++++++-- .../arm/mve/intrinsics/vldrwq_f32.c | 18 ++++++- .../mve/intrinsics/vldrwq_gather_base_f32.c | 19 ++++++- .../mve/intrinsics/vldrwq_gather_base_s32.c | 19 ++++++- .../mve/intrinsics/vldrwq_gather_base_u32.c | 19 ++++++- .../intrinsics/vldrwq_gather_base_wb_f32.c | 22 ++++++-- .../intrinsics/vldrwq_gather_base_wb_s32.c | 22 ++++++-- .../intrinsics/vldrwq_gather_base_wb_u32.c | 22 ++++++-- .../intrinsics/vldrwq_gather_base_wb_z_f32.c | 28 ++++++++--- .../intrinsics/vldrwq_gather_base_wb_z_s32.c | 28 ++++++++--- .../intrinsics/vldrwq_gather_base_wb_z_u32.c | 28 ++++++++--- .../mve/intrinsics/vldrwq_gather_base_z_f32.c | 23 ++++++++- .../mve/intrinsics/vldrwq_gather_base_z_s32.c | 23 ++++++++- .../mve/intrinsics/vldrwq_gather_base_z_u32.c | 23 ++++++++- .../mve/intrinsics/vldrwq_gather_offset_f32.c | 28 +++++++++-- .../mve/intrinsics/vldrwq_gather_offset_s32.c | 28 +++++++++-- .../mve/intrinsics/vldrwq_gather_offset_u32.c | 28 +++++++++-- .../intrinsics/vldrwq_gather_offset_z_f32.c | 36 +++++++++++-- .../intrinsics/vldrwq_gather_offset_z_s32.c | 36 +++++++++++-- .../intrinsics/vldrwq_gather_offset_z_u32.c | 36 +++++++++++-- .../vldrwq_gather_shifted_offset_f32.c | 28 +++++++++-- .../vldrwq_gather_shifted_offset_s32.c | 28 +++++++++-- .../vldrwq_gather_shifted_offset_u32.c | 28 +++++++++-- .../vldrwq_gather_shifted_offset_z_f32.c | 36 +++++++++++-- .../vldrwq_gather_shifted_offset_z_s32.c | 36 +++++++++++-- .../vldrwq_gather_shifted_offset_z_u32.c | 36 +++++++++++-- .../arm/mve/intrinsics/vldrwq_s32.c | 18 ++++++- .../arm/mve/intrinsics/vldrwq_u32.c | 18 ++++++- .../arm/mve/intrinsics/vldrwq_z_f32.c | 23 +++++++-- .../arm/mve/intrinsics/vldrwq_z_s32.c | 23 +++++++-- .../arm/mve/intrinsics/vldrwq_z_u32.c | 23 +++++++-- .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 37 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 50 +++++++++++-------- .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 50 +++++++++++-------- .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 50 +++++++++++-------- .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 50 +++++++++++-------- .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 50 +++++++++++-------- .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 50 +++++++++++-------- .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 50 +++++++++++-------- .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 50 +++++++++++-------- .../arm/mve/intrinsics/vstrbq_p_s16.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrbq_p_s32.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrbq_p_s8.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrbq_p_u16.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrbq_p_u32.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrbq_p_u8.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrbq_s16.c | 32 +++++++++--- .../arm/mve/intrinsics/vstrbq_s32.c | 32 +++++++++--- .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 32 +++++++++--- .../intrinsics/vstrbq_scatter_offset_p_s16.c | 40 ++++++++++++--- .../intrinsics/vstrbq_scatter_offset_p_s32.c | 40 ++++++++++++--- .../intrinsics/vstrbq_scatter_offset_p_s8.c | 40 ++++++++++++--- .../intrinsics/vstrbq_scatter_offset_p_u16.c | 40 ++++++++++++--- .../intrinsics/vstrbq_scatter_offset_p_u32.c | 40 ++++++++++++--- .../intrinsics/vstrbq_scatter_offset_p_u8.c | 40 ++++++++++++--- .../intrinsics/vstrbq_scatter_offset_s16.c | 32 +++++++++--- .../intrinsics/vstrbq_scatter_offset_s32.c | 32 +++++++++--- .../mve/intrinsics/vstrbq_scatter_offset_s8.c | 32 +++++++++--- .../intrinsics/vstrbq_scatter_offset_u16.c | 32 +++++++++--- .../intrinsics/vstrbq_scatter_offset_u32.c | 32 +++++++++--- .../mve/intrinsics/vstrbq_scatter_offset_u8.c | 32 +++++++++--- .../arm/mve/intrinsics/vstrbq_u16.c | 32 +++++++++--- .../arm/mve/intrinsics/vstrbq_u32.c | 32 +++++++++--- .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 32 +++++++++--- .../arm/mve/intrinsics/vstrhq_f16.c | 32 +++++++++--- .../arm/mve/intrinsics/vstrhq_p_f16.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrhq_p_s16.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrhq_p_s32.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrhq_p_u16.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrhq_p_u32.c | 40 ++++++++++++--- .../arm/mve/intrinsics/vstrhq_s16.c | 32 +++++++++--- .../arm/mve/intrinsics/vstrhq_s32.c | 32 +++++++++--- .../intrinsics/vstrhq_scatter_offset_f16.c | 32 +++++++++--- .../intrinsics/vstrhq_scatter_offset_p_f16.c | 40 ++++++++++++--- .../intrinsics/vstrhq_scatter_offset_p_s16.c | 40 ++++++++++++--- .../intrinsics/vstrhq_scatter_offset_p_s32.c | 40 ++++++++++++--- .../intrinsics/vstrhq_scatter_offset_p_u16.c | 40 ++++++++++++--- .../intrinsics/vstrhq_scatter_offset_p_u32.c | 40 ++++++++++++--- .../intrinsics/vstrhq_scatter_offset_s16.c | 32 +++++++++--- .../intrinsics/vstrhq_scatter_offset_s32.c | 32 +++++++++--- .../intrinsics/vstrhq_scatter_offset_u16.c | 32 +++++++++--- .../intrinsics/vstrhq_scatter_offset_u32.c | 32 +++++++++--- .../vstrhq_scatter_shifted_offset_f16.c | 32 +++++++++--- .../vstrhq_scatter_shifted_offset_p_f16.c | 40 ++++++++++++--- .../vstrhq_scatter_shifted_offset_p_s16.c | 40 ++++++++++++--- .../vstrhq_scatter_shifted_offset_p_s32.c | 40 ++++++++++++--- .../vstrhq_scatter_shifted_offset_p_u16.c | 40 ++++++++++++--- .../vstrhq_scatter_shifted_offset_p_u32.c | 40 ++++++++++++--- .../vstrhq_scatter_shifted_offset_s16.c | 32 +++++++++--- .../vstrhq_scatter_shifted_offset_s32.c | 32 +++++++++--- .../vstrhq_scatter_shifted_offset_u16.c | 32 +++++++++--- .../vstrhq_scatter_shifted_offset_u32.c | 32 +++++++++--- .../arm/mve/intrinsics/vstrhq_u16.c | 32 +++++++++--- .../arm/mve/intrinsics/vstrhq_u32.c | 32 +++++++++--- 194 files changed, 5171 insertions(+), 1035 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c index 699e40d0e3b..f0a9243a6d5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c @@ -1,20 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float16x8_t -foo (float16_t const * base) +foo (float16_t const *base) { return vld1q_f16 (base); } + +/* +**foo1: +** ... +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float16x8_t -foo1 (float16_t const * base) +foo1 (float16_t const *base) { return vld1q (base); } -/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c index 86592303362..129d256dd86 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c @@ -1,20 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float32x4_t -foo (float32_t const * base) +foo (float32_t const *base) { return vld1q_f32 (base); } + +/* +**foo1: +** ... +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float32x4_t -foo1 (float32_t const * base) +foo1 (float32_t const *base) { return vld1q (base); } -/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c index f4f04f534db..a95bf6c4260 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c @@ -1,20 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int16x8_t -foo (int16_t const * base) +foo (int16_t const *base) { return vld1q_s16 (base); } + +/* +**foo1: +** ... +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int16x8_t -foo1 (int16_t const * base) +foo1 (int16_t const *base) { return vld1q (base); } -/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c index e0f66166751..bb24e52d164 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c @@ -1,20 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int32x4_t -foo (int32_t const * base) +foo (int32_t const *base) { return vld1q_s32 (base); } + +/* +**foo1: +** ... +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int32_t const * base) +foo1 (int32_t const *base) { return vld1q (base); } -/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c index 1b7edead6b1..0d89c2f19cd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c @@ -1,20 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int8x16_t -foo (int8_t const * base) +foo (int8_t const *base) { return vld1q_s8 (base); } + +/* +**foo1: +** ... +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int8x16_t -foo1 (int8_t const * base) +foo1 (int8_t const *base) { return vld1q (base); } -/* { dg-final { scan-assembler-times "vldrb.8" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c index 50e1f5cedcb..a31baf75fed 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c @@ -1,20 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint16_t const * base) +foo (uint16_t const *base) { return vld1q_u16 (base); } + +/* +**foo1: +** ... +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint16_t const * base) +foo1 (uint16_t const *base) { return vld1q (base); } -/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c index a13fe824382..7d4f858c784 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c @@ -1,20 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint32_t const * base) +foo (uint32_t const *base) { return vld1q_u32 (base); } + +/* +**foo1: +** ... +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint32_t const * base) +foo1 (uint32_t const *base) { return vld1q (base); } -/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c index dfd1deb93f0..455ec5ce105 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c @@ -1,20 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint8x16_t -foo (uint8_t const * base) +foo (uint8_t const *base) { return vld1q_u8 (base); } + +/* +**foo1: +** ... +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint8x16_t -foo1 (uint8_t const * base) +foo1 (uint8_t const *base) { return vld1q (base); } -/* { dg-final { scan-assembler-times "vldrb.8" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c index 3c32e408e42..951b795fd59 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float16x8_t -foo (float16_t const * base, mve_pred16_t p) +foo (float16_t const *base, mve_pred16_t p) { return vld1q_z_f16 (base, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float16x8_t -foo1 (float16_t const * base, mve_pred16_t p) +foo1 (float16_t const *base, mve_pred16_t p) { return vld1q_z (base, p); } -/* { dg-final { scan-assembler-times "vpst" 2 } } */ -/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c index 3fc935c889b..4b43f0f4be3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float32x4_t -foo (float32_t const * base, mve_pred16_t p) +foo (float32_t const *base, mve_pred16_t p) { return vld1q_z_f32 (base, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float32x4_t -foo1 (float32_t const * base, mve_pred16_t p) +foo1 (float32_t const *base, mve_pred16_t p) { return vld1q_z (base, p); } -/* { dg-final { scan-assembler-times "vpst" 2 } } */ -/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c index 49cc81092f3..a65c10c5fc1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int16x8_t -foo (int16_t const * base, mve_pred16_t p) +foo (int16_t const *base, mve_pred16_t p) { return vld1q_z_s16 (base, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int16x8_t -foo1 (int16_t const * base, mve_pred16_t p) +foo1 (int16_t const *base, mve_pred16_t p) { return vld1q_z (base, p); } -/* { dg-final { scan-assembler-times "vpst" 2 } } */ -/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c index ec317cd70e8..31749046fc6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int32x4_t -foo (int32_t const * base, mve_pred16_t p) +foo (int32_t const *base, mve_pred16_t p) { return vld1q_z_s32 (base, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int32_t const * base, mve_pred16_t p) +foo1 (int32_t const *base, mve_pred16_t p) { return vld1q_z (base, p); } -/* { dg-final { scan-assembler-times "vpst" 2 } } */ -/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c index 538c140e78e..990522faee8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int8x16_t -foo (int8_t const * base, mve_pred16_t p) +foo (int8_t const *base, mve_pred16_t p) { return vld1q_z_s8 (base, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int8x16_t -foo1 (int8_t const * base, mve_pred16_t p) +foo1 (int8_t const *base, mve_pred16_t p) { return vld1q_z (base, p); } -/* { dg-final { scan-assembler-times "vpst" 2 } } */ -/* { dg-final { scan-assembler-times "vldrbt.8" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c index e5e588a187e..8a41b42306c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint16_t const * base, mve_pred16_t p) +foo (uint16_t const *base, mve_pred16_t p) { return vld1q_z_u16 (base, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint16_t const * base, mve_pred16_t p) +foo1 (uint16_t const *base, mve_pred16_t p) { return vld1q_z (base, p); } -/* { dg-final { scan-assembler-times "vpst" 2 } } */ -/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c index 999beefa7e8..67b200f6028 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint32_t const * base, mve_pred16_t p) +foo (uint32_t const *base, mve_pred16_t p) { return vld1q_z_u32 (base, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint32_t const * base, mve_pred16_t p) +foo1 (uint32_t const *base, mve_pred16_t p) { return vld1q_z (base, p); } -/* { dg-final { scan-assembler-times "vpst" 2 } } */ -/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c index 172053c7142..c113a0db3e1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint8x16_t -foo (uint8_t const * base, mve_pred16_t p) +foo (uint8_t const *base, mve_pred16_t p) { return vld1q_z_u8 (base, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint8x16_t -foo1 (uint8_t const * base, mve_pred16_t p) +foo1 (uint8_t const *base, mve_pred16_t p) { return vld1q_z (base, p); } -/* { dg-final { scan-assembler-times "vpst" 2 } } */ -/* { dg-final { scan-assembler-times "vldrbt.8" 2 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c index db50f27bb60..e554cdab33d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c @@ -1,24 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ float16x8x4_t -foo (float16_t const * addr) +foo (float16_t const *addr) { return vld4q_f16 (addr); } -/* { dg-final { scan-assembler "vld40.16" } } */ -/* { dg-final { scan-assembler "vld41.16" } } */ -/* { dg-final { scan-assembler "vld42.16" } } */ -/* { dg-final { scan-assembler "vld43.16" } } */ +/* +**foo1: +** ... +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ float16x8x4_t -foo1 (float16_t const * addr) +foo1 (float16_t const *addr) { return vld4q (addr); } -/* { dg-final { scan-assembler "vld40.16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c index de3fe0e79fc..be61054d331 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c @@ -1,24 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ float32x4x4_t -foo (float32_t const * addr) +foo (float32_t const *addr) { return vld4q_f32 (addr); } -/* { dg-final { scan-assembler "vld40.32" } } */ -/* { dg-final { scan-assembler "vld41.32" } } */ -/* { dg-final { scan-assembler "vld42.32" } } */ -/* { dg-final { scan-assembler "vld43.32" } } */ +/* +**foo1: +** ... +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ float32x4x4_t -foo1 (float32_t const * addr) +foo1 (float32_t const *addr) { return vld4q (addr); } -/* { dg-final { scan-assembler "vld40.32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c index 41a9dd86a4f..f9cbc17da61 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c @@ -1,24 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ int16x8x4_t -foo (int16_t const * addr) +foo (int16_t const *addr) { return vld4q_s16 (addr); } -/* { dg-final { scan-assembler "vld40.16" } } */ -/* { dg-final { scan-assembler "vld41.16" } } */ -/* { dg-final { scan-assembler "vld42.16" } } */ -/* { dg-final { scan-assembler "vld43.16" } } */ +/* +**foo1: +** ... +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ int16x8x4_t -foo1 (int16_t const * addr) +foo1 (int16_t const *addr) { return vld4q (addr); } -/* { dg-final { scan-assembler "vld40.16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c index 6f29c1b28c0..056e26023a9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c @@ -1,24 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ int32x4x4_t -foo (int32_t const * addr) +foo (int32_t const *addr) { return vld4q_s32 (addr); } -/* { dg-final { scan-assembler "vld40.32" } } */ -/* { dg-final { scan-assembler "vld41.32" } } */ -/* { dg-final { scan-assembler "vld42.32" } } */ -/* { dg-final { scan-assembler "vld43.32" } } */ +/* +**foo1: +** ... +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ int32x4x4_t -foo1 (int32_t const * addr) +foo1 (int32_t const *addr) { return vld4q (addr); } -/* { dg-final { scan-assembler "vld40.32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c index 7701facb55c..2bec51ab4f6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c @@ -1,24 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ int8x16x4_t -foo (int8_t const * addr) +foo (int8_t const *addr) { return vld4q_s8 (addr); } -/* { dg-final { scan-assembler "vld40.8" } } */ -/* { dg-final { scan-assembler "vld41.8" } } */ -/* { dg-final { scan-assembler "vld42.8" } } */ -/* { dg-final { scan-assembler "vld43.8" } } */ +/* +**foo1: +** ... +** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ int8x16x4_t -foo1 (int8_t const * addr) +foo1 (int8_t const *addr) { return vld4q (addr); } -/* { dg-final { scan-assembler "vld40.8" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c index 5a5e22d36d0..a2c98670174 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c @@ -1,24 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ uint16x8x4_t -foo (uint16_t const * addr) +foo (uint16_t const *addr) { return vld4q_u16 (addr); } -/* { dg-final { scan-assembler "vld40.16" } } */ -/* { dg-final { scan-assembler "vld41.16" } } */ -/* { dg-final { scan-assembler "vld42.16" } } */ -/* { dg-final { scan-assembler "vld43.16" } } */ +/* +**foo1: +** ... +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ uint16x8x4_t -foo1 (uint16_t const * addr) +foo1 (uint16_t const *addr) { return vld4q (addr); } -/* { dg-final { scan-assembler "vld40.16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c index e40d9b24fb4..4bbe56db205 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c @@ -1,24 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ uint32x4x4_t -foo (uint32_t const * addr) +foo (uint32_t const *addr) { return vld4q_u32 (addr); } -/* { dg-final { scan-assembler "vld40.32" } } */ -/* { dg-final { scan-assembler "vld41.32" } } */ -/* { dg-final { scan-assembler "vld42.32" } } */ -/* { dg-final { scan-assembler "vld43.32" } } */ +/* +**foo1: +** ... +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ uint32x4x4_t -foo1 (uint32_t const * addr) +foo1 (uint32_t const *addr) { return vld4q (addr); } -/* { dg-final { scan-assembler "vld40.32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c index 0d9abc36190..63353dba4b6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c @@ -1,24 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ uint8x16x4_t -foo (uint8_t const * addr) +foo (uint8_t const *addr) { return vld4q_u8 (addr); } -/* { dg-final { scan-assembler "vld40.8" } } */ -/* { dg-final { scan-assembler "vld41.8" } } */ -/* { dg-final { scan-assembler "vld42.8" } } */ -/* { dg-final { scan-assembler "vld43.8" } } */ +/* +**foo1: +** ... +** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ uint8x16x4_t -foo1 (uint8_t const * addr) +foo1 (uint8_t const *addr) { return vld4q (addr); } -/* { dg-final { scan-assembler "vld40.8" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c index 0f6c24dde0a..ce4255b8430 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int16x8_t -foo (int8_t const * base, uint16x8_t offset) +foo (int8_t const *base, uint16x8_t offset) { return vldrbq_gather_offset_s16 (base, offset); } -/* { dg-final { scan-assembler "vldrb.s16" } } */ +/* +**foo1: +** ... +** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int16x8_t -foo1 (int8_t const * base, uint16x8_t offset) +foo1 (int8_t const *base, uint16x8_t offset) { return vldrbq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrb.s16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c index 4c1415d2c5f..cd5eb6b9e66 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo (int8_t const * base, uint32x4_t offset) +foo (int8_t const *base, uint32x4_t offset) { return vldrbq_gather_offset_s32 (base, offset); } -/* { dg-final { scan-assembler "vldrb.s32" } } */ +/* +**foo1: +** ... +** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int8_t const * base, uint32x4_t offset) +foo1 (int8_t const *base, uint32x4_t offset) { return vldrbq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrb.s32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c index 4108bbae3e2..5ef4a895082 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int8x16_t -foo (int8_t const * base, uint8x16_t offset) +foo (int8_t const *base, uint8x16_t offset) { return vldrbq_gather_offset_s8 (base, offset); } -/* { dg-final { scan-assembler "vldrb.u8" } } */ +/* +**foo1: +** ... +** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int8x16_t -foo1 (int8_t const * base, uint8x16_t offset) +foo1 (int8_t const *base, uint8x16_t offset) { return vldrbq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrb.u8" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c index 5d5b005a8f4..cfec3c66a54 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint8_t const * base, uint16x8_t offset) +foo (uint8_t const *base, uint16x8_t offset) { return vldrbq_gather_offset_u16 (base, offset); } -/* { dg-final { scan-assembler "vldrb.u16" } } */ +/* +**foo1: +** ... +** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint8_t const * base, uint16x8_t offset) +foo1 (uint8_t const *base, uint16x8_t offset) { return vldrbq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrb.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c index 7c2d92b7c58..f416a03c325 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint8_t const * base, uint32x4_t offset) +foo (uint8_t const *base, uint32x4_t offset) { return vldrbq_gather_offset_u32 (base, offset); } -/* { dg-final { scan-assembler "vldrb.u32" } } */ +/* +**foo1: +** ... +** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint8_t const * base, uint32x4_t offset) +foo1 (uint8_t const *base, uint32x4_t offset) { return vldrbq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrb.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c index 110f9db0296..e8bdd1eabb6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint8x16_t -foo (uint8_t const * base, uint8x16_t offset) +foo (uint8_t const *base, uint8x16_t offset) { return vldrbq_gather_offset_u8 (base, offset); } -/* { dg-final { scan-assembler "vldrb.u8" } } */ +/* +**foo1: +** ... +** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint8x16_t -foo1 (uint8_t const * base, uint8x16_t offset) +foo1 (uint8_t const *base, uint8x16_t offset) { return vldrbq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrb.u8" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c index f0616b5ab8d..9a134609780 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int16x8_t -foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p) +foo (int8_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z_s16 (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int16x8_t -foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p) +foo1 (int8_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.s16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c index 5bf291d4ba5..f47e02076b2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (int8_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z_s32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (int8_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.s32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c index a3798a01b5f..e2b58b47f1d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int8x16_t -foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p) +foo (int8_t const *base, uint8x16_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z_s8 (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int8x16_t -foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p) +foo1 (int8_t const *base, uint8x16_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.u8" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c index 578bd15c66e..2a1801fc941 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) +foo (uint8_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z_u16 (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) +foo1 (uint8_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c index a58044af176..c415fe26ba8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (uint8_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z_u32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (uint8_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c index 0e06833961b..90a19680999 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint8x16_t -foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) +foo (uint8_t const *base, uint8x16_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z_u8 (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint8x16_t -foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) +foo1 (uint8_t const *base, uint8x16_t offset, mve_pred16_t p) { return vldrbq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrbt.u8" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c index 4403092b988..c54e04dbdda 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c @@ -1,13 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int16x8_t -foo (int8_t const * base) +foo (int8_t const *base) { return vldrbq_s16 (base); } -/* { dg-final { scan-assembler "vldrb.s16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c index 95ea9364ffc..1623f53d971 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c @@ -1,13 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int32x4_t -foo (int8_t const * base) +foo (int8_t const *base) { return vldrbq_s32 (base); } -/* { dg-final { scan-assembler "vldrb.s32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c index ec2f2176ccf..b1c141ae287 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c @@ -1,14 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int8x16_t -foo (int8_t const * base) +foo (int8_t const *base) { return vldrbq_s8 (base); } -/* { dg-final { scan-assembler-times "vldrb.8" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c index 2fb297f92ad..203e2e9de83 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c @@ -1,13 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint8_t const * base) +foo (uint8_t const *base) { return vldrbq_u16 (base); } -/* { dg-final { scan-assembler "vldrb.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c index dc555c1be2d..2005c3a2bbf 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c @@ -1,13 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint8_t const * base) +foo (uint8_t const *base) { return vldrbq_u32 (base); } -/* { dg-final { scan-assembler "vldrb.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c index d07b472a4ff..b4c109eb147 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c @@ -1,14 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint8x16_t -foo (uint8_t const * base) +foo (uint8_t const *base) { return vldrbq_u8 (base); } -/* { dg-final { scan-assembler-times "vldrb.8" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c index 8bd08ab5cff..813f6a31a25 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int16x8_t -foo (int8_t const * base, mve_pred16_t p) +foo (int8_t const *base, mve_pred16_t p) { return vldrbq_z_s16 (base, p); } -/* { dg-final { scan-assembler "vldrbt.s16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c index 0309ff4111b..10e1dbf6ad9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int32x4_t -foo (int8_t const * base, mve_pred16_t p) +foo (int8_t const *base, mve_pred16_t p) { return vldrbq_z_s32 (base, p); } -/* { dg-final { scan-assembler "vldrbt.s32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c index aed3c910063..de361d4c9a0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int8x16_t -foo (int8_t const * base, mve_pred16_t p) +foo (int8_t const *base, mve_pred16_t p) { return vldrbq_z_s8 (base, p); } -/* { dg-final { scan-assembler-times "vpst" 1 } } */ -/* { dg-final { scan-assembler-times "vldrbt.8" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c index adcb0cfa2ae..ba4401045e7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint8_t const * base, mve_pred16_t p) +foo (uint8_t const *base, mve_pred16_t p) { return vldrbq_z_u16 (base, p); } -/* { dg-final { scan-assembler "vldrbt.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c index 6b7bce60d62..adc88a59a71 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint8_t const * base, mve_pred16_t p) +foo (uint8_t const *base, mve_pred16_t p) { return vldrbq_z_u32 (base, p); } -/* { dg-final { scan-assembler "vldrbt.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c index 54c61e74454..b13d9fb426f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint8x16_t -foo (uint8_t const * base, mve_pred16_t p) +foo (uint8_t const *base, mve_pred16_t p) { return vldrbq_z_u8 (base, p); } -/* { dg-final { scan-assembler-times "vpst" 1 } } */ -/* { dg-final { scan-assembler-times "vldrbt.8" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c index 6499f930c40..3539c1e40ba 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c @@ -1,13 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ int64x2_t foo (uint64x2_t addr) { - return vldrdq_gather_base_s64 (addr, 8); + return vldrdq_gather_base_s64 (addr, 0); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrd.64" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c index 9a11638a261..2245df61a4e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c @@ -1,13 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ uint64x2_t foo (uint64x2_t addr) { - return vldrdq_gather_base_u64 (addr, 8); + return vldrdq_gather_base_u64 (addr, 0); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrd.64" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c index a9b1f81b62d..e3fd7f16a31 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c @@ -1,16 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ int64x2_t -foo (uint64x2_t * addr) +foo (uint64x2_t *addr) { - return vldrdq_gather_base_wb_s64 (addr, 8); + return vldrdq_gather_base_wb_s64 (addr, 0); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ -/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c index e32a06695ae..161cf00b65e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c @@ -1,16 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ uint64x2_t -foo (uint64x2_t * addr) +foo (uint64x2_t *addr) { - return vldrdq_gather_base_wb_u64 (addr, 8); + return vldrdq_gather_base_wb_u64 (addr, 0); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ -/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c index bb06cf88e32..0716baa635a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + #include "arm_mve.h" -int64x2_t foo (uint64x2_t * addr, mve_pred16_t p) +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ +int64x2_t +foo (uint64x2_t *addr, mve_pred16_t p) { - return vldrdq_gather_base_wb_z_s64 (addr, 1016, p); + return vldrdq_gather_base_wb_z_s64 (addr, 0, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ -/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c index 558115d49ef..242c7c06e27 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + #include "arm_mve.h" -uint64x2_t foo (uint64x2_t * addr, mve_pred16_t p) +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ +uint64x2_t +foo (uint64x2_t *addr, mve_pred16_t p) { - return vldrdq_gather_base_wb_z_u64 (addr, 8, p); + return vldrdq_gather_base_wb_z_u64 (addr, 0, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ -/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c index d7455b49206..d451f4e693f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ int64x2_t foo (uint64x2_t addr, mve_pred16_t p) { - return vldrdq_gather_base_z_s64 (addr, 8, p); + return vldrdq_gather_base_z_s64 (addr, 0, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrdt.u64" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c index 07f72d422b4..508db3ca538 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ uint64x2_t foo (uint64x2_t addr, mve_pred16_t p) { - return vldrdq_gather_base_z_u64 (addr, 8, p); + return vldrdq_gather_base_z_u64 (addr, 0, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrdt.u64" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c index 1d2d904efc4..9431491f3fd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int64x2_t -foo (int64_t const * base, uint64x2_t offset) +foo (int64_t const *base, uint64x2_t offset) { return vldrdq_gather_offset_s64 (base, offset); } -/* { dg-final { scan-assembler "vldrd.u64" } } */ +/* +**foo1: +** ... +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int64x2_t -foo1 (int64_t const * base, uint64x2_t offset) +foo1 (int64_t const *base, uint64x2_t offset) { return vldrdq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrd.u64" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c index 49a3b134d2f..11c0872f5a7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint64x2_t -foo (uint64_t const * base, uint64x2_t offset) +foo (uint64_t const *base, uint64x2_t offset) { return vldrdq_gather_offset_u64 (base, offset); } -/* { dg-final { scan-assembler "vldrd.u64" } } */ +/* +**foo1: +** ... +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint64x2_t -foo1 (uint64_t const * base, uint64x2_t offset) +foo1 (uint64_t const *base, uint64x2_t offset) { return vldrdq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrd.u64" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c index 1ff5f2acd1b..f474cbef788 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int64x2_t -foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p) +foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p) { return vldrdq_gather_offset_z_s64 (base, offset, p); } -/* { dg-final { scan-assembler "vldrdt.u64" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int64x2_t -foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p) +foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p) { return vldrdq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrdt.u64" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c index 63b2254d171..19136d7f451 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint64x2_t -foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) +foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) { return vldrdq_gather_offset_z_u64 (base, offset, p); } -/* { dg-final { scan-assembler "vldrdt.u64" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint64x2_t -foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) +foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) { return vldrdq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrdt.u64" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c index 4feb9c06fcd..ad11d8fa5cb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) +** ... +*/ int64x2_t -foo (int64_t const * base, uint64x2_t offset) +foo (int64_t const *base, uint64x2_t offset) { return vldrdq_gather_shifted_offset_s64 (base, offset); } -/* { dg-final { scan-assembler "vldrd.u64" } } */ +/* +**foo1: +** ... +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) +** ... +*/ int64x2_t -foo1 (int64_t const * base, uint64x2_t offset) +foo1 (int64_t const *base, uint64x2_t offset) { return vldrdq_gather_shifted_offset (base, offset); } -/* { dg-final { scan-assembler "vldrd.u64" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c index 999735039c8..a466494974b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) +** ... +*/ uint64x2_t -foo (uint64_t const * base, uint64x2_t offset) +foo (uint64_t const *base, uint64x2_t offset) { return vldrdq_gather_shifted_offset_u64 (base, offset); } -/* { dg-final { scan-assembler "vldrd.u64" } } */ +/* +**foo1: +** ... +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) +** ... +*/ uint64x2_t -foo1 (uint64_t const * base, uint64x2_t offset) +foo1 (uint64_t const *base, uint64x2_t offset) { return vldrdq_gather_shifted_offset (base, offset); } -/* { dg-final { scan-assembler "vldrd.u64" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c index 77303a47a08..3555105d09e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) +** ... +*/ int64x2_t -foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p) +foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p) { return vldrdq_gather_shifted_offset_z_s64 (base, offset, p); } -/* { dg-final { scan-assembler "vldrdt.u64" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) +** ... +*/ int64x2_t -foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p) +foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p) { return vldrdq_gather_shifted_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrdt.u64" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c index 0273b242031..f7cfbfcddb3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) +** ... +*/ uint64x2_t -foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) +foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) { return vldrdq_gather_shifted_offset_z_u64 (base, offset, p); } -/* { dg-final { scan-assembler "vldrdt.u64" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) +** ... +*/ uint64x2_t -foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) +foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) { return vldrdq_gather_shifted_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrdt.u64" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c index 05bef418d82..87c746f4ad7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c @@ -1,14 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float16x8_t -foo (float16_t const * base) +foo (float16_t const *base) { return vldrhq_f16 (base); } -/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c index 525e54c72f5..287276e41f9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ float16x8_t -foo (float16_t const * base, uint16x8_t offset) +foo (float16_t const *base, uint16x8_t offset) { return vldrhq_gather_offset_f16 (base, offset); } -/* { dg-final { scan-assembler "vldrh.f16" } } */ +/* +**foo1: +** ... +** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ float16x8_t -foo1 (float16_t const * base, uint16x8_t offset) +foo1 (float16_t const *base, uint16x8_t offset) { return vldrhq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrh.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c index 47ef03445b4..e2493a62b3a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int16x8_t -foo (int16_t const * base, uint16x8_t offset) +foo (int16_t const *base, uint16x8_t offset) { return vldrhq_gather_offset_s16 (base, offset); } -/* { dg-final { scan-assembler "vldrh.u16" } } */ +/* +**foo1: +** ... +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int16x8_t -foo1 (int16_t const * base, uint16x8_t offset) +foo1 (int16_t const *base, uint16x8_t offset) { return vldrhq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrh.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c index 39379aaedd3..5d1e348cc86 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo (int16_t const * base, uint32x4_t offset) +foo (int16_t const *base, uint32x4_t offset) { return vldrhq_gather_offset_s32 (base, offset); } -/* { dg-final { scan-assembler "vldrh.s32" } } */ +/* +**foo1: +** ... +** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int16_t const * base, uint32x4_t offset) +foo1 (int16_t const *base, uint32x4_t offset) { return vldrhq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrh.s32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c index fa345e24b48..6d5f6f877dc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint16_t const * base, uint16x8_t offset) +foo (uint16_t const *base, uint16x8_t offset) { return vldrhq_gather_offset_u16 (base, offset); } -/* { dg-final { scan-assembler "vldrh.u16" } } */ +/* +**foo1: +** ... +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint16_t const * base, uint16x8_t offset) +foo1 (uint16_t const *base, uint16x8_t offset) { return vldrhq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrh.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c index b888660dc37..c39afbe6119 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint16_t const * base, uint32x4_t offset) +foo (uint16_t const *base, uint32x4_t offset) { return vldrhq_gather_offset_u32 (base, offset); } -/* { dg-final { scan-assembler "vldrh.u32" } } */ +/* +**foo1: +** ... +** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint16_t const * base, uint32x4_t offset) +foo1 (uint16_t const *base, uint32x4_t offset) { return vldrhq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrh.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c index 7ee84232f04..53c673e3644 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ float16x8_t -foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_offset_z_f16 (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ float16x8_t -foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c index 9b354fad50d..1e68a77824e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int16x8_t -foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_offset_z_s16 (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int16x8_t -foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c index 0e252291944..06c208f31c5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrhq_gather_offset_z_s32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrhq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.s32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c index 763e33d90bb..f50f026b00e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_offset_z_u16 (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c index 36baa252aa4..eff32dc6718 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrhq_gather_offset_z_u32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrhq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c index 843904a7041..f8468be41fa 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ float16x8_t -foo (float16_t const * base, uint16x8_t offset) +foo (float16_t const *base, uint16x8_t offset) { return vldrhq_gather_shifted_offset_f16 (base, offset); } -/* { dg-final { scan-assembler "vldrh.f16" } } */ +/* +**foo1: +** ... +** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ float16x8_t -foo1 (float16_t const * base, uint16x8_t offset) +foo1 (float16_t const *base, uint16x8_t offset) { return vldrhq_gather_shifted_offset (base, offset); } -/* { dg-final { scan-assembler "vldrh.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c index 6d013c835b5..ac2491ea143 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ int16x8_t -foo (int16_t const * base, uint16x8_t offset) +foo (int16_t const *base, uint16x8_t offset) { return vldrhq_gather_shifted_offset_s16 (base, offset); } -/* { dg-final { scan-assembler "vldrh.u16" } } */ +/* +**foo1: +** ... +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ int16x8_t -foo1 (int16_t const * base, uint16x8_t offset) +foo1 (int16_t const *base, uint16x8_t offset) { return vldrhq_gather_shifted_offset (base, offset); } -/* { dg-final { scan-assembler "vldrh.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c index 5ec8e8c1dc8..6919b3a3cc2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ int32x4_t -foo (int16_t const * base, uint32x4_t offset) +foo (int16_t const *base, uint32x4_t offset) { return vldrhq_gather_shifted_offset_s32 (base, offset); } -/* { dg-final { scan-assembler "vldrh.s32" } } */ +/* +**foo1: +** ... +** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int16_t const * base, uint32x4_t offset) +foo1 (int16_t const *base, uint32x4_t offset) { return vldrhq_gather_shifted_offset (base, offset); } -/* { dg-final { scan-assembler "vldrh.s32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c index fa5f3d04548..7e8fdf3799d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint16_t const * base, uint16x8_t offset) +foo (uint16_t const *base, uint16x8_t offset) { return vldrhq_gather_shifted_offset_u16 (base, offset); } -/* { dg-final { scan-assembler "vldrh.u16" } } */ +/* +**foo1: +** ... +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint16_t const * base, uint16x8_t offset) +foo1 (uint16_t const *base, uint16x8_t offset) { return vldrhq_gather_shifted_offset (base, offset); } -/* { dg-final { scan-assembler "vldrh.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c index 227b18d7864..de2d22d985d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint16_t const * base, uint32x4_t offset) +foo (uint16_t const *base, uint32x4_t offset) { return vldrhq_gather_shifted_offset_u32 (base, offset); } -/* { dg-final { scan-assembler "vldrh.u32" } } */ +/* +**foo1: +** ... +** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint16_t const * base, uint32x4_t offset) +foo1 (uint16_t const *base, uint32x4_t offset) { return vldrhq_gather_shifted_offset (base, offset); } -/* { dg-final { scan-assembler "vldrh.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c index cae37837c7e..a55ada003ed 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ float16x8_t -foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_shifted_offset_z_f16 (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ float16x8_t -foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_shifted_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c index 1aff290a6b0..ee57d77e3db 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ int16x8_t -foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_shifted_offset_z_s16 (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ int16x8_t -foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_shifted_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c index 92ee073adf9..9f8963f56bc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ int32x4_t -foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrhq_gather_shifted_offset_z_s32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrhq_gather_shifted_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.s32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c index 792510d3639..90be7020ac2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_shifted_offset_z_u16 (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) { return vldrhq_gather_shifted_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c index 8ae845418e8..0ff6d021b51 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrhq_gather_shifted_offset_z_u32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrhq_gather_shifted_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrht.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c index 7c977b6a699..107ce22856b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c @@ -1,14 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int16x8_t -foo (int16_t const * base) +foo (int16_t const *base) { return vldrhq_s16 (base); } -/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c index 229b52163fa..5cc864c38e4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c @@ -1,14 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int32x4_t -foo (int16_t const * base) +foo (int16_t const *base) { return vldrhq_s32 (base); } -/* { dg-final { scan-assembler-times "vldrh.s32" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c index 07f6d9e3944..12f807da03b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c @@ -1,14 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint16_t const * base) +foo (uint16_t const *base) { return vldrhq_u16 (base); } -/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c index cd24f01831f..5d4f34f9789 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c @@ -1,14 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint16_t const * base) +foo (uint16_t const *base) { return vldrhq_u32 (base); } -/* { dg-final { scan-assembler-times "vldrh.u32" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c index dd0fc9c7b73..582061bbab3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float16x8_t -foo (float16_t const * base, mve_pred16_t p) +foo (float16_t const *base, mve_pred16_t p) { return vldrhq_z_f16 (base, p); } -/* { dg-final { scan-assembler-times "vpst" 1 } } */ -/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */ +#ifdef __cplusplus +} +#endif + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c index 36d3458d95c..dc32460ccdd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int16x8_t -foo (int16_t const * base, mve_pred16_t p) +foo (int16_t const *base, mve_pred16_t p) { return vldrhq_z_s16 (base, p); } -/* { dg-final { scan-assembler-times "vpst" 1 } } */ -/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */ +#ifdef __cplusplus +} +#endif + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c index 9c67b479be7..15dd77cb36c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int32x4_t -foo (int16_t const * base, mve_pred16_t p) +foo (int16_t const *base, mve_pred16_t p) { return vldrhq_z_s32 (base, p); } -/* { dg-final { scan-assembler-times "vpst" 1 } } */ -/* { dg-final { scan-assembler-times "vldrht.s32" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c index 26354b5971a..91ab2caf1c6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint16x8_t -foo (uint16_t const * base, mve_pred16_t p) +foo (uint16_t const *base, mve_pred16_t p) { return vldrhq_z_u16 (base, p); } -/* { dg-final { scan-assembler-times "vpst" 1 } } */ -/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */ +#ifdef __cplusplus +} +#endif + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c index 948fe5ee5b4..1682ec1987a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint16_t const * base, mve_pred16_t p) +foo (uint16_t const *base, mve_pred16_t p) { return vldrhq_z_u32 (base, p); } -/* { dg-final { scan-assembler-times "vpst" 1 } } */ -/* { dg-final { scan-assembler-times "vldrht.u32" 1 } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c index 143079aa23f..9cf47332b38 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c @@ -1,14 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float32x4_t -foo (float32_t const * base) +foo (float32_t const *base) { return vldrwq_f32 (base); } -/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */ +#ifdef __cplusplus +} +#endif + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c index 5e0faaad8dd..c3f052efbc6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c @@ -1,13 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ float32x4_t foo (uint32x4_t addr) { - return vldrwq_gather_base_f32 (addr, 4); + return vldrwq_gather_base_f32 (addr, 0); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrw.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c index 8ca44199e3e..f2dbcfb9f6e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c @@ -1,13 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ int32x4_t foo (uint32x4_t addr) { - return vldrwq_gather_base_s32 (addr, 4); + return vldrwq_gather_base_s32 (addr, 0); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrw.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c index 3c3e90f1c0a..0926689805f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c @@ -1,13 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t addr) { - return vldrwq_gather_base_u32 (addr, 4); + return vldrwq_gather_base_u32 (addr, 0); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrw.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c index 8e2994f75d7..f9cd0a3ffe0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c @@ -1,16 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ float32x4_t -foo (uint32x4_t * addr) +foo (uint32x4_t *addr) { - return vldrwq_gather_base_wb_f32 (addr, 8); + return vldrwq_gather_base_wb_f32 (addr, 0); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c index e5054738b75..b8f16969a31 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c @@ -1,16 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ int32x4_t -foo (uint32x4_t * addr) +foo (uint32x4_t *addr) { - return vldrwq_gather_base_wb_s32 (addr, 8); + return vldrwq_gather_base_wb_s32 (addr, 0); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c index 7f39414143b..387d0115f46 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c @@ -1,16 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ uint32x4_t -foo (uint32x4_t * addr) +foo (uint32x4_t *addr) { - return vldrwq_gather_base_wb_u32 (addr, 8); + return vldrwq_gather_base_wb_u32 (addr, 0); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c index 1e57ca40739..bea7ecdee83 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c @@ -1,18 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ float32x4_t -foo (uint32x4_t * addr, mve_pred16_t p) +foo (uint32x4_t *addr, mve_pred16_t p) { - return vldrwq_gather_base_wb_z_f32 (addr, 8, p); + return vldrwq_gather_base_wb_z_f32 (addr, 0, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c index f8d77fdfd5b..4469ac14a0a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c @@ -1,18 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ int32x4_t -foo (uint32x4_t * addr, mve_pred16_t p) +foo (uint32x4_t *addr, mve_pred16_t p) { - return vldrwq_gather_base_wb_z_s32 (addr, 8, p); + return vldrwq_gather_base_wb_z_s32 (addr, 0, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c index 8a0e109c70c..9d4d81b3afe 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c @@ -1,18 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ uint32x4_t -foo (uint32x4_t * addr, mve_pred16_t p) +foo (uint32x4_t *addr, mve_pred16_t p) { - return vldrwq_gather_base_wb_z_u32 (addr, 8, p); + return vldrwq_gather_base_wb_z_u32 (addr, 0, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c index 81aac523728..905000a31a8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ float32x4_t foo (uint32x4_t addr, mve_pred16_t p) { - return vldrwq_gather_base_z_f32 (addr, 4, p); + return vldrwq_gather_base_z_f32 (addr, 0, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c index fec49bbde06..3ee6a219b80 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ int32x4_t foo (uint32x4_t addr, mve_pred16_t p) { - return vldrwq_gather_base_z_s32 (addr, 4, p); + return vldrwq_gather_base_z_s32 (addr, 0, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c index b64a11d6620..488adf58b78 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t addr, mve_pred16_t p) { - return vldrwq_gather_base_z_u32 (addr, 4, p); + return vldrwq_gather_base_z_u32 (addr, 0, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c index 6a4ea041137..a513452a12d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ float32x4_t -foo (float32_t const * base, uint32x4_t offset) +foo (float32_t const *base, uint32x4_t offset) { return vldrwq_gather_offset_f32 (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +/* +**foo1: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ float32x4_t -foo1 (float32_t const * base, uint32x4_t offset) +foo1 (float32_t const *base, uint32x4_t offset) { return vldrwq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c index ee15fa4a0b0..57ad6583153 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo (int32_t const * base, uint32x4_t offset) +foo (int32_t const *base, uint32x4_t offset) { return vldrwq_gather_offset_s32 (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +/* +**foo1: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int32_t const * base, uint32x4_t offset) +foo1 (int32_t const *base, uint32x4_t offset) { return vldrwq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c index d344779058f..30fc36c6f97 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint32_t const * base, uint32x4_t offset) +foo (uint32_t const *base, uint32x4_t offset) { return vldrwq_gather_offset_u32 (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +/* +**foo1: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint32_t const * base, uint32x4_t offset) +foo1 (uint32_t const *base, uint32x4_t offset) { return vldrwq_gather_offset (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c index 93253119418..1f84edcdb8e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ float32x4_t -foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_offset_z_f32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ float32x4_t -foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c index 4537427bef3..3fe5a986cc3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_offset_z_s32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c index e59c4c996bf..087e5d0ce1e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_offset_z_u32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c index 1ba2cb0ccde..bed16f5fa72 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ float32x4_t -foo (float32_t const * base, uint32x4_t offset) +foo (float32_t const *base, uint32x4_t offset) { return vldrwq_gather_shifted_offset_f32 (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +/* +**foo1: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ float32x4_t -foo1 (float32_t const * base, uint32x4_t offset) +foo1 (float32_t const *base, uint32x4_t offset) { return vldrwq_gather_shifted_offset (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c index 39d976bb676..e6c589020f3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ int32x4_t -foo (int32_t const * base, uint32x4_t offset) +foo (int32_t const *base, uint32x4_t offset) { return vldrwq_gather_shifted_offset_s32 (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +/* +**foo1: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int32_t const * base, uint32x4_t offset) +foo1 (int32_t const *base, uint32x4_t offset) { return vldrwq_gather_shifted_offset (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c index 971f482dfff..8e287da0dbf 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint32_t const * base, uint32x4_t offset) +foo (uint32_t const *base, uint32x4_t offset) { return vldrwq_gather_shifted_offset_u32 (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +/* +**foo1: +** ... +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint32_t const * base, uint32x4_t offset) +foo1 (uint32_t const *base, uint32x4_t offset) { return vldrwq_gather_shifted_offset (base, offset); } -/* { dg-final { scan-assembler "vldrw.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c index e4110cd50aa..f69d67fd2aa 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ float32x4_t -foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_shifted_offset_z_f32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ float32x4_t -foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_shifted_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c index 71dd8a757ce..3aff6de03b6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ int32x4_t -foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_shifted_offset_z_s32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ int32x4_t -foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_shifted_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c index f95d6f0f708..ed8873d0c53 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_shifted_offset_z_u32 (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) +foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) { return vldrwq_gather_shifted_offset_z (base, offset, p); } -/* { dg-final { scan-assembler "vldrwt.u32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c index 860dd324d25..87c3ac9f9d2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c @@ -1,14 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int32x4_t -foo (int32_t const * base) +foo (int32_t const *base) { return vldrwq_s32 (base); } -/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */ +#ifdef __cplusplus +} +#endif + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c index 513ed49fb6e..5b560c534a1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c @@ -1,14 +1,28 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint32_t const * base) +foo (uint32_t const *base) { return vldrwq_u32 (base); } -/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */ +#ifdef __cplusplus +} +#endif + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c index 3e0a6a60bcf..14a61fcfbd4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ float32x4_t -foo (float32_t const * base, mve_pred16_t p) +foo (float32_t const *base, mve_pred16_t p) { return vldrwq_z_f32 (base, p); } -/* { dg-final { scan-assembler-times "vpst" 1 } } */ -/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */ +#ifdef __cplusplus +} +#endif + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c index 82b914885b5..5c90707becc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ int32x4_t -foo (int32_t const * base, mve_pred16_t p) +foo (int32_t const *base, mve_pred16_t p) { return vldrwq_z_s32 (base, p); } -/* { dg-final { scan-assembler-times "vpst" 1 } } */ -/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */ +#ifdef __cplusplus +} +#endif + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c index 6a66e167881..16b50335fe7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c @@ -1,15 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ uint32x4_t -foo (uint32_t const * base, mve_pred16_t p) +foo (uint32_t const *base, mve_pred16_t p) { return vldrwq_z_u32 (base, p); } -/* { dg-final { scan-assembler-times "vpst" 1 } } */ -/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */ +#ifdef __cplusplus +} +#endif + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c index 64650e26bcb..5180667658e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (float16_t * addr, float16x8x2_t value) +foo (float16_t *addr, float16x8x2_t value) { - vst2q_f16 (addr, value); + return vst2q_f16 (addr, value); } -/* { dg-final { scan-assembler "vst20.16" } } */ -/* { dg-final { scan-assembler "vst21.16" } } */ +/* +**foo1: +** ... +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (float16_t * addr, float16x8x2_t value) +foo1 (float16_t *addr, float16x8x2_t value) { - vst2q (addr, value); + return vst2q (addr, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vst20.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c index 8840afb867d..3e6f5b0ed75 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (float32_t * addr, float32x4x2_t value) +foo (float32_t *addr, float32x4x2_t value) { - vst2q_f32 (addr, value); + return vst2q_f32 (addr, value); } -/* { dg-final { scan-assembler "vst20.32" } } */ -/* { dg-final { scan-assembler "vst21.32" } } */ +/* +**foo1: +** ... +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (float32_t * addr, float32x4x2_t value) +foo1 (float32_t *addr, float32x4x2_t value) { - vst2q (addr, value); + return vst2q (addr, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vst20.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c index 15182c5eee0..1c939317779 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int16_t * addr, int16x8x2_t value) +foo (int16_t *addr, int16x8x2_t value) { - vst2q_s16 (addr, value); + return vst2q_s16 (addr, value); } -/* { dg-final { scan-assembler "vst20.16" } } */ -/* { dg-final { scan-assembler "vst21.16" } } */ +/* +**foo1: +** ... +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int16_t * addr, int16x8x2_t value) +foo1 (int16_t *addr, int16x8x2_t value) { - vst2q (addr, value); + return vst2q (addr, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vst20.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c index 11c92463ae4..28c8e078942 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int32_t * addr, int32x4x2_t value) +foo (int32_t *addr, int32x4x2_t value) { - vst2q_s32 (addr, value); + return vst2q_s32 (addr, value); } -/* { dg-final { scan-assembler "vst20.32" } } */ -/* { dg-final { scan-assembler "vst21.32" } } */ +/* +**foo1: +** ... +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int32_t * addr, int32x4x2_t value) +foo1 (int32_t *addr, int32x4x2_t value) { - vst2q (addr, value); + return vst2q (addr, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vst20.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c index 90257ae5dae..e882c01bd63 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int8_t * addr, int8x16x2_t value) +foo (int8_t *addr, int8x16x2_t value) { - vst2q_s8 (addr, value); + return vst2q_s8 (addr, value); } -/* { dg-final { scan-assembler "vst20.8" } } */ -/* { dg-final { scan-assembler "vst21.8" } } */ +/* +**foo1: +** ... +** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int8_t * addr, int8x16x2_t value) +foo1 (int8_t *addr, int8x16x2_t value) { - vst2q (addr, value); + return vst2q (addr, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vst20.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c index a8a7c49757a..0cfbd6b9902 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint16_t * addr, uint16x8x2_t value) +foo (uint16_t *addr, uint16x8x2_t value) { - vst2q_u16 (addr, value); + return vst2q_u16 (addr, value); } -/* { dg-final { scan-assembler "vst20.16" } } */ -/* { dg-final { scan-assembler "vst21.16" } } */ +/* +**foo1: +** ... +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * addr, uint16x8x2_t value) +foo1 (uint16_t *addr, uint16x8x2_t value) { - vst2q (addr, value); + return vst2q (addr, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vst20.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c index b5d78180995..ea46a5969d0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint32_t * addr, uint32x4x2_t value) +foo (uint32_t *addr, uint32x4x2_t value) { - vst2q_u32 (addr, value); + return vst2q_u32 (addr, value); } -/* { dg-final { scan-assembler "vst20.32" } } */ -/* { dg-final { scan-assembler "vst21.32" } } */ +/* +**foo1: +** ... +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * addr, uint32x4x2_t value) +foo1 (uint32_t *addr, uint32x4x2_t value) { - vst2q (addr, value); + return vst2q (addr, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vst20.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c index 4e7d6fea7ed..895c2ccf425 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint8_t * addr, uint8x16x2_t value) +foo (uint8_t *addr, uint8x16x2_t value) { - vst2q_u8 (addr, value); + return vst2q_u8 (addr, value); } -/* { dg-final { scan-assembler "vst20.8" } } */ -/* { dg-final { scan-assembler "vst21.8" } } */ +/* +**foo1: +** ... +** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * addr, uint8x16x2_t value) +foo1 (uint8_t *addr, uint8x16x2_t value) { - vst2q (addr, value); + return vst2q (addr, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vst20.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c index 0da66894e2c..94066089f58 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c @@ -1,37 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo (float16_t * addr, float16x8x4_t value) +foo (float16_t *addr, float16x8x4_t value) { - vst4q_f16 (addr, value); + return vst4q_f16 (addr, value); } -/* { dg-final { scan-assembler "vst40.16" } } */ -/* { dg-final { scan-assembler "vst41.16" } } */ -/* { dg-final { scan-assembler "vst42.16" } } */ -/* { dg-final { scan-assembler "vst43.16" } } */ +/* +**foo1: +** ... +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo1 (float16_t * addr, float16x8x4_t value) +foo1 (float16_t *addr, float16x8x4_t value) { - vst4q (addr, value); + return vst4q (addr, value); } -/* { dg-final { scan-assembler "vst40.16" } } */ -/* { dg-final { scan-assembler "vst41.16" } } */ -/* { dg-final { scan-assembler "vst42.16" } } */ -/* { dg-final { scan-assembler "vst43.16" } } */ - -void -foo2 (float16_t * addr, float16x8x4_t value) -{ - vst4q_f16 (addr, value); - addr += 32; - vst4q_f16 (addr, value); +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c index c1614bd10fc..0150ba7ca56 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c @@ -1,37 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo (float32_t * addr, float32x4x4_t value) +foo (float32_t *addr, float32x4x4_t value) { - vst4q_f32 (addr, value); + return vst4q_f32 (addr, value); } -/* { dg-final { scan-assembler "vst40.32" } } */ -/* { dg-final { scan-assembler "vst41.32" } } */ -/* { dg-final { scan-assembler "vst42.32" } } */ -/* { dg-final { scan-assembler "vst43.32" } } */ +/* +**foo1: +** ... +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo1 (float32_t * addr, float32x4x4_t value) +foo1 (float32_t *addr, float32x4x4_t value) { - vst4q (addr, value); + return vst4q (addr, value); } -/* { dg-final { scan-assembler "vst40.32" } } */ -/* { dg-final { scan-assembler "vst41.32" } } */ -/* { dg-final { scan-assembler "vst42.32" } } */ -/* { dg-final { scan-assembler "vst43.32" } } */ - -void -foo2 (float32_t * addr, float32x4x4_t value) -{ - vst4q_f32 (addr, value); - addr += 16; - vst4q_f32 (addr, value); +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c index e1250449bee..8c9df15b3c7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c @@ -1,37 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo (int16_t * addr, int16x8x4_t value) +foo (int16_t *addr, int16x8x4_t value) { - vst4q_s16 (addr, value); + return vst4q_s16 (addr, value); } -/* { dg-final { scan-assembler "vst40.16" } } */ -/* { dg-final { scan-assembler "vst41.16" } } */ -/* { dg-final { scan-assembler "vst42.16" } } */ -/* { dg-final { scan-assembler "vst43.16" } } */ +/* +**foo1: +** ... +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo1 (int16_t * addr, int16x8x4_t value) +foo1 (int16_t *addr, int16x8x4_t value) { - vst4q (addr, value); + return vst4q (addr, value); } -/* { dg-final { scan-assembler "vst40.16" } } */ -/* { dg-final { scan-assembler "vst41.16" } } */ -/* { dg-final { scan-assembler "vst42.16" } } */ -/* { dg-final { scan-assembler "vst43.16" } } */ - -void -foo2 (int16_t * addr, int16x8x4_t value) -{ - vst4q_s16 (addr, value); - addr += 32; - vst4q_s16 (addr, value); +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c index e6e1272744e..1a1a9797360 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c @@ -1,37 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo (int32_t * addr, int32x4x4_t value) +foo (int32_t *addr, int32x4x4_t value) { - vst4q_s32 (addr, value); + return vst4q_s32 (addr, value); } -/* { dg-final { scan-assembler "vst40.32" } } */ -/* { dg-final { scan-assembler "vst41.32" } } */ -/* { dg-final { scan-assembler "vst42.32" } } */ -/* { dg-final { scan-assembler "vst43.32" } } */ +/* +**foo1: +** ... +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo1 (int32_t * addr, int32x4x4_t value) +foo1 (int32_t *addr, int32x4x4_t value) { - vst4q (addr, value); + return vst4q (addr, value); } -/* { dg-final { scan-assembler "vst40.32" } } */ -/* { dg-final { scan-assembler "vst41.32" } } */ -/* { dg-final { scan-assembler "vst42.32" } } */ -/* { dg-final { scan-assembler "vst43.32" } } */ - -void -foo2 (int32_t * addr, int32x4x4_t value) -{ - vst4q_s32 (addr, value); - addr += 16; - vst4q_s32 (addr, value); +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c index 16eb488ff99..d23032a73bc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c @@ -1,37 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo (int8_t * addr, int8x16x4_t value) +foo (int8_t *addr, int8x16x4_t value) { - vst4q_s8 (addr, value); + return vst4q_s8 (addr, value); } -/* { dg-final { scan-assembler "vst40.8" } } */ -/* { dg-final { scan-assembler "vst41.8" } } */ -/* { dg-final { scan-assembler "vst42.8" } } */ -/* { dg-final { scan-assembler "vst43.8" } } */ +/* +**foo1: +** ... +** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo1 (int8_t * addr, int8x16x4_t value) +foo1 (int8_t *addr, int8x16x4_t value) { - vst4q (addr, value); + return vst4q (addr, value); } -/* { dg-final { scan-assembler "vst40.8" } } */ -/* { dg-final { scan-assembler "vst41.8" } } */ -/* { dg-final { scan-assembler "vst42.8" } } */ -/* { dg-final { scan-assembler "vst43.8" } } */ - -void -foo2 (int8_t * addr, int8x16x4_t value) -{ - vst4q_s8 (addr, value); - addr += 16*4; - vst4q_s8 (addr, value); +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c index afd60306d0d..76cc4311e1b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c @@ -1,37 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo (uint16_t * addr, uint16x8x4_t value) +foo (uint16_t *addr, uint16x8x4_t value) { - vst4q_u16 (addr, value); + return vst4q_u16 (addr, value); } -/* { dg-final { scan-assembler "vst40.16" } } */ -/* { dg-final { scan-assembler "vst41.16" } } */ -/* { dg-final { scan-assembler "vst42.16" } } */ -/* { dg-final { scan-assembler "vst43.16" } } */ +/* +**foo1: +** ... +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo1 (uint16_t * addr, uint16x8x4_t value) +foo1 (uint16_t *addr, uint16x8x4_t value) { - vst4q (addr, value); + return vst4q (addr, value); } -/* { dg-final { scan-assembler "vst40.16" } } */ -/* { dg-final { scan-assembler "vst41.16" } } */ -/* { dg-final { scan-assembler "vst42.16" } } */ -/* { dg-final { scan-assembler "vst43.16" } } */ - -void -foo2 (uint16_t * addr, uint16x8x4_t value) -{ - vst4q_u16 (addr, value); - addr += 32; - vst4q_u16 (addr, value); +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c index 755dd689dff..e5f62858eee 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c @@ -1,37 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo (uint32_t * addr, uint32x4x4_t value) +foo (uint32_t *addr, uint32x4x4_t value) { - vst4q_u32 (addr, value); + return vst4q_u32 (addr, value); } -/* { dg-final { scan-assembler "vst40.32" } } */ -/* { dg-final { scan-assembler "vst41.32" } } */ -/* { dg-final { scan-assembler "vst42.32" } } */ -/* { dg-final { scan-assembler "vst43.32" } } */ +/* +**foo1: +** ... +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo1 (uint32_t * addr, uint32x4x4_t value) +foo1 (uint32_t *addr, uint32x4x4_t value) { - vst4q (addr, value); + return vst4q (addr, value); } -/* { dg-final { scan-assembler "vst40.32" } } */ -/* { dg-final { scan-assembler "vst41.32" } } */ -/* { dg-final { scan-assembler "vst42.32" } } */ -/* { dg-final { scan-assembler "vst43.32" } } */ - -void -foo2 (uint32_t * addr, uint32x4x4_t value) -{ - vst4q_u32 (addr, value); - addr += 16; - vst4q_u32 (addr, value); +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c index 0b28451df55..923cd0d3b10 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c @@ -1,37 +1,47 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo (uint8_t * addr, uint8x16x4_t value) +foo (uint8_t *addr, uint8x16x4_t value) { - vst4q_u8 (addr, value); + return vst4q_u8 (addr, value); } -/* { dg-final { scan-assembler "vst40.8" } } */ -/* { dg-final { scan-assembler "vst41.8" } } */ -/* { dg-final { scan-assembler "vst42.8" } } */ -/* { dg-final { scan-assembler "vst43.8" } } */ +/* +**foo1: +** ... +** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] +** ... +*/ void -foo1 (uint8_t * addr, uint8x16x4_t value) +foo1 (uint8_t *addr, uint8x16x4_t value) { - vst4q (addr, value); + return vst4q (addr, value); } -/* { dg-final { scan-assembler "vst40.8" } } */ -/* { dg-final { scan-assembler "vst41.8" } } */ -/* { dg-final { scan-assembler "vst42.8" } } */ -/* { dg-final { scan-assembler "vst43.8" } } */ - -void -foo2 (uint8_t * addr, uint8x16x4_t value) -{ - vst4q_u8 (addr, value); - addr += 16*4; - vst4q_u8 (addr, value); +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c index ad74d8aa2e9..19804443e01 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int8_t * addr, int16x8_t value, mve_pred16_t p) +foo (int8_t *base, int16x8_t value, mve_pred16_t p) { - vstrbq_p_s16 (addr, value, p); + return vstrbq_p_s16 (base, value, p); } -/* { dg-final { scan-assembler "vstrbt.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int8_t * addr, int16x8_t value, mve_pred16_t p) +foo1 (int8_t *base, int16x8_t value, mve_pred16_t p) { - vstrbq_p (addr, value, p); + return vstrbq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c index 46fd4549ffb..26be212770b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int8_t * addr, int32x4_t value, mve_pred16_t p) +foo (int8_t *base, int32x4_t value, mve_pred16_t p) { - vstrbq_p_s32 (addr, value, p); + return vstrbq_p_s32 (base, value, p); } -/* { dg-final { scan-assembler "vstrbt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int8_t * addr, int32x4_t value, mve_pred16_t p) +foo1 (int8_t *base, int32x4_t value, mve_pred16_t p) { - vstrbq_p (addr, value, p); + return vstrbq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c index 8e70b9eb098..a0d08772a50 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int8_t * addr, int8x16_t value, mve_pred16_t p) +foo (int8_t *base, int8x16_t value, mve_pred16_t p) { - vstrbq_p_s8 (addr, value, p); + return vstrbq_p_s8 (base, value, p); } -/* { dg-final { scan-assembler "vstrbt.8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p) +foo1 (int8_t *base, int8x16_t value, mve_pred16_t p) { - vstrbq_p (addr, value, p); + return vstrbq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c index 180f9033edd..bc02c59887a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint8_t * addr, uint16x8_t value, mve_pred16_t p) +foo (uint8_t *base, uint16x8_t value, mve_pred16_t p) { - vstrbq_p_u16 (addr, value, p); + return vstrbq_p_u16 (base, value, p); } -/* { dg-final { scan-assembler "vstrbt.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * addr, uint16x8_t value, mve_pred16_t p) +foo1 (uint8_t *base, uint16x8_t value, mve_pred16_t p) { - vstrbq_p (addr, value, p); + return vstrbq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c index 1b944fc9ffc..1215d5f0978 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint8_t * addr, uint32x4_t value, mve_pred16_t p) +foo (uint8_t *base, uint32x4_t value, mve_pred16_t p) { - vstrbq_p_u32 (addr, value, p); + return vstrbq_p_u32 (base, value, p); } -/* { dg-final { scan-assembler "vstrbt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * addr, uint32x4_t value, mve_pred16_t p) +foo1 (uint8_t *base, uint32x4_t value, mve_pred16_t p) { - vstrbq_p (addr, value, p); + return vstrbq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c index 7e73cbff84e..a88234e411d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p) +foo (uint8_t *base, uint8x16_t value, mve_pred16_t p) { - vstrbq_p_u8 (addr, value, p); + return vstrbq_p_u8 (base, value, p); } -/* { dg-final { scan-assembler "vstrbt.8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p) +foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p) { - vstrbq_p (addr, value, p); + return vstrbq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c index 4d12bc2cd19..1e88d3aa600 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int8_t * addr, int16x8_t value) +foo (int8_t *base, int16x8_t value) { - vstrbq_s16 (addr, value); + return vstrbq_s16 (base, value); } -/* { dg-final { scan-assembler "vstrb.16" } } */ +/* +**foo1: +** ... +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int8_t * addr, int16x8_t value) +foo1 (int8_t *base, int16x8_t value) { - vstrbq (addr, value); + return vstrbq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c index 750413f35ae..12764bf3041 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int8_t * addr, int32x4_t value) +foo (int8_t *base, int32x4_t value) { - vstrbq_s32 (addr, value); + return vstrbq_s32 (base, value); } -/* { dg-final { scan-assembler "vstrb.32" } } */ +/* +**foo1: +** ... +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int8_t * addr, int32x4_t value) +foo1 (int8_t *base, int32x4_t value) { - vstrbq (addr, value); + return vstrbq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c index 7ffb2c51976..05a9e5c42ce 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int8_t * addr, int8x16_t value) +foo (int8_t *base, int8x16_t value) { - vstrbq_s8 (addr, value); + return vstrbq_s8 (base, value); } -/* { dg-final { scan-assembler "vstrb.8" } } */ +/* +**foo1: +** ... +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int8_t * addr, int8x16_t value) +foo1 (int8_t *base, int8x16_t value) { - vstrbq (addr, value); + return vstrbq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c index f59fa349cc0..052c3f85b75 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +foo (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p_s16 (base, offset, value, p); + return vstrbq_scatter_offset_p_s16 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrbt.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +foo1 (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p (base, offset, value, p); + return vstrbq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c index 737c1008976..57410e46a8a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p_s32 (base, offset, value, p); + return vstrbq_scatter_offset_p_s32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrbt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo1 (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p (base, offset, value, p); + return vstrbq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c index 8b2d06807b4..c3cdefdf078 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) +foo (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p_s8 (base, offset, value, p); + return vstrbq_scatter_offset_p_s8 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrbt.8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) +foo1 (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p (base, offset, value, p); + return vstrbq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c index 0adccaac39c..0868cc2248b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +foo (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p_u16 (base, offset, value, p); + return vstrbq_scatter_offset_p_u16 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrbt.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p (base, offset, value, p); + return vstrbq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c index 308119294df..9d769941569 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p_u32 (base, offset, value, p); + return vstrbq_scatter_offset_p_u32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrbt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p (base, offset, value, p); + return vstrbq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c index 28b2ca4b83a..4586535d600 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) +foo (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p_u8 (base, offset, value, p); + return vstrbq_scatter_offset_p_u8 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrbt.8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) +foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) { - vstrbq_scatter_offset_p (base, offset, value, p); + return vstrbq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrbt.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c index e6cf1828b33..179b96f4973 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int8_t * base, uint16x8_t offset, int16x8_t value) +foo (int8_t *base, uint16x8_t offset, int16x8_t value) { - vstrbq_scatter_offset_s16 (base, offset, value); + return vstrbq_scatter_offset_s16 (base, offset, value); } -/* { dg-final { scan-assembler "vstrb.16" } } */ +/* +**foo1: +** ... +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int8_t * base, uint16x8_t offset, int16x8_t value) +foo1 (int8_t *base, uint16x8_t offset, int16x8_t value) { - vstrbq_scatter_offset (base, offset, value); + return vstrbq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c index 052e02a7cf9..e7b7767c9f2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int8_t * base, uint32x4_t offset, int32x4_t value) +foo (int8_t *base, uint32x4_t offset, int32x4_t value) { - vstrbq_scatter_offset_s32 (base, offset, value); + return vstrbq_scatter_offset_s32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrb.32" } } */ +/* +**foo1: +** ... +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int8_t * base, uint32x4_t offset, int32x4_t value) +foo1 (int8_t *base, uint32x4_t offset, int32x4_t value) { - vstrbq_scatter_offset (base, offset, value); + return vstrbq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c index 523f318e73c..f47bdd1a630 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int8_t * base, uint8x16_t offset, int8x16_t value) +foo (int8_t *base, uint8x16_t offset, int8x16_t value) { - vstrbq_scatter_offset_s8 (base, offset, value); + return vstrbq_scatter_offset_s8 (base, offset, value); } -/* { dg-final { scan-assembler "vstrb.8" } } */ +/* +**foo1: +** ... +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int8_t * base, uint8x16_t offset, int8x16_t value) +foo1 (int8_t *base, uint8x16_t offset, int8x16_t value) { - vstrbq_scatter_offset (base, offset, value); + return vstrbq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c index 49d4d31ad21..90e8cf351f9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint8_t * base, uint16x8_t offset, uint16x8_t value) +foo (uint8_t *base, uint16x8_t offset, uint16x8_t value) { - vstrbq_scatter_offset_u16 (base, offset, value); + return vstrbq_scatter_offset_u16 (base, offset, value); } -/* { dg-final { scan-assembler "vstrb.16" } } */ +/* +**foo1: +** ... +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value) +foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value) { - vstrbq_scatter_offset (base, offset, value); + return vstrbq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c index 0012852298c..e5449aa0942 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint8_t * base, uint32x4_t offset, uint32x4_t value) +foo (uint8_t *base, uint32x4_t offset, uint32x4_t value) { - vstrbq_scatter_offset_u32 (base, offset, value); + return vstrbq_scatter_offset_u32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrb.32" } } */ +/* +**foo1: +** ... +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value) +foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value) { - vstrbq_scatter_offset (base, offset, value); + return vstrbq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c index e54422a1afe..06c8c45e877 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint8_t * base, uint8x16_t offset, uint8x16_t value) +foo (uint8_t *base, uint8x16_t offset, uint8x16_t value) { - vstrbq_scatter_offset_u8 (base, offset, value); + return vstrbq_scatter_offset_u8 (base, offset, value); } -/* { dg-final { scan-assembler "vstrb.8" } } */ +/* +**foo1: +** ... +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value) +foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value) { - vstrbq_scatter_offset (base, offset, value); + return vstrbq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c index 9fa9d18c6a1..0b350e2491b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint8_t * addr, uint16x8_t value) +foo (uint8_t *base, uint16x8_t value) { - vstrbq_u16 (addr, value); + return vstrbq_u16 (base, value); } -/* { dg-final { scan-assembler "vstrb.16" } } */ +/* +**foo1: +** ... +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * addr, uint16x8_t value) +foo1 (uint8_t *base, uint16x8_t value) { - vstrbq (addr, value); + return vstrbq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c index e535aa275ef..2f809356420 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint8_t * addr, uint32x4_t value) +foo (uint8_t *base, uint32x4_t value) { - vstrbq_u32 (addr, value); + return vstrbq_u32 (base, value); } -/* { dg-final { scan-assembler "vstrb.32" } } */ +/* +**foo1: +** ... +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * addr, uint32x4_t value) +foo1 (uint8_t *base, uint32x4_t value) { - vstrbq (addr, value); + return vstrbq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c index 93771aabcbd..deeea98dda5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint8_t * addr, uint8x16_t value) +foo (uint8_t *base, uint8x16_t value) { - vstrbq_u8 (addr, value); + return vstrbq_u8 (base, value); } -/* { dg-final { scan-assembler "vstrb.8" } } */ +/* +**foo1: +** ... +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint8_t * addr, uint8x16_t value) +foo1 (uint8_t *base, uint8x16_t value) { - vstrbq (addr, value); + return vstrbq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrb.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c index 74e2617c380..a41217b24f2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (float16_t * addr, float16x8_t value) +foo (float16_t *base, float16x8_t value) { - vstrhq_f16 (addr, value); + return vstrhq_f16 (base, value); } -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* +**foo1: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (float16_t * addr, float16x8_t value) +foo1 (float16_t *base, float16x8_t value) { - vstrhq (addr, value); + return vstrhq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c index 227da4f10aa..8398a60023d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (float16_t * addr, float16x8_t value, mve_pred16_t p) +foo (float16_t *base, float16x8_t value, mve_pred16_t p) { - vstrhq_p_f16 (addr, value, p); + return vstrhq_p_f16 (base, value, p); } -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p) +foo1 (float16_t *base, float16x8_t value, mve_pred16_t p) { - vstrhq_p (addr, value, p); + return vstrhq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c index f3ba71f0ce1..ee1026801be 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int16_t * addr, int16x8_t value, mve_pred16_t p) +foo (int16_t *base, int16x8_t value, mve_pred16_t p) { - vstrhq_p_s16 (addr, value, p); + return vstrhq_p_s16 (base, value, p); } -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p) +foo1 (int16_t *base, int16x8_t value, mve_pred16_t p) { - vstrhq_p (addr, value, p); + return vstrhq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c index dab646706ce..b8490209644 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int16_t * addr, int32x4_t value, mve_pred16_t p) +foo (int16_t *base, int32x4_t value, mve_pred16_t p) { - vstrhq_p_s32 (addr, value, p); + return vstrhq_p_s32 (base, value, p); } -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int16_t * addr, int32x4_t value, mve_pred16_t p) +foo1 (int16_t *base, int32x4_t value, mve_pred16_t p) { - vstrhq_p (addr, value, p); + return vstrhq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c index e575c70cc44..59fb73cef19 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p) +foo (uint16_t *base, uint16x8_t value, mve_pred16_t p) { - vstrhq_p_u16 (addr, value, p); + return vstrhq_p_u16 (base, value, p); } -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p) +foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p) { - vstrhq_p (addr, value, p); + return vstrhq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c index e863e284c3c..ed66db7f8ce 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint16_t * addr, uint32x4_t value, mve_pred16_t p) +foo (uint16_t *base, uint32x4_t value, mve_pred16_t p) { - vstrhq_p_u32 (addr, value, p); + return vstrhq_p_u32 (base, value, p); } -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * addr, uint32x4_t value, mve_pred16_t p) +foo1 (uint16_t *base, uint32x4_t value, mve_pred16_t p) { - vstrhq_p (addr, value, p); + return vstrhq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c index 5e47fb4e1a6..972d733c5bd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int16_t * addr, int16x8_t value) +foo (int16_t *base, int16x8_t value) { - vstrhq_s16 (addr, value); + return vstrhq_s16 (base, value); } -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* +**foo1: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int16_t * addr, int16x8_t value) +foo1 (int16_t *base, int16x8_t value) { - vstrhq (addr, value); + return vstrhq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c index 73e01c9acfb..f260c61c3a8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int16_t * addr, int32x4_t value) +foo (int16_t *base, int32x4_t value) { - vstrhq_s32 (addr, value); + return vstrhq_s32 (base, value); } -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* +**foo1: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int16_t * addr, int32x4_t value) +foo1 (int16_t *base, int32x4_t value) { - vstrhq (addr, value); + return vstrhq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c index d29bd08ad0a..794d75e76ac 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (float16_t * base, uint16x8_t offset, float16x8_t value) +foo (float16_t *base, uint16x8_t offset, float16x8_t value) { - vstrhq_scatter_offset_f16 (base, offset, value); + return vstrhq_scatter_offset_f16 (base, offset, value); } -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* +**foo1: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (float16_t * base, uint16x8_t offset, float16x8_t value) +foo1 (float16_t *base, uint16x8_t offset, float16x8_t value) { - vstrhq_scatter_offset (base, offset, value); + return vstrhq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c index 79d9827b378..1fd5a0773dc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) +foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) { - vstrhq_scatter_offset_p_f16 (base, offset, value, p); + return vstrhq_scatter_offset_p_f16 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) +foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) { - vstrhq_scatter_offset_p (base, offset, value, p); + return vstrhq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c index 1b401d4c5b7..34c44a90541 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) { - vstrhq_scatter_offset_p_s16 (base, offset, value, p); + return vstrhq_scatter_offset_p_s16 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) { - vstrhq_scatter_offset_p (base, offset, value, p); + return vstrhq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c index afb325b9789..2a84b28a3f5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrhq_scatter_offset_p_s32 (base, offset, value, p); + return vstrhq_scatter_offset_p_s32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrhq_scatter_offset_p (base, offset, value, p); + return vstrhq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c index 73bee831282..f1c875657ce 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) { - vstrhq_scatter_offset_p_u16 (base, offset, value, p); + return vstrhq_scatter_offset_p_u16 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) { - vstrhq_scatter_offset_p (base, offset, value, p); + return vstrhq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c index bae7c2d14c2..913fd8d5591 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrhq_scatter_offset_p_u32 (base, offset, value, p); + return vstrhq_scatter_offset_p_u32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrhq_scatter_offset_p (base, offset, value, p); + return vstrhq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c index bf3c03a85c6..b322d0fa02e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int16_t * base, uint16x8_t offset, int16x8_t value) +foo (int16_t *base, uint16x8_t offset, int16x8_t value) { - vstrhq_scatter_offset_s16 (base, offset, value); + return vstrhq_scatter_offset_s16 (base, offset, value); } -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* +**foo1: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int16_t * base, uint16x8_t offset, int16x8_t value) +foo1 (int16_t *base, uint16x8_t offset, int16x8_t value) { - vstrhq_scatter_offset (base, offset, value); + return vstrhq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c index 0591ab55c07..49fcc3a382b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int16_t * base, uint32x4_t offset, int32x4_t value) +foo (int16_t *base, uint32x4_t offset, int32x4_t value) { - vstrhq_scatter_offset_s32 (base, offset, value); + return vstrhq_scatter_offset_s32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* +**foo1: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int16_t * base, uint32x4_t offset, int32x4_t value) +foo1 (int16_t *base, uint32x4_t offset, int32x4_t value) { - vstrhq_scatter_offset (base, offset, value); + return vstrhq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c index 0a2fa1f410e..b5de540a74c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint16_t * base, uint16x8_t offset, uint16x8_t value) +foo (uint16_t *base, uint16x8_t offset, uint16x8_t value) { - vstrhq_scatter_offset_u16 (base, offset, value); + return vstrhq_scatter_offset_u16 (base, offset, value); } -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* +**foo1: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value) +foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value) { - vstrhq_scatter_offset (base, offset, value); + return vstrhq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c index 809a44dee16..7808f25d4a4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint16_t * base, uint32x4_t offset, uint32x4_t value) +foo (uint16_t *base, uint32x4_t offset, uint32x4_t value) { - vstrhq_scatter_offset_u32 (base, offset, value); + return vstrhq_scatter_offset_u32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* +**foo1: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value) +foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value) { - vstrhq_scatter_offset (base, offset, value); + return vstrhq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c index 1dcb1f7692d..6d57a22fe41 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo (float16_t * base, uint16x8_t offset, float16x8_t value) +foo (float16_t *base, uint16x8_t offset, float16x8_t value) { - vstrhq_scatter_shifted_offset_f16 (base, offset, value); + return vstrhq_scatter_shifted_offset_f16 (base, offset, value); } -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* +**foo1: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo1 (float16_t * base, uint16x8_t offset, float16x8_t value) +foo1 (float16_t *base, uint16x8_t offset, float16x8_t value) { - vstrhq_scatter_shifted_offset (base, offset, value); + return vstrhq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c index c46eec95adf..2e77dd492a1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) +foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) { - vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p); + return vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) +foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) { - vstrhq_scatter_shifted_offset_p (base, offset, value, p); + return vstrhq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c index 7e9a549e8c2..1c83a13ffdf 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) { - vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p); + return vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) { - vstrhq_scatter_shifted_offset_p (base, offset, value, p); + return vstrhq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c index 502b4b00e2a..6d786de4379 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p); + return vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrhq_scatter_shifted_offset_p (base, offset, value, p); + return vstrhq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c index 151145ce174..fd73168ddbb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) { - vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p); + return vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) { - vstrhq_scatter_shifted_offset_p (base, offset, value, p); + return vstrhq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c index 14efd952593..689195ce603 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p); + return vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrhq_scatter_shifted_offset_p (base, offset, value, p); + return vstrhq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrht.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c index e5142ed85f7..0edacd938f6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo (int16_t * base, uint16x8_t offset, int16x8_t value) +foo (int16_t *base, uint16x8_t offset, int16x8_t value) { - vstrhq_scatter_shifted_offset_s16 (base, offset, value); + return vstrhq_scatter_shifted_offset_s16 (base, offset, value); } -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* +**foo1: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo1 (int16_t * base, uint16x8_t offset, int16x8_t value) +foo1 (int16_t *base, uint16x8_t offset, int16x8_t value) { - vstrhq_scatter_shifted_offset (base, offset, value); + return vstrhq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c index 431808f9008..ebda2faec92 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo (int16_t * base, uint32x4_t offset, int32x4_t value) +foo (int16_t *base, uint32x4_t offset, int32x4_t value) { - vstrhq_scatter_shifted_offset_s32 (base, offset, value); + return vstrhq_scatter_shifted_offset_s32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* +**foo1: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo1 (int16_t * base, uint32x4_t offset, int32x4_t value) +foo1 (int16_t *base, uint32x4_t offset, int32x4_t value) { - vstrhq_scatter_shifted_offset (base, offset, value); + return vstrhq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c index f93e5d51913..abe8bbf8045 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo (uint16_t * base, uint16x8_t offset, uint16x8_t value) +foo (uint16_t *base, uint16x8_t offset, uint16x8_t value) { - vstrhq_scatter_shifted_offset_u16 (base, offset, value); + return vstrhq_scatter_shifted_offset_u16 (base, offset, value); } -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* +**foo1: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value) +foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value) { - vstrhq_scatter_shifted_offset (base, offset, value); + return vstrhq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c index fc250706fa8..a01b04bd940 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo (uint16_t * base, uint32x4_t offset, uint32x4_t value) +foo (uint16_t *base, uint32x4_t offset, uint32x4_t value) { - vstrhq_scatter_shifted_offset_u32 (base, offset, value); + return vstrhq_scatter_shifted_offset_u32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* +**foo1: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value) +foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value) { - vstrhq_scatter_shifted_offset (base, offset, value); + return vstrhq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c index f7b3ef1012b..85f5790ff49 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint16_t * addr, uint16x8_t value) +foo (uint16_t *base, uint16x8_t value) { - vstrhq_u16 (addr, value); + return vstrhq_u16 (base, value); } -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* +**foo1: +** ... +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * addr, uint16x8_t value) +foo1 (uint16_t *base, uint16x8_t value) { - vstrhq (addr, value); + return vstrhq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c index 8e01fd10032..d0958e22222 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint16_t * addr, uint32x4_t value) +foo (uint16_t *base, uint32x4_t value) { - vstrhq_u32 (addr, value); + return vstrhq_u32 (base, value); } -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* +**foo1: +** ... +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint16_t * addr, uint32x4_t value) +foo1 (uint16_t *base, uint32x4_t value) { - vstrhq (addr, value); + return vstrhq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrh.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ From patchwork Thu May 18 10:59:08 2023 Content-Type: text/plain; charset="utf-8" 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT011.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB6418 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Stam Markianos-Wright via Gcc-patches From: Stamatis Markianos-Wright Reply-To: Stam Markianos-Wright Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766229650752696543?= X-GMAIL-MSGID: =?utf-8?q?1766229650752696543?= From: Andrea Corallo Hi all, this patch fixes the vstrwq* MVE instrinsics failing to emit the correct sequence of instruction due to a missing predicate. Also the immediate range is fixed to be multiples of 2 up between [-252, 252]. Best Regards Andrea gcc/ChangeLog: * config/arm/constraints.md (mve_vldrd_immediate): Move it to predicates.md. (Ri): Move constraint definition from predicates.md. (Rl): Define new constraint. * config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_v4si): Add missing constraint. (mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint for op 1, use mve_vstrw_immediate predicate and Rl constraint for op 2. Fix asm output spacing. (mve_vstrdq_scatter_base_wb_p_v2di): Add missing constraint. * config/arm/predicates.md (Ri) Move constraint to constraints.md (mve_vldrd_immediate): Move it from constraints.md. (mve_vstrw_immediate): New predicate. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use check-function-bodies instead of scan-assembler checks. Use extern "C" for C++ testing. * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise. --- gcc/config/arm/constraints.md | 20 ++++++++-- gcc/config/arm/mve.md | 10 ++--- gcc/config/arm/predicates.md | 14 +++---- .../arm/mve/intrinsics/vstrwq_f32.c | 32 ++++++++++++--- .../arm/mve/intrinsics/vstrwq_p_f32.c | 40 ++++++++++++++++--- .../arm/mve/intrinsics/vstrwq_p_s32.c | 40 ++++++++++++++++--- .../arm/mve/intrinsics/vstrwq_p_u32.c | 40 ++++++++++++++++--- .../arm/mve/intrinsics/vstrwq_s32.c | 32 ++++++++++++--- .../mve/intrinsics/vstrwq_scatter_base_f32.c | 28 +++++++++++-- .../intrinsics/vstrwq_scatter_base_p_f32.c | 36 +++++++++++++++-- .../intrinsics/vstrwq_scatter_base_p_s32.c | 36 +++++++++++++++-- .../intrinsics/vstrwq_scatter_base_p_u32.c | 36 +++++++++++++++-- .../mve/intrinsics/vstrwq_scatter_base_s32.c | 28 +++++++++++-- .../mve/intrinsics/vstrwq_scatter_base_u32.c | 28 +++++++++++-- .../intrinsics/vstrwq_scatter_base_wb_f32.c | 32 ++++++++++++--- .../intrinsics/vstrwq_scatter_base_wb_p_f32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_base_wb_p_s32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_base_wb_p_u32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_base_wb_s32.c | 32 ++++++++++++--- .../intrinsics/vstrwq_scatter_base_wb_u32.c | 32 ++++++++++++--- .../intrinsics/vstrwq_scatter_offset_f32.c | 32 ++++++++++++--- .../intrinsics/vstrwq_scatter_offset_p_f32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_offset_p_s32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_offset_p_u32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_offset_s32.c | 32 ++++++++++++--- .../intrinsics/vstrwq_scatter_offset_u32.c | 32 ++++++++++++--- .../vstrwq_scatter_shifted_offset_f32.c | 32 ++++++++++++--- .../vstrwq_scatter_shifted_offset_p_f32.c | 40 ++++++++++++++++--- .../vstrwq_scatter_shifted_offset_p_s32.c | 40 ++++++++++++++++--- .../vstrwq_scatter_shifted_offset_p_u32.c | 40 ++++++++++++++++--- .../vstrwq_scatter_shifted_offset_s32.c | 32 ++++++++++++--- .../vstrwq_scatter_shifted_offset_u32.c | 32 ++++++++++++--- .../arm/mve/intrinsics/vstrwq_u32.c | 32 ++++++++++++--- 33 files changed, 922 insertions(+), 178 deletions(-) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 504cd938b26..05a4ebbdd67 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -102,10 +102,6 @@ (define_constraint "Rg" (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2) || (ival == 4) || (ival == 8))"))) -;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE. -(define_predicate "mve_vldrd_immediate" - (match_test "satisfies_constraint_Ri (op)")) - (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") @@ -574,6 +570,22 @@ (define_constraint "US" (match_code "symbol_ref") ) +;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE. +(define_constraint "Ri" + "@internal In Thumb-2 state a constant is multiple of 8 and in range + of -/+ 1016 for MVE" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016) + && ((ival % 8) == 0)"))) + +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE. +(define_constraint "Rl" + "@internal In Thumb-2 state a constant is multiple of 2 and in range + of -/+ 252 for MVE" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252) + && ((ival % 2) == 0)"))) + (define_memory_constraint "Uz" "@internal A memory access that is accessible as an LDC/STC operand" diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 85d701a66b3..96dac5b02ec 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -5677,7 +5677,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_v4si" [(match_operand:V4SI 1 "s_register_operand" "0") (match_operand:SI 2 "mve_vldrd_immediate" "Ri") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:V4BI 4 "vpr_register_operand")] + (match_operand:V4BI 4 "vpr_register_operand" "Up")] VSTRWSBWBQ)) (set (match_operand:V4SI 0 "s_register_operand" "=w") (unspec:V4SI [(match_dup 1) (match_dup 2)] @@ -5726,9 +5726,9 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:V4SI 1 "s_register_operand" "0") - (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:SI 2 "mve_vstrw_immediate" "Rl") (match_operand:V4SF 3 "s_register_operand" "w") - (match_operand:V4BI 4 "vpr_register_operand")] + (match_operand:V4BI 4 "vpr_register_operand" "Up")] VSTRWQSBWB_F)) (set (match_operand:V4SI 0 "s_register_operand" "=w") (unspec:V4SI [(match_dup 1) (match_dup 2)] @@ -5740,7 +5740,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" ops[0] = operands[1]; ops[1] = operands[2]; ops[2] = operands[3]; - output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); + output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops); return ""; } [(set_attr "length" "8")]) @@ -5779,7 +5779,7 @@ (define_insn "mve_vstrdq_scatter_base_wb_p_v2di" [(match_operand:V2DI 1 "s_register_operand" "0") (match_operand:SI 2 "mve_vldrd_immediate" "Ri") (match_operand:V2DI 3 "s_register_operand" "w") - (match_operand:V2QI 4 "vpr_register_operand")] + (match_operand:V2QI 4 "vpr_register_operand" "Up")] VSTRDSBWBQ)) (set (match_operand:V2DI 0 "s_register_operand" "=w") (unspec:V2DI [(match_dup 1) (match_dup 2)] diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 8e235f63ee6..622a491482b 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -73,13 +73,13 @@ (define_predicate "mve_imm_32" (define_predicate "mve_imm_selective_upto_8" (match_test "satisfies_constraint_Rg (op)")) -;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE. -(define_constraint "Ri" - "@internal In Thumb-2 state a constant is multiple of 8 and in range - of -/+ 1016 for MVE" - (and (match_code "const_int") - (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016) - && ((ival % 8) == 0)"))) +;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE. +(define_predicate "mve_vldrd_immediate" + (match_test "satisfies_constraint_Ri (op)")) + +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE. +(define_predicate "mve_vstrw_immediate" + (match_test "satisfies_constraint_Rl (op)")) ; Predicate for stack protector guard's address in ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c index 8aa04fcbdee..e92ecb0f6bc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (float32_t * addr, float32x4_t value) +foo (float32_t *base, float32x4_t value) { - vstrwq_f32 (addr, value); + return vstrwq_f32 (base, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (float32_t * addr, float32x4_t value) +foo1 (float32_t *base, float32x4_t value) { - vstrwq (addr, value); + return vstrwq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c index 411de6414f7..f1992a67736 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (float32_t * addr, float32x4_t value, mve_pred16_t p) +foo (float32_t *base, float32x4_t value, mve_pred16_t p) { - vstrwq_p_f32 (addr, value, p); + return vstrwq_p_f32 (base, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p) +foo1 (float32_t *base, float32x4_t value, mve_pred16_t p) { - vstrwq_p (addr, value, p); + return vstrwq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c index 3b042814d27..a00aeabb9fe 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int32_t * addr, int32x4_t value, mve_pred16_t p) +foo (int32_t *base, int32x4_t value, mve_pred16_t p) { - vstrwq_p_s32 (addr, value, p); + return vstrwq_p_s32 (base, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p) +foo1 (int32_t *base, int32x4_t value, mve_pred16_t p) { - vstrwq_p (addr, value, p); + return vstrwq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c index b9e92204c88..05fded8aac8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p) +foo (uint32_t *base, uint32x4_t value, mve_pred16_t p) { - vstrwq_p_u32 (addr, value, p); + return vstrwq_p_u32 (base, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p) +foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p) { - vstrwq_p (addr, value, p); + return vstrwq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c index c7b3d91a972..b2a184f3c66 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int32_t * addr, int32x4_t value) +foo (int32_t *base, int32x4_t value) { - vstrwq_s32 (addr, value); + return vstrwq_s32 (base, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int32_t * addr, int32x4_t value) +foo1 (int32_t *base, int32x4_t value) { - vstrwq (addr, value); + return vstrwq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c index f8b56917295..c80e8d9cdc5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, float32x4_t value) { - vstrwq_scatter_base_f32 (addr, 8, value); + return vstrwq_scatter_base_f32 (addr, 0, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, float32x4_t value) { - vstrwq_scatter_base (addr, 8, value); + return vstrwq_scatter_base (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c index 4a75e6503e1..237843c0661 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p_f32 (addr, 8, value, p); + return vstrwq_scatter_base_p_f32 (addr, 0, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p (addr, 8, value, p); + return vstrwq_scatter_base_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c index 5ac4f300a7d..5f4f4a09664 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p_s32 (addr, 8, value, p); + return vstrwq_scatter_base_p_s32 (addr, 0, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p (addr, 8, value, p); + return vstrwq_scatter_base_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c index e564f26b9c7..8c5cf63f861 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p_u32 (addr, 8, value, p); + return vstrwq_scatter_base_p_u32 (addr, 0, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p (addr, 8, value, p); + return vstrwq_scatter_base_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c index 5bba36db5cb..5208cf4f808 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, int32x4_t value) { - vstrwq_scatter_base_s32 (addr, 8, value); + return vstrwq_scatter_base_s32 (addr, 0, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, int32x4_t value) { - vstrwq_scatter_base (addr, 8, value); + return vstrwq_scatter_base (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c index 1dcbb5a739c..e728db2b9f1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, uint32x4_t value) { - vstrwq_scatter_base_u32 (addr, 8, value); + return vstrwq_scatter_base_u32 (addr, 0, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, uint32x4_t value) { - vstrwq_scatter_base (addr, 8, value); + return vstrwq_scatter_base (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c index b2cc6e555ae..e481191aa57 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c @@ -1,19 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, const int offset, float32x4_t value) +foo (uint32x4_t *addr, float32x4_t value) { - vstrwq_scatter_base_wb_f32 (addr, 8, value); + return vstrwq_scatter_base_wb_f32 (addr, 0, value); } + +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, const int offset, float32x4_t value) +foo1 (uint32x4_t *addr, float32x4_t value) { - vstrwq_scatter_base_wb (addr, 8, value); + return vstrwq_scatter_base_wb (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c index 4befd49d7b9..8d217d46230 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c @@ -1,19 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) +foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p); + return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) +foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p (addr, 8, value, p); + return vstrwq_scatter_base_wb_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c index dfb1827c4f0..afc47adcd7f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c @@ -1,19 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) +foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p); + return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) +foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p (addr, 8, value, p); + return vstrwq_scatter_base_wb_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c index 4eb78c600be..65191c2f1ed 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c @@ -1,19 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) +foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p); + return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) +foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p (addr, 8, value, p); + return vstrwq_scatter_base_wb_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c index 618dbaf5aa6..b6a9f6cd1f4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c @@ -1,19 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, const int offset, int32x4_t value) +foo (uint32x4_t *addr, int32x4_t value) { - vstrwq_scatter_base_wb_s32 (addr, 8, value); + return vstrwq_scatter_base_wb_s32 (addr, 0, value); } + +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, const int offset, int32x4_t value) +foo1 (uint32x4_t *addr, int32x4_t value) { - vstrwq_scatter_base_wb (addr, 8, value); + return vstrwq_scatter_base_wb (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c index 912a4590cf5..81a278f4e2b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c @@ -1,19 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, uint32x4_t value) +foo (uint32x4_t *addr, uint32x4_t value) { - vstrwq_scatter_base_wb_u32 (addr, 8, value); + return vstrwq_scatter_base_wb_u32 (addr, 0, value); } + +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, uint32x4_t value) +foo1 (uint32x4_t *addr, uint32x4_t value) { - vstrwq_scatter_base_wb (addr, 8, value); + return vstrwq_scatter_base_wb (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c index c14d3ce607b..b81df68aa21 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (float32_t * base, uint32x4_t offset, float32x4_t value) +foo (float32_t *base, uint32x4_t offset, float32x4_t value) { - vstrwq_scatter_offset_f32 (base, offset, value); + return vstrwq_scatter_offset_f32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value) { - vstrwq_scatter_offset (base, offset, value); + return vstrwq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c index 115be56ec00..8aee42f76a3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p_f32 (base, offset, value, p); + return vstrwq_scatter_offset_p_f32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p (base, offset, value, p); + return vstrwq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c index 48652af3cff..9c74ae7a8d8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p_s32 (base, offset, value, p); + return vstrwq_scatter_offset_p_s32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p (base, offset, value, p); + return vstrwq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c index dcd42ec453f..015a202b548 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p_u32 (base, offset, value, p); + return vstrwq_scatter_offset_p_u32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p (base, offset, value, p); + return vstrwq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c index 04672e5a4aa..df373111b78 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int32_t * base, uint32x4_t offset, int32x4_t value) +foo (int32_t *base, uint32x4_t offset, int32x4_t value) { - vstrwq_scatter_offset_s32 (base, offset, value); + return vstrwq_scatter_offset_s32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value) { - vstrwq_scatter_offset (base, offset, value); + return vstrwq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c index e3d312550c6..a74696ca273 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value) { - vstrwq_scatter_offset_u32 (base, offset, value); + return vstrwq_scatter_offset_u32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value) { - vstrwq_scatter_offset (base, offset, value); + return vstrwq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c index b20c4c7ed3a..1c9b29a57b8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (float32_t * base, uint32x4_t offset, float32x4_t value) +foo (float32_t *base, uint32x4_t offset, float32x4_t value) { - vstrwq_scatter_shifted_offset_f32 (base, offset, value); + return vstrwq_scatter_shifted_offset_f32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value) { - vstrwq_scatter_shifted_offset (base, offset, value); + return vstrwq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c index 1682f702dc6..08e1572854e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c index eef6ea6e196..2b8f8a7d61f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c index b11e7e04dc4..3e4e87bf79a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c index 8ac25c47554..7f25490a69a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (int32_t * base, uint32x4_t offset, int32x4_t value) +foo (int32_t *base, uint32x4_t offset, int32x4_t value) { - vstrwq_scatter_shifted_offset_s32 (base, offset, value); + return vstrwq_scatter_shifted_offset_s32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value) { - vstrwq_scatter_shifted_offset (base, offset, value); + return vstrwq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c index 1ce0ddacc7a..a96220c4f6e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value) { - vstrwq_scatter_shifted_offset_u32 (base, offset, value); + return vstrwq_scatter_shifted_offset_u32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value) { - vstrwq_scatter_shifted_offset (base, offset, value); + return vstrwq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c index 4aec9935b84..df554af79a6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint32_t * addr, uint32x4_t value) +foo (uint32_t *base, uint32x4_t value) { - vstrwq_u32 (addr, value); + return vstrwq_u32 (base, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * addr, uint32x4_t value) +foo1 (uint32_t *base, uint32x4_t value) { - vstrwq (addr, value); + return vstrwq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ From patchwork Thu May 18 10:59:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stamatis Markianos-Wright X-Patchwork-Id: 95776 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp401644vqo; Thu, 18 May 2023 04:02:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7ujP0KSpNomySX9kyrCHCiooL0mtlwcCUkiMX3dnJ1hd7iwWs4RurOsN54jy8/B0W1xgoN X-Received: by 2002:a17:907:25ce:b0:96f:44b0:b3c0 with SMTP id ae14-20020a17090725ce00b0096f44b0b3c0mr371373ejc.56.1684407755229; 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Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT061.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9481 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Stam Markianos-Wright via Gcc-patches From: Stamatis Markianos-Wright Reply-To: Stam Markianos-Wright Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766229546307590678?= X-GMAIL-MSGID: =?utf-8?q?1766229546307590678?= Hi all, We noticed that calls to the vadcq and vsbcq intrinsics, both of which use __builtin_arm_set_fpscr_nzcvqc to set the Carry flag in the FPSCR, would produce the following code: ``` < r2 is the *carry input > vmrs r3, FPSCR_nzcvqc bic r3, r3, #536870912 orr r3, r3, r2, lsl #29 vmsr FPSCR_nzcvqc, r3 ``` when the MVE ACLE instead gives a different instruction sequence of: ``` < Rt is the *carry input > VMRS Rs,FPSCR_nzcvqc BFI Rs,Rt,#29,#1 VMSR FPSCR_nzcvqc,Rs ``` the bic + orr pair is slower and it's also wrong, because, if the *carry input is greater than 1, then we risk overwriting the top two bits of the FPSCR register (the N and Z flags). This turned out to be a problem in the header file and the solution was to simply add a `& 1x0u` to the `*carry` input: then the compiler knows that we only care about the lowest bit and can optimise to a BFI. Ok for trunk? Thanks, Stam Markianos-Wright gcc/ChangeLog: * config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic. (__arm_vadcq_u32): Likewise. (__arm_vadcq_m_s32): Likewise. (__arm_vadcq_m_u32): Likewise. (__arm_vsbcq_s32): Likewise. (__arm_vsbcq_u32): Likewise. (__arm_vsbcq_m_s32): Likewise. (__arm_vsbcq_m_u32): Likewise. * config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c: New. --- gcc/config/arm/arm_mve.h | 16 ++--- gcc/config/arm/mve.md | 2 +- .../arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c | 67 +++++++++++++++++++ 3 files changed, 76 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 1774e6eca2b..4ad1c99c288 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -4098,7 +4098,7 @@ __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry) { - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b); *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; return __res; @@ -4108,7 +4108,7 @@ __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry) { - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b); *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; return __res; @@ -4118,7 +4118,7 @@ __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p) { - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p); *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; return __res; @@ -4128,7 +4128,7 @@ __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p) { - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); uint32x4_t __res = __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b, __p); *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; return __res; @@ -4174,7 +4174,7 @@ __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry) { - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b); *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; return __res; @@ -4184,7 +4184,7 @@ __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry) { - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); uint32x4_t __res = __builtin_mve_vsbcq_uv4si (__a, __b); *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; return __res; @@ -4194,7 +4194,7 @@ __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p) { - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b, __p); *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; return __res; @@ -4204,7 +4204,7 @@ __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p) { - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b, __p); *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; return __res; diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 65d8b4b6c4e..9e3570c5264 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -6100,7 +6100,7 @@ (define_expand "mve_vldrdq_gather_base_nowb_z_v2di" (define_insn "get_fpscr_nzcvqc" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] + (unspec_volatile:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] "TARGET_HAVE_MVE" "vmrs\\t%0, FPSCR_nzcvqc" [(set_attr "type" "mve_move")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c b/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c new file mode 100644 index 00000000000..a8c6cce67c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c @@ -0,0 +1,67 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_mve_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_1m_mve } */ + +#include + +volatile int32x4_t c1; +volatile uint32x4_t c2; +int *carry; + +int +main () +{ + int32x4_t a1 = vcreateq_s32 (0, 0); + int32x4_t b1 = vcreateq_s32 (0, 0); + int32x4_t inactive1 = vcreateq_s32 (0, 0); + + uint32x4_t a2 = vcreateq_u32 (0, 0); + uint32x4_t b2 = vcreateq_u32 (0, 0); + uint32x4_t inactive2 = vcreateq_u32 (0, 0); + + mve_pred16_t p = 0xFFFF; + (*carry) = 0xFFFFFFFF; + + __builtin_arm_set_fpscr_nzcvqc (0); + c1 = vadcq (a1, b1, carry); + if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) + __builtin_abort (); + (*carry) = 0xFFFFFFFF; + __builtin_arm_set_fpscr_nzcvqc (0); + c2 = vadcq (a2, b2, carry); + if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) + __builtin_abort (); + (*carry) = 0xFFFFFFFF; + __builtin_arm_set_fpscr_nzcvqc (0); + c1 = vsbcq (a1, b1, carry); + if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) + __builtin_abort (); + (*carry) = 0xFFFFFFFF; + __builtin_arm_set_fpscr_nzcvqc (0); + c2 = vsbcq (a2, b2, carry); + if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) + __builtin_abort (); + (*carry) = 0xFFFFFFFF; + __builtin_arm_set_fpscr_nzcvqc (0); + c1 = vadcq_m (inactive1, a1, b1, carry, p); + if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) + __builtin_abort (); + (*carry) = 0xFFFFFFFF; + __builtin_arm_set_fpscr_nzcvqc (0); + c2 = vadcq_m (inactive2, a2, b2, carry, p); + if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) + __builtin_abort (); + (*carry) = 0xFFFFFFFF; + __builtin_arm_set_fpscr_nzcvqc (0); + c1 = vsbcq_m (inactive1, a1, b1, carry, p); + if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) + __builtin_abort (); + (*carry) = 0xFFFFFFFF; + __builtin_arm_set_fpscr_nzcvqc (0); + c2 = vsbcq_m (inactive2, a2, b2, carry, p); + if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) + __builtin_abort (); + + return 0; +} From patchwork Thu May 18 10:59:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stamatis Markianos-Wright X-Patchwork-Id: 95775 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp401617vqo; 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The applicable tests are authored by Andrea earlier in this patch series Ok for trunk? gcc/ChangeLog: * config/arm/arm_mve.h (__arm_vbicq): Change coerce on scalar constant. --- gcc/config/arm/arm_mve.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 4ad1c99c288..30cec519791 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -10847,10 +10847,10 @@ extern void *__ARM_undef; #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -11699,10 +11699,10 @@ extern void *__ARM_undef; #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ From patchwork Thu May 18 10:59:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stamatis Markianos-Wright X-Patchwork-Id: 95779 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp403176vqo; Thu, 18 May 2023 04:04:45 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5U6JU2Jsx6Ym97qZMeg7sgQ42uu7vf9ZI1qgdxpxfp9V3GMdsUG/X2TRWcwdiVc3Tzfm0u X-Received: by 2002:a17:907:5c5:b0:95f:56e8:1c3c with SMTP id wg5-20020a17090705c500b0095f56e81c3cmr41199000ejb.17.1684407885544; Thu, 18 May 2023 04:04:45 -0700 (PDT) Received: from sourceware.org (server2.sourceware.org. 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT041.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB10044 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Stam Markianos-Wright via Gcc-patches From: Stamatis Markianos-Wright Reply-To: Stam Markianos-Wright Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766229683259059929?= X-GMAIL-MSGID: =?utf-8?q?1766229683259059929?= Hi all, Previously we had fixed the overloading of scalar arguments to intrinsics with the introduction of a new `__ARM_mve_coerce3` _ Generic association. This allowed users to give types other than int32_t, e.g. int, short, long, etc., which previously would emit a nonsensical error message from the _Generic. Here I adjust that handling slightly and I am also doing the same thing, but for pointer types: (un)signed char* can be now used instead of (u)int8_t* (un)signed short* can be now used instead of (u)int16_t* (un)signed int* and long* can be now used instead of (u)int32_t* (un)signed long long* can be now used instead of (u)int64_t* __fp16* and _Float16* can be now used instead of float16_t* float* can be now used instead of float32_t* This required me to break down the _coerce_ generics for the specific pointer types. On the scalar types, the change in this patch is minor, renaming the _coerce_ generics and passing all scalars through the `__typeof` for consistency with each-other. No test regressions in the GCC testsuite or CMSIS-NN. gcc/ChangeLog: * config/arm/arm_mve.h: (__ARM_mve_typeid): Add more pointer types. (__ARM_mve_coerce1): Remove. (__ARM_mve_coerce2): Remove. (__ARM_mve_coerce3): Remove. (__ARM_mve_coerce_i_scalar): New. (__ARM_mve_coerce_s8_ptr): New. (__ARM_mve_coerce_u8_ptr): New. (__ARM_mve_coerce_s16_ptr): New. (__ARM_mve_coerce_u16_ptr): New. (__ARM_mve_coerce_s32_ptr): New. (__ARM_mve_coerce_u32_ptr): New. (__ARM_mve_coerce_s64_ptr): New. (__ARM_mve_coerce_u64_ptr): New. (__ARM_mve_coerce_f_scalar): New. (__ARM_mve_coerce_f16_ptr): New. (__ARM_mve_coerce_f32_ptr): New. (__arm_vst4q): Change _coerce_ overloads. (__arm_vbicq): Change _coerce_ overloads. (__arm_vld1q): Change _coerce_ overloads. (__arm_vld1q_z): Change _coerce_ overloads. (__arm_vld2q): Change _coerce_ overloads. (__arm_vld4q): Change _coerce_ overloads. (__arm_vldrhq_gather_offset): Change _coerce_ overloads. (__arm_vldrhq_gather_offset_z): Change _coerce_ overloads. (__arm_vldrhq_gather_shifted_offset): Change _coerce_ overloads. (__arm_vldrhq_gather_shifted_offset_z): Change _coerce_ overloads. (__arm_vldrwq_gather_offset): Change _coerce_ overloads. (__arm_vldrwq_gather_offset_z): Change _coerce_ overloads. (__arm_vldrwq_gather_shifted_offset): Change _coerce_ overloads. (__arm_vldrwq_gather_shifted_offset_z): Change _coerce_ overloads. (__arm_vst1q_p): Change _coerce_ overloads. (__arm_vst2q): Change _coerce_ overloads. (__arm_vst1q): Change _coerce_ overloads. (__arm_vstrhq): Change _coerce_ overloads. (__arm_vstrhq_p): Change _coerce_ overloads. (__arm_vstrhq_scatter_offset_p): Change _coerce_ overloads. (__arm_vstrhq_scatter_offset): Change _coerce_ overloads. (__arm_vstrhq_scatter_shifted_offset_p): Change _coerce_ overloads. (__arm_vstrhq_scatter_shifted_offset): Change _coerce_ overloads. (__arm_vstrwq_p): Change _coerce_ overloads. (__arm_vstrwq): Change _coerce_ overloads. (__arm_vstrwq_scatter_offset): Change _coerce_ overloads. (__arm_vstrwq_scatter_offset_p): Change _coerce_ overloads. (__arm_vstrwq_scatter_shifted_offset): Change _coerce_ overloads. (__arm_vstrwq_scatter_shifted_offset_p): Change _coerce_ overloads. (__arm_vsetq_lane): Change _coerce_ overloads. (__arm_vldrbq_gather_offset): Change _coerce_ overloads. (__arm_vdwdupq_x_u8): Change _coerce_ overloads. (__arm_vdwdupq_x_u16): Change _coerce_ overloads. (__arm_vdwdupq_x_u32): Change _coerce_ overloads. (__arm_viwdupq_x_u8): Change _coerce_ overloads. (__arm_viwdupq_x_u16): Change _coerce_ overloads. (__arm_viwdupq_x_u32): Change _coerce_ overloads. (__arm_vidupq_x_u8): Change _coerce_ overloads. (__arm_vddupq_x_u8): Change _coerce_ overloads. (__arm_vidupq_x_u16): Change _coerce_ overloads. (__arm_vddupq_x_u16): Change _coerce_ overloads. (__arm_vidupq_x_u32): Change _coerce_ overloads. (__arm_vddupq_x_u32): Change _coerce_ overloads. (__arm_vldrdq_gather_offset): Change _coerce_ overloads. (__arm_vldrdq_gather_offset_z): Change _coerce_ overloads. (__arm_vldrdq_gather_shifted_offset): Change _coerce_ overloads. (__arm_vldrdq_gather_shifted_offset_z): Change _coerce_ overloads. (__arm_vldrbq_gather_offset_z): Change _coerce_ overloads. (__arm_vidupq_u16): Change _coerce_ overloads. (__arm_vidupq_u32): Change _coerce_ overloads. (__arm_vidupq_u8): Change _coerce_ overloads. (__arm_vddupq_u16): Change _coerce_ overloads. (__arm_vddupq_u32): Change _coerce_ overloads. (__arm_vddupq_u8): Change _coerce_ overloads. (__arm_viwdupq_m): Change _coerce_ overloads. (__arm_viwdupq_u16): Change _coerce_ overloads. (__arm_viwdupq_u32): Change _coerce_ overloads. (__arm_viwdupq_u8): Change _coerce_ overloads. (__arm_vdwdupq_m): Change _coerce_ overloads. (__arm_vdwdupq_u16): Change _coerce_ overloads. (__arm_vdwdupq_u32): Change _coerce_ overloads. (__arm_vdwdupq_u8): Change _coerce_ overloads. (__arm_vstrbq): Change _coerce_ overloads. (__arm_vstrbq_p): Change _coerce_ overloads. (__arm_vstrbq_scatter_offset_p): Change _coerce_ overloads. (__arm_vstrdq_scatter_offset_p): Change _coerce_ overloads. (__arm_vstrdq_scatter_offset): Change _coerce_ overloads. (__arm_vstrdq_scatter_shifted_offset_p): Change _coerce_ overloads. (__arm_vstrdq_scatter_shifted_offset): Change _coerce_ overloads. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Add testcases. * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Add testcases. --- gcc/config/arm/arm_mve.h | 914 +++++++++--------- .../mve_intrinsic_type_overloads-fp.c | 55 +- .../mve_intrinsic_type_overloads-int.c | 74 +- 3 files changed, 577 insertions(+), 466 deletions(-) diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 30cec519791..30485e74cdd 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -10727,16 +10727,29 @@ enum { short: __ARM_mve_type_int_n, \ int: __ARM_mve_type_int_n, \ long: __ARM_mve_type_int_n, \ + long long: __ARM_mve_type_int_n, \ _Float16: __ARM_mve_type_fp_n, \ __fp16: __ARM_mve_type_fp_n, \ float: __ARM_mve_type_fp_n, \ double: __ARM_mve_type_fp_n, \ - long long: __ARM_mve_type_int_n, \ unsigned char: __ARM_mve_type_int_n, \ unsigned short: __ARM_mve_type_int_n, \ unsigned int: __ARM_mve_type_int_n, \ unsigned long: __ARM_mve_type_int_n, \ unsigned long long: __ARM_mve_type_int_n, \ + signed char*: __ARM_mve_type_int8_t_ptr, \ + short*: __ARM_mve_type_int16_t_ptr, \ + int*: __ARM_mve_type_int32_t_ptr, \ + long*: __ARM_mve_type_int32_t_ptr, \ + long long*: __ARM_mve_type_int64_t_ptr, \ + _Float16*: __ARM_mve_type_float16_t_ptr, \ + __fp16*: __ARM_mve_type_float16_t_ptr, \ + float*: __ARM_mve_type_float32_t_ptr, \ + unsigned char*: __ARM_mve_type_uint8_t_ptr, \ + unsigned short*: __ARM_mve_type_uint16_t_ptr, \ + unsigned int*: __ARM_mve_type_uint32_t_ptr, \ + unsigned long*: __ARM_mve_type_uint32_t_ptr, \ + unsigned long long*: __ARM_mve_type_uint64_t_ptr, \ default: __ARM_mve_unsupported_type)) #else #define __ARM_mve_typeid(x) _Generic(x, \ @@ -10795,32 +10808,67 @@ enum { unsigned int: __ARM_mve_type_int_n, \ unsigned long: __ARM_mve_type_int_n, \ unsigned long long: __ARM_mve_type_int_n, \ + signed char*: __ARM_mve_type_int8_t_ptr, \ + short*: __ARM_mve_type_int16_t_ptr, \ + int*: __ARM_mve_type_int32_t_ptr, \ + long*: __ARM_mve_type_int32_t_ptr, \ + long long*: __ARM_mve_type_int64_t_ptr, \ + unsigned char*: __ARM_mve_type_uint8_t_ptr, \ + unsigned short*: __ARM_mve_type_uint16_t_ptr, \ + unsigned int*: __ARM_mve_type_uint32_t_ptr, \ + unsigned long*: __ARM_mve_type_uint32_t_ptr, \ + unsigned long long*: __ARM_mve_type_uint64_t_ptr, \ default: __ARM_mve_unsupported_type)) #endif /* MVE Floating point. */ extern void *__ARM_undef; #define __ARM_mve_coerce(param, type) \ _Generic(param, type: param, default: *(type *)__ARM_undef) -#define __ARM_mve_coerce1(param, type) \ - _Generic(param, type: param, const type: param, default: *(type *)__ARM_undef) -#define __ARM_mve_coerce2(param, type) \ - _Generic(param, type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef)) -#define __ARM_mve_coerce3(param, type) \ - _Generic(param, type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef)) +#define __ARM_mve_coerce_i_scalar(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef)) + +#define __ARM_mve_coerce_s8_ptr(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, signed char*: param, default: *(type *)__ARM_undef)) +#define __ARM_mve_coerce_u8_ptr(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, unsigned char*: param, default: *(type *)__ARM_undef)) + +#define __ARM_mve_coerce_s16_ptr(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, short*: param, default: *(type *)__ARM_undef)) +#define __ARM_mve_coerce_u16_ptr(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, unsigned short*: param, default: *(type *)__ARM_undef)) + +#define __ARM_mve_coerce_s32_ptr(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, int*: param, long*: param, default: *(type *)__ARM_undef)) +#define __ARM_mve_coerce_u32_ptr(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, unsigned int*: param, unsigned long*: param, default: *(type *)__ARM_undef)) + +#define __ARM_mve_coerce_s64_ptr(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, long long*: param, default: *(type *)__ARM_undef)) +#define __ARM_mve_coerce_u64_ptr(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, unsigned long long*: param, default: *(type *)__ARM_undef)) + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +#define __ARM_mve_coerce_f_scalar(param, type) \ + _Generic(param, type: param, const type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef)) +#define __ARM_mve_coerce_f16_ptr(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, __fp16*: param, _Float16*: param, default: *(type *)__ARM_undef)) +#define __ARM_mve_coerce_f32_ptr(param, type) \ + _Generic(param, type: param, const type: param, default: _Generic (param, float*: param, default: *(type *)__ARM_undef)) +#endif #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ #define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce_f16_ptr(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) #define __arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -10847,10 +10895,10 @@ extern void *__ARM_undef; #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -11188,236 +11236,236 @@ extern void *__ARM_undef; #define __arm_vld1q(p0) (\ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce1(p0, float32_t *)))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \ + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *)))) #define __arm_vld1q_z(p0,p1) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce1(p0, float16_t *), p1), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \ + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), p1), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1))) #define __arm_vld2q(p0) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce1(p0, float32_t *)))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \ + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *)))) #define __arm_vld4q(p0) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce1(p0, float32_t *)))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \ + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *)))) #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) #define __arm_vldrwq_gather_offset(p0,p1) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1))) #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2))) + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2))) #define __arm_vldrwq_gather_shifted_offset(p0,p1) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1))) #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2))) + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2))) #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));}) #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));}) #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));}) #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) #define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ @@ -11434,44 +11482,44 @@ extern void *__ARM_undef; #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));}) #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -11600,16 +11648,16 @@ extern void *__ARM_undef; #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) #else /* MVE Integer. */ @@ -11625,12 +11673,12 @@ extern void *__ARM_undef; #define __arm_vst4q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) #define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -11699,10 +11747,10 @@ extern void *__ARM_undef; #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -11789,12 +11837,12 @@ extern void *__ARM_undef; #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) #define __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ @@ -11803,144 +11851,144 @@ extern void *__ARM_undef; #define __arm_vld1q(p0) (\ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)))) #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) #define __arm_vldrwq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));}) + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));}) + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) #define __arm_vldrwq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));}) + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));}) + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));}) #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) #define __arm_vstrdq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ @@ -11955,58 +12003,58 @@ extern void *__ARM_undef; #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -12092,29 +12140,29 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define __arm_vld1q_z(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1))) #define __arm_vld2q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *)))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)))) #define __arm_vld4q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *)))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)))) #define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -12130,14 +12178,14 @@ extern void *__ARM_undef; #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));}) + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));}) #endif /* MVE Integer. */ @@ -12146,62 +12194,62 @@ extern void *__ARM_undef; #define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) #define __arm_vdwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) #define __arm_vdwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) #define __arm_viwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) #define __arm_viwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) #define __arm_viwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) #define __arm_vidupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u8 ((uint32_t) __p1, p2, p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) #define __arm_vddupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u8 ((uint32_t) __p1, p2, p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) #define __arm_vidupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u16 ((uint32_t) __p1, p2, p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) #define __arm_vddupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u16 ((uint32_t) __p1, p2, p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) #define __arm_vidupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u32 ((uint32_t) __p1, p2, p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) #define __arm_vddupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u32 ((uint32_t) __p1, p2, p3), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) #define __arm_vhcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ @@ -12234,20 +12282,20 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_wb_u64 (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) #define __arm_vldrdq_gather_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \ - int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1))) + int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \ + int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1))) #define __arm_vldrdq_gather_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \ - int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2))) + int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \ + int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2))) #define __arm_vldrdq_gather_shifted_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \ - int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1))) + int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \ + int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1))) #define __arm_vldrdq_gather_shifted_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \ - int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2))) + int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \ + int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2))) #define __arm_vadciq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -12303,12 +12351,12 @@ extern void *__ARM_undef; #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) #define __arm_vhcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -12364,12 +12412,12 @@ extern void *__ARM_undef; #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) #define __arm_vidupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -12377,9 +12425,9 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) #define __arm_vddupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -12387,89 +12435,89 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) #define __arm_vidupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u16 ((uint32_t) __p0, p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) #define __arm_vidupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u32 ((uint32_t) __p0, p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) #define __arm_vidupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u8 ((uint32_t) __p0, p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) #define __arm_vddupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u16 ((uint32_t) __p0, p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) #define __arm_vddupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u32 ((uint32_t) __p0, p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) #define __arm_vddupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u8 ((uint32_t) __p0, p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) #define __arm_viwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) #define __arm_viwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce3(p0, int), p1, (const int) p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, (const int) p2));}) + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, (const int) p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, (const int) p2));}) #define __arm_viwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce3(p0, int), p1, p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) #define __arm_viwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce3(p0, int), p1, p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) #define __arm_vdwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) #define __arm_vdwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce3(p0, int), p1, p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) #define __arm_vdwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce3(p0, int), p1, p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) #define __arm_vdwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce3(p0, int), p1, p2), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) #define __arm_vshlcq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -12514,22 +12562,22 @@ extern void *__ARM_undef; #define __arm_vstrbq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) #define __arm_vstrbq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) #define __arm_vstrdq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ @@ -12545,47 +12593,47 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) #define __arm_vstrbq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define __arm_vstrdq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ - int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) #define __arm_vstrdq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ - int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) #define __arm_vstrdq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ - int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) #define __arm_vstrdq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ - int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) #endif /* __cplusplus */ #endif /* __ARM_FEATURE_MVE */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c index a2787a47859..a1e786ecd9f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c @@ -1,6 +1,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */ +/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */ +/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */ #include "arm_mve.h" float f1; @@ -10,35 +11,14 @@ float32_t f4; __fp16 f5; _Float16 f6; -int i1; -short i2; -long i3; -long long i4; -int8_t i5; -int16_t i6; -int32_t i7; -int64_t i8; - float16x8_t floatvec; -int16x8_t intvec; -void test(void) +/* Test a few different supported ways of passing a scalar int value. +The intrinsic vmulq was chosen arbitrarily, but it is representative of +all intrinsics that take a non-const scalar value. */ +void +test_scalars (void) { - /* Test a few different supported ways of passing an int value. The - intrinsic vmulq was chosen arbitrarily, but it is representative of - all intrinsics that take a non-const scalar value. */ - intvec = vmulq(intvec, 2); - intvec = vmulq(intvec, (int32_t) 2); - intvec = vmulq(intvec, (short) 2); - intvec = vmulq(intvec, i1); - intvec = vmulq(intvec, i2); - intvec = vmulq(intvec, i3); - intvec = vmulq(intvec, i4); - intvec = vmulq(intvec, i5); - intvec = vmulq(intvec, i6); - intvec = vmulq(intvec, i7); - intvec = vmulq(intvec, i8); - /* Test a few different supported ways of passing a float value. */ floatvec = vmulq(floatvec, 0.5); floatvec = vmulq(floatvec, 0.5f); @@ -53,4 +33,25 @@ void test(void) floatvec = vmulq(floatvec, (_Float16) 0.15); } +/* Next, test a number of valid pointer overloads. */ +void +foo11 (__fp16 * addr, float16x8_t value) +{ + vst1q (addr, value); +} + +#ifndef __cplusplus +void +foo12 (_Float16 * addr, float16x8_t value) +{ + vst1q (addr, value); +} +#endif + +void +foo13 (float * addr, float32x4_t value) +{ + vst1q (addr, value); +} + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c index 7b88f462e17..7947dc024bc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c @@ -1,7 +1,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */ - +/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */ +/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */ #include "arm_mve.h" int i1; @@ -15,11 +15,12 @@ int64_t i8; int16x8_t intvec; -void test(void) +/* Test a few different supported ways of passing a scalar int value. +The intrinsic vmulq was chosen arbitrarily, but it is representative of +all intrinsics that take a non-const scalar value. */ +void +test_scalars (void) { - /* Test a few different supported ways of passing an int value. The - intrinsic vmulq was chosen arbitrarily, but it is representative of - all intrinsics that take a non-const scalar value. */ intvec = vmulq(intvec, 2); intvec = vmulq(intvec, (int32_t) 2); intvec = vmulq(intvec, (short) 2); @@ -33,4 +34,65 @@ void test(void) intvec = vmulq(intvec, i8); } +/* Next, test a number of valid pointer overloads. */ +void +foo1 (signed char * addr, int8x16_t value) +{ + vst1q (addr, value); +} + +void +foo2 (short * addr, int16x8_t value) +{ + vst1q (addr, value); +} + +void +foo3 (int * addr, int32x4_t value) +{ + vst1q (addr, value); /* { dg-warning "invalid conversion" "" { target c++ } } */ +} + +void +foo4 (long * addr, int32x4_t value) +{ + vst1q (addr, value); +} + +void +foo5 (long long * addr, uint64x2_t value) +{ + vldrdq_gather_offset (addr, value); +} + +void +foo6 (unsigned char * addr, uint8x16_t value) +{ + vst1q (addr, value); +} + +void +foo7 (unsigned short * addr, uint16x8_t value) +{ + vst1q (addr, value); +} + +void +foo8 (unsigned int * addr, uint32x4_t value) +{ + vst1q (addr, value); /* { dg-warning "invalid conversion" "" { target c++ } } */ +} + +void +foo9 (unsigned long * addr, uint32x4_t value) +{ + vst1q (addr, value); +} + +void +foo10 (unsigned long long * addr, uint64x2_t value) +{ + vldrdq_gather_offset (addr, value); +} + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ From patchwork Thu May 18 10:59:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stamatis Markianos-Wright X-Patchwork-Id: 95782 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp405092vqo; Thu, 18 May 2023 04:07:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4rq81KgDNJPndvu3arYZwTH+BkeBKZtqXc4xamYDNQ2pnhjyDmR8anwOmz723TL2NxqpJx X-Received: by 2002:a17:907:2d09:b0:966:4d75:4a44 with SMTP id gs9-20020a1709072d0900b009664d754a44mr36355041ejc.24.1684408057223; Thu, 18 May 2023 04:07:37 -0700 (PDT) Received: from sourceware.org (server2.sourceware.org. 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"Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766229862975634752?= X-GMAIL-MSGID: =?utf-8?q?1766229862975634752?= Following Andrea's overhaul of the MVE testsuite, these tests are now reduntant, as equivalent checks have been added to the each intrinsic's .c test. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vaddq_m.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c: Removed. * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c: Removed. * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c: Removed. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c: Removed. * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c: Removed. * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c: Removed. --- .../arm/mve/intrinsics/mve_fp_vaddq_n.c | 47 ------ .../arm/mve/intrinsics/mve_vaddq_m.c | 48 ------ .../arm/mve/intrinsics/mve_vaddq_n.c | 31 ---- .../arm/mve/intrinsics/mve_vddupq_m_n_u16.c | 13 -- .../arm/mve/intrinsics/mve_vddupq_m_n_u32.c | 13 -- .../arm/mve/intrinsics/mve_vddupq_m_n_u8.c | 13 -- .../arm/mve/intrinsics/mve_vddupq_n_u16.c | 13 -- .../arm/mve/intrinsics/mve_vddupq_n_u32.c | 13 -- .../arm/mve/intrinsics/mve_vddupq_n_u8.c | 13 -- .../arm/mve/intrinsics/mve_vddupq_x_n_u16.c | 12 -- .../arm/mve/intrinsics/mve_vddupq_x_n_u32.c | 12 -- .../arm/mve/intrinsics/mve_vddupq_x_n_u8.c | 12 -- .../arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c | 13 -- .../arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c | 13 -- .../arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c | 13 -- .../arm/mve/intrinsics/mve_vidupq_m_n_u16.c | 13 -- .../arm/mve/intrinsics/mve_vidupq_m_n_u32.c | 12 -- .../arm/mve/intrinsics/mve_vidupq_m_n_u8.c | 13 -- .../arm/mve/intrinsics/mve_vidupq_n_u16.c | 13 -- .../arm/mve/intrinsics/mve_vidupq_n_u32.c | 12 -- .../arm/mve/intrinsics/mve_vidupq_n_u8.c | 13 -- .../arm/mve/intrinsics/mve_vidupq_x_n_u16.c | 12 -- .../arm/mve/intrinsics/mve_vidupq_x_n_u32.c | 12 -- .../arm/mve/intrinsics/mve_vidupq_x_n_u8.c | 12 -- .../arm/mve/intrinsics/mve_viwdupq_x_n_u16.c | 13 -- .../arm/mve/intrinsics/mve_viwdupq_x_n_u32.c | 13 -- .../arm/mve/intrinsics/mve_viwdupq_x_n_u8.c | 13 -- .../intrinsics/mve_vldrdq_gather_offset_s64.c | 12 -- .../intrinsics/mve_vldrdq_gather_offset_u64.c | 12 -- .../mve_vldrdq_gather_offset_z_s64.c | 12 -- .../mve_vldrdq_gather_offset_z_u64.c | 12 -- .../mve_vldrdq_gather_shifted_offset_s64.c | 12 -- .../mve_vldrdq_gather_shifted_offset_u64.c | 12 -- .../mve_vldrdq_gather_shifted_offset_z_s64.c | 12 -- .../mve_vldrdq_gather_shifted_offset_z_u64.c | 12 -- .../intrinsics/mve_vldrhq_gather_offset_f16.c | 12 -- .../intrinsics/mve_vldrhq_gather_offset_s16.c | 12 -- .../intrinsics/mve_vldrhq_gather_offset_s32.c | 12 -- .../intrinsics/mve_vldrhq_gather_offset_u16.c | 12 -- .../intrinsics/mve_vldrhq_gather_offset_u32.c | 13 -- .../mve_vldrhq_gather_offset_z_f16.c | 12 -- .../mve_vldrhq_gather_offset_z_s16.c | 12 -- .../mve_vldrhq_gather_offset_z_s32.c | 12 -- .../mve_vldrhq_gather_offset_z_u16.c | 13 -- .../mve_vldrhq_gather_offset_z_u32.c | 13 -- .../mve_vldrhq_gather_shifted_offset_f16.c | 12 -- .../mve_vldrhq_gather_shifted_offset_s16.c | 13 -- .../mve_vldrhq_gather_shifted_offset_s32.c | 13 -- .../mve_vldrhq_gather_shifted_offset_u16.c | 13 -- .../mve_vldrhq_gather_shifted_offset_u32.c | 13 -- .../mve_vldrhq_gather_shifted_offset_z_f16.c | 13 -- .../mve_vldrhq_gather_shifted_offset_z_s16.c | 13 -- .../mve_vldrhq_gather_shifted_offset_z_s32.c | 12 -- .../mve_vldrhq_gather_shifted_offset_z_u16.c | 12 -- .../mve_vldrhq_gather_shifted_offset_z_u32.c | 12 -- .../intrinsics/mve_vldrwq_gather_offset_f32.c | 12 -- .../intrinsics/mve_vldrwq_gather_offset_s32.c | 13 -- .../intrinsics/mve_vldrwq_gather_offset_u32.c | 13 -- .../mve_vldrwq_gather_offset_z_f32.c | 12 -- .../mve_vldrwq_gather_offset_z_s32.c | 13 -- .../mve_vldrwq_gather_offset_z_u32.c | 13 -- .../mve_vldrwq_gather_shifted_offset_f32.c | 12 -- .../mve_vldrwq_gather_shifted_offset_s32.c | 13 -- .../mve_vldrwq_gather_shifted_offset_u32.c | 13 -- .../mve_vldrwq_gather_shifted_offset_z_f32.c | 12 -- .../mve_vldrwq_gather_shifted_offset_z_s32.c | 13 -- .../mve_vldrwq_gather_shifted_offset_z_u32.c | 13 -- .../mve_vstore_scatter_shifted_offset.c | 141 ----------------- .../mve_vstore_scatter_shifted_offset_p.c | 142 ------------------ .../arm/mve/intrinsics/vaddq_m_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vaddq_m_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vaddq_x_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vaddq_x_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpeqq_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpeqq_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpgeq_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpgeq_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpgtq_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpgtq_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpleq_m_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpleq_m_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpleq_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpleq_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpltq_m_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpltq_m_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpltq_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpltq_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpneq_m_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpneq_m_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vcmpneq_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vcmpneq_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vfmaq_m_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vfmaq_m_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vfmaq_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vfmaq_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vfmasq_m_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vfmasq_m_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vfmasq_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vfmasq_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vmaxnmavq_f16-1.c | 12 -- .../arm/mve/intrinsics/vmaxnmavq_f32-1.c | 12 -- .../arm/mve/intrinsics/vmaxnmavq_p_f16-1.c | 12 -- .../arm/mve/intrinsics/vmaxnmavq_p_f32-1.c | 12 -- .../arm/mve/intrinsics/vmaxnmvq_f16-1.c | 12 -- .../arm/mve/intrinsics/vmaxnmvq_f32-1.c | 12 -- .../arm/mve/intrinsics/vmaxnmvq_p_f16-1.c | 12 -- .../arm/mve/intrinsics/vmaxnmvq_p_f32-1.c | 12 -- .../arm/mve/intrinsics/vminnmavq_f16-1.c | 12 -- .../arm/mve/intrinsics/vminnmavq_f32-1.c | 12 -- .../arm/mve/intrinsics/vminnmavq_p_f16-1.c | 12 -- .../arm/mve/intrinsics/vminnmavq_p_f32-1.c | 12 -- .../arm/mve/intrinsics/vminnmvq_f16-1.c | 12 -- .../arm/mve/intrinsics/vminnmvq_f32-1.c | 12 -- .../arm/mve/intrinsics/vminnmvq_p_f16-1.c | 12 -- .../arm/mve/intrinsics/vminnmvq_p_f32-1.c | 12 -- .../arm/mve/intrinsics/vmulq_m_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vmulq_m_n_f32-1.c | 12 -- .../arm/mve/intrinsics/vmulq_n_f16-1.c | 12 -- .../arm/mve/intrinsics/vmulq_n_f32-1.c | 12 -- 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foo (int8x16_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -int16x8_t foo1 (int16x8_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -int32x4_t foo2 (int32x4_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -uint8x16_t foo3 (uint8x16_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -uint16x8_t foo4 (uint16x8_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -uint32x4_t foo5 (uint32x4_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -float16x8_t foo6 (float16x8_t a) -{ - return vaddq (a, (float16_t)23.6); -} -float32x4_t foo7 (float32x4_t a) -{ - return vaddq (a, (float32_t)23.46); -} -float16x8_t foo8 (float16x8_t a) -{ - return vaddq (a, 23.6); -} -float32x4_t foo9 (float32x4_t a) -{ - return vaddq (a, 23.46); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c deleted file mode 100644 index 719b95d9020..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c +++ /dev/null @@ -1,48 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include -mve_pred16_t p; - -int32x4_t fn1 (int32x4_t vecIdx) -{ - return vaddq_m(vuninitializedq_s32(), vecIdx, 1, p); -} - -int16x8_t fn2 (int16x8_t vecIdx) -{ - return vaddq_m(vuninitializedq_s16(), vecIdx, 1, p); -} - -int8x16_t fn3 (int8x16_t vecIdx) -{ - return vaddq_m(vuninitializedq_s8(), vecIdx, 1, p); -} - -uint32x4_t fn4 (uint32x4_t vecIdx) -{ - return vaddq_m(vuninitializedq_u32(), vecIdx, 1, p); -} - -uint16x8_t fn5 (uint16x8_t vecIdx) -{ - return vaddq_m(vuninitializedq_u16(), vecIdx, 1, p); -} - -uint8x16_t fn6 (uint8x16_t vecIdx) -{ - return vaddq_m(vuninitializedq_u8(), vecIdx, 1, p); -} - -float32x4_t fn7 (float32x4_t vecIdx) -{ - return vaddq_m(vuninitializedq_f32(), vecIdx, (float32_t) 1.23, p); -} - -float16x8_t fn8 (float16x8_t vecIdx) -{ - return vaddq_m(vuninitializedq_f16(), vecIdx, (float16_t) 1.40, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c deleted file mode 100644 index baa7fabe061..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c +++ /dev/null @@ -1,31 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include -int8x16_t foo (int8x16_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -int16x8_t foo1 (int16x8_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -int32x4_t foo2 (int32x4_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -uint8x16_t foo3 (uint8x16_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -uint16x8_t foo4 (uint16x8_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} -uint32x4_t foo5 (uint32x4_t a, int16_t b) -{ - return vaddq (a, (b<<3)); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c deleted file mode 100644 index 15587802925..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint16x8_t -foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p) -{ - return vddupq_m (inactive, a, 1, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c deleted file mode 100644 index 8a9ed6327d3..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p) -{ - return vddupq_m (inactive, a, 4, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c deleted file mode 100644 index fe4aceeea97..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint8x16_t -foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p) -{ - return vddupq_m (inactive, a, 4, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c deleted file mode 100644 index 05a68cbe559..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint16x8_t -foo1 (int32_t a) -{ - return vddupq_u16 (a, 4); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c deleted file mode 100644 index f702c4cdb0a..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (int32_t a) -{ - return vddupq_u32 (a, 1); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c deleted file mode 100644 index f272056c423..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint8x16_t -foo1 (int32_t a) -{ - return vddupq_u8 (a, 1); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c deleted file mode 100644 index 31e37827e60..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint16x8_t -foo1 (int32_t a, mve_pred16_t p) -{ - return vddupq_x_u16 (a, 1, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c deleted file mode 100644 index 9989d0b0f00..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint32x4_t -foo1 (int32_t a, mve_pred16_t p) -{ - return vddupq_x_u32 (a, 4, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c deleted file mode 100644 index 19f1501fe4e..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint8x16_t -foo1 (int32_t a, mve_pred16_t p) -{ - return vddupq_x_u8 (a, 4, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c deleted file mode 100644 index 07ea2d7d14c..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint16x8_t -foo1 (int32_t a, uint32_t b, mve_pred16_t p) -{ - return vdwdupq_x_u16 (a, b, 1, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c deleted file mode 100644 index 9889b0b2b66..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (int32_t a, uint32_t b, mve_pred16_t p) -{ - return vdwdupq_x_u32 (a, b, 4, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c deleted file mode 100644 index 13ad8d69e18..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint8x16_t -foo1 (int32_t a, uint32_t b, mve_pred16_t p) -{ - return vdwdupq_x_u8 (a, b, 4, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c deleted file mode 100644 index cbe998e2faa..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint16x8_t -foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p) -{ - return vidupq_m (inactive, a, 4, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c deleted file mode 100644 index c9aa5c661de..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint32x4_t -foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p) -{ - return vidupq_m (inactive, a, 1, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c deleted file mode 100644 index 7b075744d9a..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint8x16_t -foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p) -{ - return vidupq_m (inactive, a, 1, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c deleted file mode 100644 index a461a1e64b1..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint16x8_t -foo1 (int32_t a) -{ - return vidupq_u16 (a, 4); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c deleted file mode 100644 index c5b01a7ac90..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint32x4_t -foo1 (int32_t a) -{ - return vidupq_u32 (a, 1); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c deleted file mode 100644 index f963d51ac0f..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint8x16_t -foo1 (int32_t a) -{ - return vidupq_u8 (a, 1); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c deleted file mode 100644 index aecd4be5e71..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint16x8_t -foo1 (int32_t a, mve_pred16_t p) -{ - return vidupq_x_u16 (a, 4, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c deleted file mode 100644 index d3d33053f92..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint32x4_t -foo1 (int32_t a, mve_pred16_t p) -{ - return vidupq_x_u32 (a, 1, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c deleted file mode 100644 index f71953aeef4..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint8x16_t -foo1 (int32_t a, mve_pred16_t p) -{ - return vidupq_x_u8 (a, 1, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c deleted file mode 100644 index 312966773e6..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint16x8_t -foo1 (int32_t a, uint32_t b, mve_pred16_t p) -{ - return viwdupq_x_u16 (a, b, 2, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c deleted file mode 100644 index a5d758126d4..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (int32_t a, uint32_t b, mve_pred16_t p) -{ - return viwdupq_x_u32 (a, b, 4, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c deleted file mode 100644 index aa4e7375d39..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint8x16_t -foo1 (int32_t a, uint32_t b, mve_pred16_t p) -{ - return viwdupq_x_u8 (a, b, 8, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c deleted file mode 100644 index e5b635983bf..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -int64x2_t -foo1 (int64_t * base, uint64x2_t offset) -{ - return vldrdq_gather_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c deleted file mode 100644 index 8d96527c6df..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint64x2_t -foo1 (uint64_t * base, uint64x2_t offset) -{ - return vldrdq_gather_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c deleted file mode 100644 index e66e4465b19..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -int64x2_t -foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p) -{ - return vldrdq_gather_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c deleted file mode 100644 index 7ca9590c12c..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint64x2_t -foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p) -{ - return vldrdq_gather_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c deleted file mode 100644 index b8491680536..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -int64x2_t -foo1 (int64_t * base, uint64x2_t offset) -{ - return vldrdq_gather_shifted_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c deleted file mode 100644 index 851d4a1f435..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint64x2_t -foo1 (uint64_t * base, uint64x2_t offset) -{ - return vldrdq_gather_shifted_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c deleted file mode 100644 index 586e38cfe43..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -int64x2_t -foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p) -{ - return vldrdq_gather_shifted_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c deleted file mode 100644 index dd6f482422f..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint64x2_t -foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p) -{ - return vldrdq_gather_shifted_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c deleted file mode 100644 index 3c0ae4b4262..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16_t * base, uint16x8_t offset) -{ - return vldrhq_gather_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c deleted file mode 100644 index bc7a51b38a5..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -int16x8_t -foo1 (int16_t * base, uint16x8_t offset) -{ - return vldrhq_gather_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c deleted file mode 100644 index d6e83072995..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -int32x4_t -foo1 (int16_t * base, uint32x4_t offset) -{ - return vldrhq_gather_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c deleted file mode 100644 index 21b0b1cf52e..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint16x8_t -foo1 (uint16_t * base, uint16x8_t offset) -{ - return vldrhq_gather_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c deleted file mode 100644 index 3a9c47e9c47..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (uint16_t * base, uint32x4_t offset) -{ - return vldrhq_gather_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c deleted file mode 100644 index e31d0bc05bb..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p) -{ - return vldrhq_gather_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c deleted file mode 100644 index 6a40159be42..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -int16x8_t -foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p) -{ - return vldrhq_gather_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c deleted file mode 100644 index 1d9a70db727..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -int32x4_t -foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p) -{ - return vldrhq_gather_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c deleted file mode 100644 index 8fedbef9aef..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint16x8_t -foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p) -{ - return vldrhq_gather_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c deleted file mode 100644 index db410437c02..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p) -{ - return vldrhq_gather_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c deleted file mode 100644 index c12bd91a733..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16_t * base, uint16x8_t offset) -{ - return vldrhq_gather_shifted_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c deleted file mode 100644 index df291626299..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -int16x8_t -foo1 (int16_t * base, uint16x8_t offset) -{ - return vldrhq_gather_shifted_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c deleted file mode 100644 index 9bc6627accf..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -int32x4_t -foo1 (int16_t * base, uint32x4_t offset) -{ - return vldrhq_gather_shifted_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c deleted file mode 100644 index c470871617d..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint16x8_t -foo1 (uint16_t * base, uint16x8_t offset) -{ - return vldrhq_gather_shifted_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c deleted file mode 100644 index 2d4fe4c1d25..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (uint16_t * base, uint32x4_t offset) -{ - return vldrhq_gather_shifted_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c deleted file mode 100644 index 755540d93b6..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p) -{ - return vldrhq_gather_shifted_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler "vldrht.f16" } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c deleted file mode 100644 index b9fc8d3242b..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -int16x8_t -foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p) -{ - return vldrhq_gather_shifted_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler "vldrht.u16" } } */ -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c deleted file mode 100644 index c65df114f15..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -int32x4_t -foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p) -{ - return vldrhq_gather_shifted_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c deleted file mode 100644 index 8bb493bc6c0..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint16x8_t -foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p) -{ - return vldrhq_gather_shifted_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c deleted file mode 100644 index cac933f0f36..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -uint32x4_t -foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p) -{ - return vldrhq_gather_shifted_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c deleted file mode 100644 index 6d10e1ce9e8..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32_t * base, uint32x4_t offset) -{ - return vldrwq_gather_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c deleted file mode 100644 index 0f29a6a8aa1..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -int32x4_t -foo1 (int32_t * base, uint32x4_t offset) -{ - return vldrwq_gather_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c deleted file mode 100644 index 29e231757ec..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (uint32_t * base, uint32x4_t offset) -{ - return vldrwq_gather_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c deleted file mode 100644 index 77a949fc1a6..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p) -{ - return vldrwq_gather_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c deleted file mode 100644 index 849783ab89f..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -int32x4_t -foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p) -{ - return vldrwq_gather_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c deleted file mode 100644 index 3fe47cbeab5..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p) -{ - return vldrwq_gather_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c deleted file mode 100644 index 0d166348de5..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32_t * base, uint32x4_t offset) -{ - return vldrwq_gather_shifted_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c deleted file mode 100644 index 78e520b159e..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -int32x4_t -foo1 (int32_t * base, uint32x4_t offset) -{ - return vldrwq_gather_shifted_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c deleted file mode 100644 index 6b8b72818d9..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (uint32_t * base, uint32x4_t offset) -{ - return vldrwq_gather_shifted_offset (base, offset); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c deleted file mode 100644 index db79e57a2f5..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p) -{ - return vldrwq_gather_shifted_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c deleted file mode 100644 index e060fee10ca..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -int32x4_t -foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p) -{ - return vldrwq_gather_shifted_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c deleted file mode 100644 index 72446470ae3..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -uint32x4_t -foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p) -{ - return vldrwq_gather_shifted_offset_z (base, offset, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c deleted file mode 100644 index 62dfb450a6d..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c +++ /dev/null @@ -1,141 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -int -foowu32( uint32_t * pDataSrc, uint32_t * pDataDest) -{ - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; - uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc); - uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[4]); - vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs1, vecIn1); - vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs2, vecIn2); - pDataDest[8] = pDataSrc[8]; - return 0; -} - -int -foowf32( float32_t * pDataSrc, float32_t * pDataDest) -{ - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; - float32x4_t vecIn1 = vldrwq_f32 ((float32_t const *) pDataSrc); - float32x4_t vecIn2 = vldrwq_f32 ((float32_t const *) &pDataSrc[4]); - vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs1, vecIn1); - vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs2, vecIn2); - pDataDest[8] = pDataSrc[8]; - return 0; -} - -int -foohu16( uint16_t * pDataSrc, uint16_t * pDataDest) -{ - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; - uint16x8_t vecIn1 = vldrhq_u16 ((uint16_t const *) pDataSrc); - uint16x8_t vecIn2 = vldrhq_u16 ((uint16_t const *) &pDataSrc[8]); - vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs1, vecIn1); - vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs2, vecIn2); - pDataDest[16] = pDataSrc[16]; - return 0; -} - -int -foohu32( uint32_t * pDataSrc, uint32_t * pDataDest) -{ - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; - uint32x4_t vecIn1 = vldrhq_u32 ((uint16_t const *) pDataSrc); - uint32x4_t vecIn2 = vldrhq_u32 ((uint16_t const *) &pDataSrc[4]); - vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1); - vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2); - pDataDest[8] = pDataSrc[8]; - return 0; -} - -int -foohf16( float16_t * pDataSrc, float16_t * pDataDest) -{ - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; - float16x8_t vecIn1 = vldrhq_f16 ((float16_t const *) pDataSrc); - float16x8_t vecIn2 = vldrhq_f16 ((float16_t const *) &pDataSrc[8]); - vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs1, vecIn1); - vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs2, vecIn2); - pDataDest[16] = pDataSrc[16]; - return 0; -} - -int -foodu64( uint64_t * pDataSrc, uint64_t * pDataDest) -{ - const uint64x2_t vecOffs1 = { 0, 1}; - const uint64x2_t vecOffs2 = { 2, 3}; - uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc); - uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[2]); - - vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1); - vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2); - - pDataDest[2] = pDataSrc[2]; - return 0; -} - -int -foows32( int32_t * pDataSrc, int32_t * pDataDest) -{ - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; - int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc); - int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[4]); - vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs1, vecIn1); - vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs2, vecIn2); - pDataDest[8] = pDataSrc[8]; - return 0; -} - -int -foohs16( int16_t * pDataSrc, int16_t * pDataDest) -{ - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; - int16x8_t vecIn1 = vldrhq_s16 ((int16_t const *) pDataSrc); - int16x8_t vecIn2 = vldrhq_s16 ((int16_t const *) &pDataSrc[8]); - vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs1, vecIn1); - vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs2, vecIn2); - pDataDest[16] = pDataSrc[16]; - return 0; -} - -int -foohs32( int32_t * pDataSrc, int32_t * pDataDest) -{ - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; - int32x4_t vecIn1 = vldrhq_s32 ((int16_t const *) pDataSrc); - int32x4_t vecIn2 = vldrhq_s32 ((int16_t const *) &pDataSrc[4]); - vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1); - vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2); - pDataDest[8] = pDataSrc[8]; - return 0; -} - -int -foods64( int64_t * pDataSrc, int64_t * pDataDest) -{ - const uint64x2_t vecOffs1 = { 0, 1}; - const uint64x2_t vecOffs2 = { 2, 3}; - int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc); - int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[2]); - - vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1); - vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2); - - pDataDest[2] = pDataSrc[2]; - return 0; -} - -/* { dg-final { scan-assembler-times "vstr\[a-z\]" 20 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c deleted file mode 100644 index a51d3a21167..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c +++ /dev/null @@ -1,142 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" - -mve_pred16_t __p; -int -foowu32( uint32_t * pDataSrc, uint32_t * pDataDest) -{ - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; - uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p); - uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[4], __p); - vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs1, vecIn1, __p); - vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs2, vecIn2, __p); - pDataDest[8] = pDataSrc[8]; - return 0; -} - -int -foowf32( float32_t * pDataSrc, float32_t * pDataDest) -{ - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; - float32x4_t vecIn1 = vldrwq_z_f32 ((float32_t const *) pDataSrc, __p); - float32x4_t vecIn2 = vldrwq_z_f32 ((float32_t const *) &pDataSrc[4], __p); - vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs1, vecIn1, __p); - vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs2, vecIn2, __p); - pDataDest[8] = pDataSrc[8]; - return 0; -} - -int -foohu16( uint16_t * pDataSrc, uint16_t * pDataDest) -{ - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; - uint16x8_t vecIn1 = vldrhq_z_u16 ((uint16_t const *) pDataSrc, __p); - uint16x8_t vecIn2 = vldrhq_z_u16 ((uint16_t const *) &pDataSrc[8], __p); - vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs1, vecIn1, __p); - vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs2, vecIn2, __p); - pDataDest[16] = pDataSrc[16]; - return 0; -} - -int -foohu32( uint32_t * pDataSrc, uint32_t * pDataDest) -{ - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; - uint32x4_t vecIn1 = vldrhq_z_u32 ((uint16_t const *) pDataSrc, __p); - uint32x4_t vecIn2 = vldrhq_z_u32 ((uint16_t const *) &pDataSrc[4], __p); - vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1, __p); - vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2, __p); - pDataDest[8] = pDataSrc[8]; - return 0; -} - -int -foohf16( float16_t * pDataSrc, float16_t * pDataDest) -{ - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; - float16x8_t vecIn1 = vldrhq_z_f16 ((float16_t const *) pDataSrc, __p); - float16x8_t vecIn2 = vldrhq_z_f16 ((float16_t const *) &pDataSrc[8], __p); - vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs1, vecIn1, __p); - vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs2, vecIn2, __p); - pDataDest[16] = pDataSrc[16]; - return 0; -} - -int -foodu64( uint64_t * pDataSrc, uint64_t * pDataDest) -{ - const uint64x2_t vecOffs1 = { 0, 1}; - const uint64x2_t vecOffs2 = { 2, 3}; - uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p); - uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[2], __p); - - vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1, __p); - vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2, __p); - - pDataDest[2] = pDataSrc[2]; - return 0; -} - -int -foows32( int32_t * pDataSrc, int32_t * pDataDest) -{ - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; - int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p); - int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[4], __p); - vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs1, vecIn1, __p); - vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs2, vecIn2, __p); - pDataDest[8] = pDataSrc[8]; - return 0; -} - -int -foohs16( int16_t * pDataSrc, int16_t * pDataDest) -{ - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; - int16x8_t vecIn1 = vldrhq_z_s16 ((int16_t const *) pDataSrc, __p); - int16x8_t vecIn2 = vldrhq_z_s16 ((int16_t const *) &pDataSrc[8], __p); - vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs1, vecIn1, __p); - vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs2, vecIn2, __p); - pDataDest[16] = pDataSrc[16]; - return 0; -} - -int -foohs32( int32_t * pDataSrc, int32_t * pDataDest) -{ - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; - int32x4_t vecIn1 = vldrhq_z_s32 ((int16_t const *) pDataSrc, __p); - int32x4_t vecIn2 = vldrhq_z_s32 ((int16_t const *) &pDataSrc[4], __p); - vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1, __p); - vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2, __p); - pDataDest[8] = pDataSrc[8]; - return 0; -} - -int -foods64( int64_t * pDataSrc, int64_t * pDataDest) -{ - const uint64x2_t vecOffs1 = { 0, 1}; - const uint64x2_t vecOffs2 = { 2, 3}; - int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p); - int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[2], __p); - - vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1, __p); - vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2, __p); - - pDataDest[2] = pDataSrc[2]; - return 0; -} - -/* { dg-final { scan-assembler-times "vstr\[a-z\]t" 20 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c deleted file mode 100644 index 8348098f948..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vaddq_m (inactive, a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c deleted file mode 100644 index c34cc98385f..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vaddq_m (inactive, a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c deleted file mode 100644 index 3bb01676947..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vaddq_x (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c deleted file mode 100644 index 66dedc7d7e5..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vaddq_x (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c deleted file mode 100644 index 909ca936492..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vcmpeqq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c deleted file mode 100644 index 8f993af20af..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vcmpeqq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c deleted file mode 100644 index 223cffc17e5..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b) -{ - return vcmpeqq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c deleted file mode 100644 index 81669bd7c60..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b) -{ - return vcmpeqq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c deleted file mode 100644 index 4a4e4b34fde..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vcmpgeq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c deleted file mode 100644 index c406a63aae2..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vcmpgeq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c deleted file mode 100644 index a65ed4421a8..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b) -{ - return vcmpgeq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c deleted file mode 100644 index 2e2fc0170eb..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b) -{ - return vcmpgeq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c deleted file mode 100644 index 08c91a72e05..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vcmpgtq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c deleted file mode 100644 index 0b74482211d..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vcmpgtq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c deleted file mode 100644 index 3b2faeaf64f..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b) -{ - return vcmpgtq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c deleted file mode 100644 index 16862e0209c..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b) -{ - return vcmpgtq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c deleted file mode 100644 index 50e53bdac47..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vcmpleq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c deleted file mode 100644 index b16da273a91..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vcmpleq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c deleted file mode 100644 index 4a4b97312b0..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b) -{ - return vcmpleq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c deleted file mode 100644 index 8d8f1051933..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b) -{ - return vcmpleq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c deleted file mode 100644 index 62ab53fb2ef..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vcmpltq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c deleted file mode 100644 index 55886fccff1..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vcmpltq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c deleted file mode 100644 index cd95daea48c..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b) -{ - return vcmpltq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c deleted file mode 100644 index db76687d53e..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b) -{ - return vcmpltq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c deleted file mode 100644 index 30618e87101..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vcmpneq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c deleted file mode 100644 index 4ecfda6d75c..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vcmpneq_m (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c deleted file mode 100644 index 75a0090fcdc..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float16x8_t a, float16_t b) -{ - return vcmpneq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c deleted file mode 100644 index 11ae14cff56..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -mve_pred16_t -foo1 (float32x4_t a, float32_t b) -{ - return vcmpneq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c deleted file mode 100644 index e47ae6d8e3b..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) -{ - return vfmaq_m (a, b, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c deleted file mode 100644 index 78c39f0b2c9..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) -{ - return vfmaq_m (a, b, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c deleted file mode 100644 index f7867f2c0c3..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t a, float16x8_t b, float16_t c) -{ - return vfmaq (a, b, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c deleted file mode 100644 index f0bc45bfed9..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t a, float32x4_t b, float32_t c) -{ - return vfmaq (a, b, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c deleted file mode 100644 index 4750e108b6d..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) -{ - return vfmasq_m (a, b, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c deleted file mode 100644 index 4a379711386..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) -{ - return vfmasq_m (a, b, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c deleted file mode 100644 index db824512b2b..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t a, float16x8_t b, float16_t c) -{ - return vfmasq (a, b, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c deleted file mode 100644 index 12b1410c008..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t a, float32x4_t b, float32_t c) -{ - return vfmasq (a, b, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c deleted file mode 100644 index 7c2349d1ee4..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16_t -foo1 (float16_t a, float16x8_t b) -{ - return vmaxnmavq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c deleted file mode 100644 index 0deef79487a..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32_t -foo1 (float32_t a, float32x4_t b) -{ - return vmaxnmavq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c deleted file mode 100644 index 56a7ac001f9..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16_t -foo1 (float16_t a, float16x8_t b, mve_pred16_t p) -{ - return vmaxnmavq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c deleted file mode 100644 index 36c10a90633..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32_t -foo1 (float32_t a, float32x4_t b, mve_pred16_t p) -{ - return vmaxnmavq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c deleted file mode 100644 index f60641f5de0..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16_t -foo1 (float16_t a, float16x8_t b) -{ - return vmaxnmvq (23.35, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c deleted file mode 100644 index f8c9f44ac78..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32_t -foo1 (float32_t a, float32x4_t b) -{ - return vmaxnmvq (34.56, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c deleted file mode 100644 index 96820ecab91..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16_t -foo1 (float16_t a, float16x8_t b, mve_pred16_t p) -{ - return vmaxnmvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c deleted file mode 100644 index 826ee8f900a..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32_t -foo1 (float32_t a, float32x4_t b, mve_pred16_t p) -{ - return vmaxnmvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c deleted file mode 100644 index 37d5136edca..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16_t -foo1 (float16_t a, float16x8_t b) -{ - return vminnmavq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c deleted file mode 100644 index 78978d05054..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32_t -foo1 (float32_t a, float32x4_t b) -{ - return vminnmavq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c deleted file mode 100644 index 7170b747a40..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16_t -foo1 (float16_t a, float16x8_t b, mve_pred16_t p) -{ - return vminnmavq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c deleted file mode 100644 index 09559053852..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32_t -foo1 (float32_t a, float32x4_t b, mve_pred16_t p) -{ - return vminnmavq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c deleted file mode 100644 index 132d1a123f8..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16_t -foo1 (float16_t a, float16x8_t b) -{ - return vminnmvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c deleted file mode 100644 index 74909075b09..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32_t -foo1 (float32_t a, float32x4_t b) -{ - return vminnmvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c deleted file mode 100644 index c88c3b74a50..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16_t -foo1 (float16_t a, float16x8_t b, mve_pred16_t p) -{ - return vminnmvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c deleted file mode 100644 index e4db972fc70..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32_t -foo1 (float32_t a, float32x4_t b, mve_pred16_t p) -{ - return vminnmvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c deleted file mode 100644 index c8222c5c7b9..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vmulq_m (inactive, a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c deleted file mode 100644 index 2fae3a7f8fa..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vmulq_m (inactive, a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c deleted file mode 100644 index cef311d981d..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t a, float16_t b) -{ - return vmulq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c deleted file mode 100644 index d6d4b9a0a7c..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t a, float32_t b) -{ - return vmulq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c deleted file mode 100644 index ea4cab03490..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vmulq_x (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c deleted file mode 100644 index a7a54c7c92c..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vmulq_x (a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c deleted file mode 100644 index 608dd30788e..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo (float16_t a, float16x8_t b) -{ - return vsetq_lane (23.26, b, 0); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c deleted file mode 100644 index c5f5db7f28d..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo (float32_t a, float32x4_t b) -{ - return vsetq_lane (23.34, b, 0); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c deleted file mode 100644 index f3e19613e7e..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vsubq_m (inactive, a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c deleted file mode 100644 index 4b5cd90c9ed..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vsubq_m (inactive, a, 23.23, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c deleted file mode 100644 index f8832546f54..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo1 (float16x8_t a, float16_t b) -{ - return vsubq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c deleted file mode 100644 index 88d9675540d..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo1 (float32x4_t a, float32_t b) -{ - return vsubq (a, 23.23); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c deleted file mode 100644 index b3a67bb43eb..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float16x8_t -foo (float16x8_t a, float16_t b, mve_pred16_t p) -{ - return vsubq_x_n_f16 (a, 23.23, p); -} - - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c deleted file mode 100644 index dcb2425397b..00000000000 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ - -#include "arm_mve.h" -float32x4_t -foo (float32x4_t a, float32_t b, mve_pred16_t p) -{ - return vsubq_x_n_f32 (a, 23.23, p); -} - - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ From patchwork Thu May 18 10:59:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit 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Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT056.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB8698 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Stam Markianos-Wright via Gcc-patches From: Stamatis Markianos-Wright Reply-To: Stam Markianos-Wright Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766229564599402318?= X-GMAIL-MSGID: =?utf-8?q?1766229564599402318?= Hi all, This is a simple testsuite tidy-up patch, addressing to types of errors: * The vcmp vector-scalar tests failing due to the compiler's preference of vector-vector comparisons, over vector-scalar comparisons. This is due to the lack of cost model for MVE and the compiler not knowing that the RTL vec_duplicate is free in those instructions. For now, we simply XFAIL these checks. * The tests for pr108177 had strict usage of q0 and r0 registers, meaning that they would FAIL with -mfloat-abi=softf. The register checks have now been relaxed. A couple of these run-tests also had incosistent use of integer MVE with floating point vectors, so I've now changed these to use FP MVE. gcc/testsuite/ChangeLog: PR target/109697 * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: XFAIL check. * gcc.target/arm/mve/pr108177-1.c: Relax registers. * gcc.target/arm/mve/pr108177-10.c: Relax registers. * gcc.target/arm/mve/pr108177-11.c: Relax registers. * gcc.target/arm/mve/pr108177-12.c: Relax registers. * gcc.target/arm/mve/pr108177-13.c: Relax registers. * gcc.target/arm/mve/pr108177-13-run.c: use mve_fp * gcc.target/arm/mve/pr108177-14.c: Relax registers. * gcc.target/arm/mve/pr108177-14-run.c: use mve_fp * gcc.target/arm/mve/pr108177-2.c: Relax registers. * gcc.target/arm/mve/pr108177-3.c: Relax registers. * gcc.target/arm/mve/pr108177-4.c: Relax registers. * gcc.target/arm/mve/pr108177-5.c: Relax registers. * gcc.target/arm/mve/pr108177-6.c: Relax registers. * gcc.target/arm/mve/pr108177-7.c: Relax registers. * gcc.target/arm/mve/pr108177-8.c: Relax registers. * gcc.target/arm/mve/pr108177-9.c: Relax registers. --- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/pr108177-1.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-10.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-11.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-12.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c | 2 +- gcc/testsuite/gcc.target/arm/mve/pr108177-13.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c | 2 +- gcc/testsuite/gcc.target/arm/mve/pr108177-14.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-2.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-3.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-4.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-5.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-6.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-7.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-8.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-9.c | 4 ++-- 40 files changed, 54 insertions(+), 54 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c index dc63c527743..9f8111438a1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c index 8c5d185ca22..799d3bcdab1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c index 2296f3e1655..16c3617c104 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c index 1d870428c55..2f84d751c53 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c index 8b8610b0617..6cfe7338fce 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c index 409c9de58ba..362e830c908 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c index c3b1736bfa1..583beb97849 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c index 3728c738b54..db7f1877d73 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c index 4e9a346ab14..978bd7d4b52 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c index 2cf1d1ab0b6..66b6d8b0056 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c index 89d8e2b9109..9c5f1f2f5c8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c index 482ac094cf3..2723aa7f98f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c index 085b8277736..5712db2ceef 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c index a62a73ff24c..f7a25af8574 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c index f05c9d24643..8cd28fb1681 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c index 4f6276484ba..1d1f4bf0e58 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c index e71dcb8f174..bf77a808064 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c index c6fdb08d8ae..f9f091cd9b3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c index 4f1ac3c0977..d22ea1aca30 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c index e36d8a95a85..83beca964d6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c index 7262503eee6..abe1abfed2a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c index 71d878dff9f..ca55fe2f76c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c index 3f997e8e487..77bac757d68 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c index 9917a95ffb7..352afa798d1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b) } /* -**foo2: +**foo2: { xfail *-*-* } ** ... ** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ** ... diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c index 2d42062bc8e..8383b4d9e3a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrbt.8 q0, \[r0\] +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrbt.8 q0, \[r0\] +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c index 4db594f588f..7b1cd3711d8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrht.32 q0, \[r0\] +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrht.32 q0, \[r0\] +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c index 329fcb33eeb..e6ae8524052 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrwt.32 q0, \[r0\] +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrwt.32 q0, \[r0\] +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c index 3f7c5b2a4c1..e352508e07e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrwt.32 q0, \[r0\] +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrwt.32 q0, \[r0\] +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c index 2e731ee3824..34a5e7d35e7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_mve_hw } */ /* { dg-options "-O2" } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ #include "pr108177-13.c" diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c index 2f82228d8f6..13afa92771d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrht.16 q0, \[r0\] +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrht.16 q0, \[r0\] +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c index 3cebcf5bbcd..a2dc3338dd3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_mve_hw } */ /* { dg-options "-O2" } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ #include "pr108177-14.c" diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c index ba6196b7994..a093cd4b708 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrwt.32 q0, \[r0\] +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrwt.32 q0, \[r0\] +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c index 52c8d87ccc8..da4181ff0b7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrbt.8 q0, \[r0\] +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrbt.8 q0, \[r0\] +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c index ac89e7ea883..9604fd100e6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrbt.16 q0, \[r0\] +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrbt.16 q0, \[r0\] +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c index dc4f7ddab07..07ba37b466c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrbt.16 q0, \[r0\] +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrbt.16 q0, \[r0\] +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c index d1dfd328d66..72c1dd5a4d6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrbt.32 q0, \[r0\] +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrbt.32 q0, \[r0\] +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c index fa70dde9eeb..3fedc9b98c8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrbt.32 q0, \[r0\] +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrbt.32 q0, \[r0\] +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c index 73cd8605171..c3b440c3b6c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrht.16 q0, \[r0\] +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrht.16 q0, \[r0\] +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c index 187c2b3f4ce..5c450b81d1c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrht.16 q0, \[r0\] +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrht.16 q0, \[r0\] +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c index caecd18a881..b5084efcc00 100644 --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c @@ -7,9 +7,9 @@ /* ** test: **... -** vstrht.32 q0, \[r0\] +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... -** vstrht.32 q0, \[r0\] +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] **... */ From patchwork Thu May 18 10:59:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stamatis Markianos-Wright X-Patchwork-Id: 95780 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp403739vqo; Thu, 18 May 2023 04:05:29 -0700 (PDT) X-Google-Smtp-Source: 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Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT053.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9546 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Stam Markianos-Wright via Gcc-patches From: Stamatis Markianos-Wright Reply-To: Stam Markianos-Wright Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766229729051397865?= X-GMAIL-MSGID: =?utf-8?q?1766229729051397865?= These newly updated tests were rewritten by Andrea. Some of them needed further manual fixing as follows: * The #shift immediate value not in the check-function-bodies as expected * The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In this case the test rewritten from the ACLE had the lsr+and pattern, but the compiler was able to optimise to ubfx. Hence I've changed the test to now match on ubfx. * Added a separate test to check shift on constants being optimised to movs. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/srshr.c: Update shift value. * gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value. * gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value. * gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value. * gcc.target/arm/mve/intrinsics/urshr.c: Update shift value. * gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value. * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx. * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx. * gcc.target/arm/mve/mve_const_shifts.c: New test. --- .../gcc.target/arm/mve/intrinsics/srshr.c | 2 +- .../gcc.target/arm/mve/intrinsics/srshrl.c | 2 +- .../gcc.target/arm/mve/intrinsics/uqshl.c | 14 +------ .../gcc.target/arm/mve/intrinsics/uqshll.c | 14 +------ .../gcc.target/arm/mve/intrinsics/urshr.c | 4 +- .../gcc.target/arm/mve/intrinsics/urshrl.c | 4 +- .../arm/mve/intrinsics/vadciq_m_s32.c | 8 +--- .../arm/mve/intrinsics/vadciq_m_u32.c | 8 +--- .../arm/mve/intrinsics/vadciq_s32.c | 8 +--- .../arm/mve/intrinsics/vadciq_u32.c | 8 +--- .../arm/mve/intrinsics/vadcq_m_s32.c | 8 +--- .../arm/mve/intrinsics/vadcq_m_u32.c | 8 +--- .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 8 +--- .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 8 +--- .../arm/mve/intrinsics/vsbciq_m_s32.c | 8 +--- .../arm/mve/intrinsics/vsbciq_m_u32.c | 8 +--- .../arm/mve/intrinsics/vsbciq_s32.c | 8 +--- .../arm/mve/intrinsics/vsbciq_u32.c | 8 +--- .../arm/mve/intrinsics/vsbcq_m_s32.c | 8 +--- .../arm/mve/intrinsics/vsbcq_m_u32.c | 8 +--- .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 8 +--- .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 8 +--- .../gcc.target/arm/mve/mve_const_shifts.c | 41 +++++++++++++++++++ 23 files changed, 81 insertions(+), 128 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c index 94e3f42fd33..734375d58c0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ int32_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c index 65f28ccbfde..a91943c38a0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ int64_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c index b23c9d97ba6..462531cad54 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint32_t @@ -21,18 +21,6 @@ foo (uint32_t value) return uqshl (value, 1); } -/* -**foo1: -** ... -** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|) -** ... -*/ -uint32_t -foo1 () -{ - return uqshl (1, 1); -} - #ifdef __cplusplus } #endif diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c index 6a3d08eea75..6fa97a561e3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint64_t @@ -21,18 +21,6 @@ foo (uint64_t value) return uqshll (value, 1); } -/* -**foo1: -** ... -** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|) -** ... -*/ -uint64_t -foo1 () -{ - return uqshll (1, 1); -} - #ifdef __cplusplus } #endif diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c index 23afcb8da4c..ff97bf5c473 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint32_t @@ -24,7 +24,7 @@ foo (uint32_t value) /* **foo1: ** ... -** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint32_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c index 8014371f47f..ff6a69d300f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint64_t @@ -24,7 +24,7 @@ foo (uint64_t value) /* **foo1: ** ... -** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint64_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c index b262bf94d39..a6a059a19e9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c @@ -20,9 +20,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c index d349caed36a..942111339f0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c @@ -20,9 +20,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c index 5166993a355..3b68bb6ac33 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c @@ -16,9 +16,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c index 080bd61d238..82228491043 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c @@ -16,9 +16,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c index 45e6ff03623..0d4cb779254 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c @@ -26,9 +26,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c index 54f141b2093..a0ba6825d8c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c @@ -26,9 +26,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1 ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c index 06d5bae09da..47f5f22dde9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c @@ -22,9 +22,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c index e2111cfd16a..55a961be217 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c @@ -22,9 +22,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c index 66a5c4c9da3..dcbaef1a571 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c @@ -20,9 +20,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c index 9306f152cde..08f67f665c1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c @@ -20,9 +20,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c index 0b5040f0b2a..803246c3235 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c @@ -16,9 +16,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c index df211a64daa..22d2b4355bc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c @@ -16,9 +16,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c index 217cfa7ac21..7a332610c69 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c @@ -26,9 +26,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c index dad04d05d68..60902196502 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c @@ -26,9 +26,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1 ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c index cd033640bcc..523fa32ee0d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c @@ -22,9 +22,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c index 6ca0c753b5e..ff720fd2df5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c @@ -22,9 +22,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c new file mode 100644 index 00000000000..b17f9f36057 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c @@ -0,0 +1,41 @@ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_mve.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo11: +** ... +** movs r0, #2 +** ... +*/ +uint32_t +foo11 () +{ + return uqshl (1, 1); +} + +/* +**foo12: +** ... +** movs r0, #2 +** movs r1, #0 +** ... +*/ +uint64_t +foo12 () +{ + return uqshll (1, 1); +} + +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */