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Fixes: 9a1bf58ccd44 ("usb: misc: eud: Add driver support for Embedded USB Debugger(EUD)") Reviewed-by: Konrad Dybcio Acked-by: Manivannan Sadhasivam Signed-off-by: Bhupesh Sharma --- Documentation/ABI/testing/sysfs-driver-eud | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-driver-eud b/Documentation/ABI/testing/sysfs-driver-eud index 83f3872182a4..2bab0db2d2f0 100644 --- a/Documentation/ABI/testing/sysfs-driver-eud +++ b/Documentation/ABI/testing/sysfs-driver-eud @@ -1,4 +1,4 @@ -What: /sys/bus/platform/drivers/eud/.../enable +What: /sys/bus/platform/drivers/qcom_eud/.../enable Date: February 2022 Contact: Souradeep Chowdhury Description: From patchwork Wed May 17 21:17:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 95564 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp64956vqo; Wed, 17 May 2023 14:33:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6G2EfEgPu9Xo6YI6j8h2MQ4iMtSJXh2scaxjpQ87EXGeTMGxpl37EBgNRPJoUrDYNUTIc0 X-Received: by 2002:a05:6a20:2451:b0:104:dcea:2227 with SMTP id t17-20020a056a20245100b00104dcea2227mr24797514pzc.2.1684359201023; Wed, 17 May 2023 14:33:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684359201; cv=none; d=google.com; s=arc-20160816; b=myitXbT5a/M8XJdUBwwjyyu7DLCYxr1wr2FRFAL+6wN+N27P8PGqEENIuKjEfjL9Q7 MBuvgnChCJpcX0da7JXh6budJcrw9HjJigSEC4YWbSeJopLvL6Pb7F/458+2PgYmFI2h 00LEnQJBaSllPJNZ3HWVS/mic08Oigr2c+DyzJIFnVji4uI7fGbonDzKKcZkrccQCg5W YyZAS0zI2zHeleU8j/8HlmyCRnyerTBCXwBLk1Nd8r9lCuyLqogafvPVu6junXre9U5O jviUYRGBiAYuduZVu1TCaTq8ZWpUCpfdsDB+egRZSndKutfWp6NgtTqVvSxJYQbTy/Iz KYIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Q9+WkMxaCFyRvz0ZQf19zyMmoq6vin0MgQ/wuGkS8c8=; b=pU5og5mLsfW9sAgEIvf593McGfWCRf4bDUaOqzS+rFCVhjHym2TSXnzOHZRfpfuLDM WJxZ2hW4QNdGdiDKgDEK1bnCxWOVr33fwm2PbYq4Zx4N5MypQ5/9rSy3omldPy7Sczs+ 1e2/SP4ZwVIzuYM8SZpK3agG8BjTaHNF50adzs6EBpgxv7m3mdxrC0QFm24aqPwwmGlV 0+gxi4NxWNxHHnIfnSJxbbI83Ai5wMvjXfofPvGn2W4UJAcchlgJBBfi3IWuN2AZF5zt AK3YFYs/j+7R2jPzdcH6PcvHHYFuZyu6IOMO+5ecjHBHJWcXMZgSZCtUtExm8prGSDIt YIyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bV7CpqoX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' needs to be set first to 'enable' the eud module. So, update the dt-bindings to accommodate the third register property (TCSR Base) required by the driver on these SoCs. Signed-off-by: Bhupesh Sharma --- .../bindings/soc/qcom/qcom,eud.yaml | 42 +++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index f2c5ec7e6437..9c64b5d9504f 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -18,12 +18,16 @@ properties: items: - enum: - qcom,sc7280-eud + - qcom,sm6115-eud - const: qcom,eud reg: - items: - - description: EUD Base Register Region - - description: EUD Mode Manager Register + minItems: 2 + maxItems: 3 + + reg-names: + minItems: 2 + maxItems: 3 interrupts: description: EUD interrupt @@ -52,6 +56,38 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-eud + then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: eud-base + - const: eud-mode-mgr + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6115-eud + then: + properties: + reg: + maxItems: 3 + reg-names: + items: + - const: eud-base + - const: eud-mode-mgr + - const: tcsr-base + examples: - | eud@88e0000 { From patchwork Wed May 17 21:17:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 95566 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp66042vqo; Wed, 17 May 2023 14:35:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7f3AzQ2bg5KKftgV0x5vBb/Ms6AnC/TeO72xosC9PQqHhyOmAtFBFreaO3QR8V4c2YT5/D X-Received: by 2002:a05:6a20:5493:b0:103:d25b:36c7 with SMTP id i19-20020a056a20549300b00103d25b36c7mr30859109pzk.35.1684359339402; Wed, 17 May 2023 14:35:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684359339; cv=none; d=google.com; s=arc-20160816; b=m9lzlYlL8bKz1rt+oSnTMEmnJUQwNrxQ78wEP/75IbwDwC7hcenBrEtYA4RmbKcYJ7 45yy6402IQYnBe6QzJAIRW7H4rccYJRrccgWk4P/Ix0lbdCr5WdJYpUsFR7ggM7wVBNE UC+F269sdciOZRmztO5+ulwRyPs7XBWnPREiJLhhNQb7eLsNmWm14jE9oBiOguP+EqtG OZ4yZYKVvMhOr942mJuNcoMPq6OgP9W+8AxL7E1ORp9qgjQAW97GPxaNJ6EUQK2cISid 7IpaItugHMomyNn8ZsIeIwWaqa1Y/5bi1JkDKhDB94wjYAD6OXD+SWn7y4Iic6D3fNZN kQvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zF+7RIYO2NHXGA6P5+vCgbOZX4fdEtvPnQSZuYHbKNI=; b=WNtlD5xvssIs6lcXIizAMMMqpr2uCMVNfAyBNMiajk8vCw1wbZmEXCP2PtzgRUqypz fRrW2rx7EKEUIaK1ItBxGD06nXuX5knDMpN9X8mqL3MU53F+1vMAzzO+J5ZRUSvf25CF 65VS/D5JVZ8TnD0guDxetTl7Y0P7JoMWTwmosrpPH1GTTg5seAqvQMtk0cJFroJ3cYSG 3PT5MOv+OLSUmPe0NlAVDi3VqMZMFc8PUWhhxQsV9tcQnZw1WP0kQjpoua+gaXXOq3pG FjfcxFBBhQ/XwCfTvGEaaD6KI964fwUoftTnS6gSCjSlXAuILWDY/MCek8qiyWFt8NOm 34Qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ww4ish6t; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Bhupesh Sharma --- drivers/usb/misc/qcom_eud.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index b7f13df00764..74f2aeaccdcb 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -22,10 +22,10 @@ #define EUD_REG_VBUS_INT_CLR 0x0080 #define EUD_REG_CSR_EUD_EN 0x1014 #define EUD_REG_SW_ATTACH_DET 0x1018 -#define EUD_REG_EUD_EN2 0x0000 +#define EUD_REG_EUD_EN2 0x0000 #define EUD_ENABLE BIT(0) -#define EUD_INT_PET_EUD BIT(0) +#define EUD_INT_PET_EUD BIT(0) #define EUD_INT_VBUS BIT(2) #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) From patchwork Wed May 17 21:17:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 95565 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp65752vqo; Wed, 17 May 2023 14:35:01 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5hlQFZELoLgJeVBe48KpPHu2dnDyBoe5JfF4Yau5MqiZLNn9zs1p2e9ZgBPaNzwIYtrn6T X-Received: by 2002:a17:90a:d517:b0:24e:56e4:9718 with SMTP id t23-20020a17090ad51700b0024e56e49718mr308328pju.15.1684359301161; Wed, 17 May 2023 14:35:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684359301; cv=none; d=google.com; s=arc-20160816; b=KQG10GPc+nECm/i/rc+s6z/+8/cCtTy7jUkG1rTfpmO63tuRtJY6PT2cju+6cqKEwP Ite7GZl2kkI6PZzjIxuSmGzxl5Vo0EiLH38O+2H1Q1KHRqilItL5aBD8J2aAnCIN+p5r +ubZwHk75IDHJGYqkQs//Ot+5eu2As7KuOfghTM88Mjv1pSWnYprILPadHDCZqgVZIQs eEi02//RT0wgZRdAAEa4E5X+60Ncro+8xbF7xqEgv1qKBmY8vX5LnouCH56xNaG/Xgvp K+pfqO0672ywv59ItXoepxsh62wXtqsOCIGHVbihYnlgVfZVLfsnrap7guFULtOIr/Dm WoUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Szw6rk2+gFj7vYEVvOOd5Ny6+rbVHSROGpb0XG2hv4I=; b=WJ9pJjyeC9SmX17BHTG7Nk70qZ84EqD6jAiT0hKGToajldW4ZuXEAeas/rPQL2ogF/ ZJW5DTHI4rgfF+AZVjv8LqveMW9neemceUaPD3F9sLCf9nq7ADzg9oa6tcemfuBSCHc/ FRgoYkrC1Xm+Gc9aLV7ue6XF9gmDuZwv09iCMTRHaS8wJynp/StGeTw0WQDLliVY+8Hv c4HVDD9B0sVh9MBGMVNLsL5fsMKQdltJ8VFrNRQoSqM+TQszM9lw1+q4ccddr6F7d1Xx t6Vmhi1BxjTI1PYchmUVwOLIKWLDXPSmTMrp65nDF3susFXHgVMVPItAnUkMcXpnx2ut 74yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ziTQjl4K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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On some SoCs (like the SM6115 / SM4250 SoC), the mode manager needs to be accessed only via the secure world (through 'scm' calls). Also, the enable bit inside 'tcsr_check_reg' needs to be set first to set the eud in 'enable' mode on these SoCs. Signed-off-by: Bhupesh Sharma --- drivers/usb/misc/Kconfig | 2 +- drivers/usb/misc/qcom_eud.c | 65 ++++++++++++++++++++++++++++++++++--- 2 files changed, 61 insertions(+), 6 deletions(-) diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig index 99b15b77dfd5..51eb5140caa1 100644 --- a/drivers/usb/misc/Kconfig +++ b/drivers/usb/misc/Kconfig @@ -146,7 +146,7 @@ config USB_APPLEDISPLAY config USB_QCOM_EUD tristate "QCOM Embedded USB Debugger(EUD) Driver" - depends on ARCH_QCOM || COMPILE_TEST + depends on (ARCH_QCOM && QCOM_SCM) || COMPILE_TEST select USB_ROLE_SWITCH help This module enables support for Qualcomm Technologies, Inc. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 74f2aeaccdcb..6face21b7fb7 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -11,9 +11,11 @@ #include #include #include +#include #include #include #include +#include #include #define EUD_REG_INT1_EN_MASK 0x0024 @@ -30,15 +32,25 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) +#define EUD_EN2_EN BIT(0) +#define EUD_EN2_DISABLE (0) +#define TCSR_CHECK_EN BIT(0) + +struct eud_soc_cfg { + u32 tcsr_check_offset; +}; + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; + const struct eud_soc_cfg *eud_cfg; void __iomem *base; void __iomem *mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + phys_addr_t secure_mode_mgr; }; static int enable_eud(struct eud_chip *priv) @@ -46,7 +58,11 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, EUD_EN2_EN); + else + writel(EUD_EN2_EN, priv->mode_mgr + EUD_REG_EUD_EN2); return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } @@ -54,7 +70,11 @@ static int enable_eud(struct eud_chip *priv) static void disable_eud(struct eud_chip *priv) { writel(0, priv->base + EUD_REG_CSR_EUD_EN); - writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, EUD_EN2_DISABLE); + else + writel(EUD_EN2_DISABLE, priv->mode_mgr + EUD_REG_EUD_EN2); } static ssize_t enable_show(struct device *dev, @@ -178,6 +198,8 @@ static void eud_role_switch_release(void *data) static int eud_probe(struct platform_device *pdev) { struct eud_chip *chip; + struct resource *res; + phys_addr_t tcsr_check; int ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); @@ -200,9 +222,37 @@ static int eud_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); - chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(chip->mode_mgr)) - return PTR_ERR(chip->mode_mgr); + /* + * EUD block on a few Qualcomm SoCs needs secure register access. + * Check for the same. + */ + if (of_device_is_compatible(chip->dev->of_node, "qcom,sm6115-eud")) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get secure_mode_mgr reg base\n"); + + chip->secure_mode_mgr = res->start; + } else { + chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->mode_mgr)) + return PTR_ERR(chip->mode_mgr); + } + + /* Check for any SoC specific config data */ + chip->eud_cfg = of_device_get_match_data(&pdev->dev); + if (chip->eud_cfg) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tcsr-base"); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get tcsr reg base\n"); + + tcsr_check = res->start + chip->eud_cfg->tcsr_check_offset; + + ret = qcom_scm_io_writel(tcsr_check, TCSR_CHECK_EN); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to write tcsr check reg\n"); + } chip->irq = platform_get_irq(pdev, 0); ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq, @@ -230,8 +280,13 @@ static int eud_remove(struct platform_device *pdev) return 0; } +static const struct eud_soc_cfg sm6115_eud_cfg = { + .tcsr_check_offset = 0x25018, +}; + static const struct of_device_id eud_dt_match[] = { { .compatible = "qcom,sc7280-eud" }, + { .compatible = "qcom,sm6115-eud", .data = &sm6115_eud_cfg }, { } }; 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The node contains EUD base register region, EUD mode manager register region and TCSR Base register region along with the interrupt entry. Also add the typec connector node for EUD which is attached to EUD node via port. EUD is also attached to DWC3 node via port. To enable the role switch, we need to set dr_mode = "otg" property for 'usb_dwc3' sub-node in the board dts file. Also the EUD device can be enabled on a board once linux is boot'ed by setting: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/../enable Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 50 ++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index f67863561f3f..92a82d7172ca 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -180,6 +180,18 @@ core3 { }; }; + eud_typec: connector { + compatible = "usb-c-connector"; + + ports { + port@0 { + con_eud: endpoint { + remote-endpoint = <&eud_con>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-sm6115", "qcom,scm"; @@ -647,6 +659,37 @@ gcc: clock-controller@1400000 { #power-domain-cells = <1>; }; + eud: eud@1610000 { + compatible = "qcom,sm6115-eud", "qcom,eud"; + reg = <0x0 0x01610000 0x0 0x2000>, + <0x0 0x01612000 0x0 0x1000>, + <0x0 0x003c0000 0x0 0x40000>; + reg-names = "eud-base", "eud-mode-mgr", "tcsr-base"; + interrupts = ; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + eud_con: endpoint { + remote-endpoint = <&con_eud>; + }; + }; + }; + }; + usb_hsphy: phy@1613000 { compatible = "qcom,sm6115-qusb2-phy"; reg = <0x0 0x01613000 0x0 0x180>; @@ -1144,6 +1187,13 @@ usb_dwc3: usb@4e00000 { snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + usb-role-switch; + + port { + usb2_role_switch: endpoint { + remote-endpoint = <&eud_ep>; + }; + }; }; }; From patchwork Wed May 17 21:17:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 95568 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp66713vqo; Wed, 17 May 2023 14:37:14 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6bE5WYinfsxPxxVc1cAvZZbt2OfFWZJwnnmQt1eSY0fl7FyKKPFCHJDpzTCFsvUizqYXVO X-Received: by 2002:a05:6a21:339a:b0:106:a78f:be22 with SMTP id yy26-20020a056a21339a00b00106a78fbe22mr3604166pzb.31.1684359434171; Wed, 17 May 2023 14:37:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684359434; cv=none; d=google.com; s=arc-20160816; b=Fotn5/GW9cG7blhEwa/7ttsH81W1/8n8jLhfvOITuHx0060r9meOa9/vE0bWmNK2ks XAq+tlc0YGmP05ifTms/Ku0PXXofs0KwzxGz2J0bxgpUa4bH5vkN6KswFiE6rnaG3Ud7 BvdxkrQIf4x0N437DpWAXdjz8BAesfIj0EptA1DascHpT9NlEka5le1IWFRnb6zF9fGJ qtMLRODRLD1AfC2fkyV1WmrM5kk5wBAkKQl2PxFzCg8SbOvPugnwcc9V5vhw8+5o3Q3G a6oymZEPRljbe7FrCA3OBDMBu5k/0WRNHVw4pOaPuxRJlieJAqpk7dm1e2BHB7uK8CiK cTdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nsC+YIR9GPviDXHSlkV5AONTmzt9XmYN5GUXlOjFZyw=; b=vlQlW5Mn2S1+5+FFeG1QyFft8afoVwzKrvUdbnhhh7xXqqNbcCF8jOPih2SW3X9u4C KpxwB+0FbKyNzilF5qHhb3YU1dk5zqVR1B7YRFqRCTNkl5aGg7kiTR9YCcBXStlqX2fk Pw9NaBkCYcHlbBKzd3YNVDIGUjQ3mN5MWQQzl0qaPx4bMKDr9g05Rxz0SK7LlrAGf5b3 tf3YTCRc6Egn8nS36vybErBJ1LZpzK9F5rz0aA5paIuk9A/+sc9VeErDtYiVAVkrJGfK XdoPkwbqbCAvfM1BDRBtvwjK2T1WerEOTTtmTzsJRER/zDUprp1/Gd9IFUizAbqjYtSI P/jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mLEnL4+9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Now, the EUD debug peripheral can be enabled by executing: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/1610000.eud/enable Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 27 +++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 1a0776a0cfd0..0ce72f1ebc10 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -30,6 +30,10 @@ vph_pwr: vph-pwr-regulator { }; }; +&eud { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -253,7 +257,28 @@ &usb { &usb_dwc3 { maximum-speed = "super-speed"; - dr_mode = "peripheral"; + + /* + * There is only one USB DWC3 controller on QRB4210 board and it is connected + * via a DIP Switch: + * - to either an USB - C type connector or an USB - A type connector + * (via a GL3590-S hub), and + * - to either an USB - A type connector (via a GL3590-S hub) or a connector + * for further connection with a mezzanine board. + * + * All of the above hardware muxes would allow us to hook things up in + * different ways to some potential benefit for static configurations (for e.g. + * on one hand we can have two USB - A type connectors and a USB - Ethernet + * connection available and on the other we can use the USB - C type in + * peripheral mode). + * + * Note that since the USB - C type can be used only in peripehral mode, + * so hardcoding the mode to 'peripheral' here makes sense. + * + * However since we want to use the EUD debug device, we set the mode as + * 'otg' here. + */ + dr_mode = "otg"; }; &usb_hsphy {